gem5 v24.1.0.1
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sdma_engine.hh
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1/*
2 * Copyright (c) 2021 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright notice,
12 * this list of conditions and the following disclaimer in the documentation
13 * and/or other materials provided with the distribution.
14 *
15 * 3. Neither the name of the copyright holder nor the names of its
16 * contributors may be used to endorse or promote products derived from this
17 * software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32#ifndef __DEV_AMDGPU_SDMA_ENGINE_HH__
33#define __DEV_AMDGPU_SDMA_ENGINE_HH__
34
35#include "base/bitunion.hh"
40#include "params/SDMAEngine.hh"
41
42namespace gem5
43{
44
49{
55
57 {
64 bool _valid;
71 bool _priv = true; // Only used for RLC queues. True otherwise.
72 bool _static = false;
73 public:
74 SDMAQueue() : _rptr(0), _wptr(0), _valid(false), _processing(false),
75 _parent(nullptr), _ib(nullptr), _type(SDMAGfx), _mqd(nullptr) {}
76
77 Addr base() { return _base; }
78 Addr rptr() { return _base + _rptr; }
79 Addr getRptr() { return _rptr; }
80 Addr wptr() { return _base + _wptr; }
81 Addr getWptr() { return _wptr; }
82 Addr size() { return _size; }
85 bool valid() { return _valid; }
86 bool processing() { return _processing; }
87 SDMAQueue* parent() { return _parent; }
88 SDMAQueue* ib() { return _ib; }
89 SDMAType queueType() { return _type; }
90 SDMAQueueDesc* getMQD() { return _mqd; }
92 bool priv() { return _priv; }
93 bool isStatic() { return _static; }
94
95 void base(Addr value) { _base = value; }
96
97 void
98 incRptr(uint32_t value)
99 {
100 _rptr = (_rptr + value) % _size;
101 _global_rptr += value;
102 }
103
104 void
105 rptr(Addr value)
106 {
107 _rptr = value;
108 _global_rptr = value;
109 }
110
111 void
113 {
114 _wptr = value % _size;
115 }
116
117 void wptr(Addr value) { _wptr = value; }
118
119 void size(Addr value) { _size = value; }
120 void rptrWbAddr(Addr value) { _rptr_wb_addr = value; }
121 void valid(bool v) { _valid = v; }
122 void processing(bool value) { _processing = value; }
123 void parent(SDMAQueue* q) { _parent = q; }
124 void ib(SDMAQueue* ib) { _ib = ib; }
126 void setMQD(SDMAQueueDesc *mqd) { _mqd = mqd; }
127 void setMQDAddr(Addr mqdAddr) { _mqd_addr = mqdAddr; }
128 void setPriv(bool priv) { _priv = priv; }
130 };
131
132 /* SDMA Engine ID */
133 int id;
143
144 /* Gfx ring buffer registers */
145 uint64_t gfxBase;
146 uint64_t gfxRptr;
147 uint64_t gfxDoorbell;
149 uint64_t gfxWptr;
150 /* Page ring buffer registers */
151 uint64_t pageBase;
152 uint64_t pageRptr;
153 uint64_t pageDoorbell;
155 uint64_t pageWptr;
156
159
160 /* processRLC will select the correct queue for the doorbell */
161 std::array<Addr, 2> rlcInfo{};
162 void processRLC0(Addr wptrOffset);
163 void processRLC1(Addr wptrOffset);
164
167
168 public:
169 SDMAEngine(const SDMAEngineParams &p);
170
171 void setGPUDevice(AMDGPUDevice *gpu_device);
172
173 void setId(int _id) { id = _id; }
174 int getId() const { return id; }
178 int getIHClientId(int _id);
179
183 Addr getGARTAddr(Addr addr) const;
184 TranslationGenPtr translate(Addr vaddr, Addr size) override;
185
191 Addr getDeviceAddress(Addr raw_addr);
192
196 Tick write(PacketPtr pkt) override { return 0; }
197 Tick read(PacketPtr pkt) override { return 0; }
198 AddrRangeList getAddrRanges() const override;
199 void serialize(CheckpointOut &cp) const override;
200 void unserialize(CheckpointIn &cp) override;
201
206 void processGfx(Addr wptrOffset);
207 void processPage(Addr wptrOffset);
208 void processRLC(Addr doorbellOffset, Addr wptrOffset);
209
218 void decodeNext(SDMAQueue *q);
219
225 void decodeHeader(SDMAQueue *q, uint32_t data);
226
230 void write(SDMAQueue *q, sdmaWrite *pkt);
231 void writeReadData(SDMAQueue *q, sdmaWrite *pkt, uint32_t *dmaBuffer);
232 void writeDone(SDMAQueue *q, sdmaWrite *pkt, uint32_t *dmaBuffer);
233 void writeCleanup(uint32_t *dmaBuffer);
234 void copy(SDMAQueue *q, sdmaCopy *pkt);
235 void copyReadData(SDMAQueue *q, sdmaCopy *pkt, uint8_t *dmaBuffer);
236 void copyDone(SDMAQueue *q, sdmaCopy *pkt, uint8_t *dmaBuffer);
237 void copyCleanup(uint8_t *dmaBuffer);
238 void indirectBuffer(SDMAQueue *q, sdmaIndirectBuffer *pkt);
239 void fence(SDMAQueue *q, sdmaFence *pkt);
240 void fenceDone(SDMAQueue *q, sdmaFence *pkt);
241 void trap(SDMAQueue *q, sdmaTrap *pkt);
242 void srbmWrite(SDMAQueue *q, sdmaSRBMWriteHeader *header,
243 sdmaSRBMWrite *pkt);
244 void pollRegMem(SDMAQueue *q, sdmaPollRegMemHeader *header,
245 sdmaPollRegMem *pkt);
247 sdmaPollRegMem *pkt, uint32_t dma_buffer, int count);
248 bool pollRegMemFunc(uint32_t value, uint32_t reference, uint32_t func);
249 void ptePde(SDMAQueue *q, sdmaPtePde *pkt);
250 void ptePdeDone(SDMAQueue *q, sdmaPtePde *pkt, uint64_t *dmaBuffer);
251 void ptePdeCleanup(uint64_t *dmaBuffer);
252 void atomic(SDMAQueue *q, sdmaAtomicHeader *header, sdmaAtomic *pkt);
253 void atomicData(SDMAQueue *q, sdmaAtomicHeader *header, sdmaAtomic *pkt,
254 uint64_t *dmaBuffer);
255 void atomicDone(SDMAQueue *q, sdmaAtomicHeader *header, sdmaAtomic *pkt,
256 uint64_t *dmaBuffer);
257 void constFill(SDMAQueue *q, sdmaConstFill *pkt, uint32_t header);
258 void constFillDone(SDMAQueue *q, sdmaConstFill *pkt, uint8_t *fill_data);
259
267
271 uint64_t getGfxBase() { return gfxBase; }
272 uint64_t getGfxRptr() { return gfxRptr; }
273 uint64_t getGfxDoorbell() { return gfxDoorbell; }
275 uint64_t getGfxWptr() { return gfxWptr; }
276 uint64_t getPageBase() { return pageBase; }
277 uint64_t getPageRptr() { return pageRptr; }
278 uint64_t getPageDoorbell() { return pageDoorbell; }
280 uint64_t getPageWptr() { return pageWptr; }
281
285 void writeMMIO(PacketPtr pkt, Addr mmio_offset);
286
287 void setGfxBaseLo(uint32_t data);
288 void setGfxBaseHi(uint32_t data);
289 void setGfxRptrLo(uint32_t data);
290 void setGfxRptrHi(uint32_t data);
291 void setGfxDoorbellLo(uint32_t data);
292 void setGfxDoorbellHi(uint32_t data);
293 void setGfxDoorbellOffsetLo(uint32_t data);
294 void setGfxDoorbellOffsetHi(uint32_t data);
295 void setGfxSize(uint32_t data);
296 void setGfxWptrLo(uint32_t data);
297 void setGfxWptrHi(uint32_t data);
298 void setPageBaseLo(uint32_t data);
299 void setPageBaseHi(uint32_t data);
300 void setPageRptrLo(uint32_t data);
301 void setPageRptrHi(uint32_t data);
302 void setPageDoorbellLo(uint32_t data);
303 void setPageDoorbellHi(uint32_t data);
304 void setPageDoorbellOffsetLo(uint32_t data);
305 void setPageDoorbellOffsetHi(uint32_t data);
306 void setPageSize(uint32_t data);
307 void setPageWptrLo(uint32_t data);
308 void setPageWptrHi(uint32_t data);
309
313 void registerRLCQueue(Addr doorbell, Addr mqdAddr, SDMAQueueDesc *mqd,
314 bool isStatic);
315 void unregisterRLCQueue(Addr doorbell, bool unmap_static);
316 void deallocateRLCQueues(bool unmap_static);
317
318 int cur_vmid = 0;
319};
320
321} // namespace gem5
322
323#endif // __DEV_AMDGPU_SDMA_ENGINE_HH__
const char data[]
Device model for an AMD GPU.
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition packet.hh:295
void setMQD(SDMAQueueDesc *mqd)
void setMQDAddr(Addr mqdAddr)
void processing(bool value)
void setStatic(bool isStatic)
SDMAQueueDesc * getMQD()
void ib(SDMAQueue *ib)
void rptrWbAddr(Addr value)
void incRptr(uint32_t value)
void parent(SDMAQueue *q)
void queueType(SDMAType type)
System DMA Engine class for AMD dGPU.
uint64_t pageDoorbell
void setPageRptrLo(uint32_t data)
void unserialize(CheckpointIn &cp) override
Unserialize an object.
uint64_t getPageDoorbellOffset()
SDMAQueue gfx
Each SDMAEngine processes four queues: paging, gfx, rlc0, and rlc1, where RLC stands for Run List Con...
void ptePde(SDMAQueue *q, sdmaPtePde *pkt)
void setGfxRptrLo(uint32_t data)
void ptePdeCleanup(uint64_t *dmaBuffer)
void setGfxWptrLo(uint32_t data)
uint64_t getGfxDoorbellOffset()
void registerRLCQueue(Addr doorbell, Addr mqdAddr, SDMAQueueDesc *mqd, bool isStatic)
Methods for RLC queues.
void setPageDoorbellHi(uint32_t data)
VegaISA::Walker * walker
Tick read(PacketPtr pkt) override
Pure virtual function that the device must implement.
void setGfxRptrHi(uint32_t data)
void writeDone(SDMAQueue *q, sdmaWrite *pkt, uint32_t *dmaBuffer)
Addr getMmioBase()
Methods for getting SDMA MMIO base address and size.
void processRLC(Addr doorbellOffset, Addr wptrOffset)
uint64_t getPageRptr()
void deallocateRLCQueues(bool unmap_static)
void copy(SDMAQueue *q, sdmaCopy *pkt)
Tick write(PacketPtr pkt) override
Inherited methods.
void writeMMIO(PacketPtr pkt, Addr mmio_offset)
Methods for setting the values of SDMA MMIO registers.
void setGfxSize(uint32_t data)
void fenceDone(SDMAQueue *q, sdmaFence *pkt)
void writeReadData(SDMAQueue *q, sdmaWrite *pkt, uint32_t *dmaBuffer)
void setId(int _id)
void setGfxBaseLo(uint32_t data)
void processRLC0(Addr wptrOffset)
void processGfx(Addr wptrOffset)
Given a new write ptr offset, communicated to the GPU through a doorbell write, the SDMA engine proce...
void setGfxDoorbellOffsetHi(uint32_t data)
void constFill(SDMAQueue *q, sdmaConstFill *pkt, uint32_t header)
AMDGPUDevice * gpuDevice
Addr getGARTAddr(Addr addr) const
Methods for translation.
void setPageDoorbellOffsetHi(uint32_t data)
void processRLC1(Addr wptrOffset)
void setGfxWptrHi(uint32_t data)
void setGfxDoorbellOffsetLo(uint32_t data)
void processPage(Addr wptrOffset)
uint64_t getGfxDoorbell()
void decodeHeader(SDMAQueue *q, uint32_t data)
Reads the first DW (32 bits) (i.e., header) of an SDMA packet, which encodes the opcode and sub-opcod...
uint64_t getGfxBase()
Methods for getting the values of SDMA MMIO registers.
void setPageDoorbellOffsetLo(uint32_t data)
int getIHClientId(int _id)
Returns the client id for the Interrupt Handler.
uint64_t getPageDoorbell()
void setGPUDevice(AMDGPUDevice *gpu_device)
Addr getDeviceAddress(Addr raw_addr)
Translate an address in an SDMA packet.
void writeCleanup(uint32_t *dmaBuffer)
void constFillDone(SDMAQueue *q, sdmaConstFill *pkt, uint8_t *fill_data)
uint64_t pageDoorbellOffset
uint64_t getPageWptr()
void setPageBaseHi(uint32_t data)
uint64_t gfxDoorbellOffset
uint64_t getGfxWptr()
uint64_t getPageBase()
bool pollRegMemFunc(uint32_t value, uint32_t reference, uint32_t func)
void setPageWptrHi(uint32_t data)
void unregisterRLCQueue(Addr doorbell, bool unmap_static)
void setPageWptrLo(uint32_t data)
void pollRegMemRead(SDMAQueue *q, sdmaPollRegMemHeader *header, sdmaPollRegMem *pkt, uint32_t dma_buffer, int count)
void setGfxDoorbellLo(uint32_t data)
void copyReadData(SDMAQueue *q, sdmaCopy *pkt, uint8_t *dmaBuffer)
void indirectBuffer(SDMAQueue *q, sdmaIndirectBuffer *pkt)
void srbmWrite(SDMAQueue *q, sdmaSRBMWriteHeader *header, sdmaSRBMWrite *pkt)
void atomicData(SDMAQueue *q, sdmaAtomicHeader *header, sdmaAtomic *pkt, uint64_t *dmaBuffer)
void trap(SDMAQueue *q, sdmaTrap *pkt)
AddrRangeList getAddrRanges() const override
Every PIO device is obliged to provide an implementation that returns the address ranges the device r...
void setPageDoorbellLo(uint32_t data)
void setGfxDoorbellHi(uint32_t data)
void setPageSize(uint32_t data)
void setPageBaseLo(uint32_t data)
void copyDone(SDMAQueue *q, sdmaCopy *pkt, uint8_t *dmaBuffer)
void copyCleanup(uint8_t *dmaBuffer)
void setGfxBaseHi(uint32_t data)
void ptePdeDone(SDMAQueue *q, sdmaPtePde *pkt, uint64_t *dmaBuffer)
TranslationGenPtr translate(Addr vaddr, Addr size) override
GPUController will perform DMA operations on VAs, and because page faults are not currently supported...
void setPageRptrHi(uint32_t data)
int getId() const
uint64_t getGfxRptr()
void decodeNext(SDMAQueue *q)
This method checks read and write pointers and starts decoding packets if the read pointer is less th...
void fence(SDMAQueue *q, sdmaFence *pkt)
void atomicDone(SDMAQueue *q, sdmaAtomicHeader *header, sdmaAtomic *pkt, uint64_t *dmaBuffer)
void serialize(CheckpointOut &cp) const override
Serialize an object.
std::array< Addr, 2 > rlcInfo
void pollRegMem(SDMAQueue *q, sdmaPollRegMemHeader *header, sdmaPollRegMem *pkt)
Implements a poll reg/mem packet that polls an SRBM register or a memory location,...
Bitfield< 23, 20 > atomic
Bitfield< 28 > v
Definition misc_types.hh:54
Bitfield< 27 > q
Definition misc_types.hh:55
Bitfield< 0 > p
Bitfield< 3 > addr
Definition types.hh:84
Copyright (c) 2024 Arm Limited All rights reserved.
Definition binary32.hh:36
std::ostream CheckpointOut
Definition serialize.hh:66
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition types.hh:147
uint64_t Tick
Tick count type.
Definition types.hh:58
std::unique_ptr< TranslationGen > TranslationGenPtr
output header
Definition nop.cc:36
PM4 packets.

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