gem5 v24.0.0.0
Loading...
Searching...
No Matches
pagetable_walker.hh
Go to the documentation of this file.
1/*
2 * Copyright (c) 2021 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright notice,
12 * this list of conditions and the following disclaimer in the documentation
13 * and/or other materials provided with the distribution.
14 *
15 * 3. Neither the name of the copyright holder nor the names of its
16 * contributors may be used to endorse or promote products derived from this
17 * software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32#ifndef __DEV_AMDGPU_PAGETABLE_WALKER_HH__
33#define __DEV_AMDGPU_PAGETABLE_WALKER_HH__
34
35#include <vector>
36
39#include "base/types.hh"
40#include "debug/GPUPTWalker.hh"
41#include "mem/packet.hh"
42#include "params/VegaPagetableWalker.hh"
43#include "sim/clocked_object.hh"
44#include "sim/system.hh"
45
46namespace gem5
47{
48
49class ThreadContext;
50
51namespace VegaISA
52{
53
54class Walker : public ClockedObject
55{
56 protected:
57 // Port for accessing memory
58 class WalkerPort : public RequestPort
59 {
60 public:
61 WalkerPort(const std::string &_name, Walker * _walker) :
62 RequestPort(_name), walker(_walker)
63 {}
64
65 protected:
67
68 bool recvTimingResp(PacketPtr pkt);
69 void recvReqRetry();
70 };
71
72 friend class WalkerPort;
74
75 // State to track each walk of the page table
77 {
78 friend class Walker;
79
80 private:
87
88 protected:
94 VegaTlbEntry entry;
99 bool started;
100 bool timing;
103
104 public:
105 WalkerState(Walker *_walker, PacketPtr pkt, bool is_functional = false)
106 : walker(_walker), state(Ready), nextState(Ready), dataSize(8),
107 enableNX(true), retrying(false), started(false), tlbPkt(pkt),
109 {
110 DPRINTF(GPUPTWalker, "Walker::WalkerState %p %p %d\n",
111 this, walker, state);
112 }
113
115 bool is_functional = false);
116 void startWalk();
118 unsigned &logBytes);
119
120 bool isRetrying();
121 void retry();
122 std::string name() const { return walker->name(); }
123 Walker* getWalker() const { return walker; }
124
125 private:
126 Fault stepWalk();
128 void walkStateMachine(PageTableEntry &pte, Addr &nextRead,
129 bool &doEndWalk, Fault &fault);
130 void sendPackets();
131 void endWalk();
132 Fault pageFault(bool present);
133 uint64_t offsetFunc(Addr logicalAddr, int top, int lsb);
134 };
135
136 friend class WalkerState;
137 // State for timing and atomic accesses (need multiple per walker in
138 // the case of multiple outstanding requests in timing mode)
140 // State for functional accesses (only need one of these per walker)
142
144 {
147 senderWalk(_senderWalk) {}
148 };
149
150 public:
151 // Kick off the state machine.
154 unsigned &logBytes, BaseMMU::Mode mode);
155 Fault startFunctional(Addr base, Addr &addr, unsigned &logBytes,
156 BaseMMU::Mode mode, bool &isSystem);
157
158 Port &getPort(const std::string &if_name,
159 PortID idx=InvalidPortID) override;
160
161 Addr getBaseAddr() const { return baseAddr; }
163
166
167 protected:
168 // The TLB we're supposed to load.
171
172 // Base address set by MAP_PROCESS packet
175
176 // Functions for dealing with packets.
177 void recvTimingResp(PacketPtr pkt);
178 void recvReqRetry();
179 bool sendTiming(WalkerState * sendingState, PacketPtr pkt);
180
181 void walkerResponse(WalkerState *state, VegaTlbEntry& entry,
182 PacketPtr pkt);
183
184 // System pointer for functional accesses
186
187 public:
188 void setTLB(GpuTLB * _tlb)
189 {
190 assert(tlb == nullptr); // only set it once
191 tlb = _tlb;
192 }
193
194 Walker(const VegaPagetableWalkerParams &p)
195 : ClockedObject(p),
196 port(name() + ".port", this),
197 funcState(this, nullptr, true), tlb(nullptr),
198 requestorId(p.system->getRequestorId(this)),
200 {
201 DPRINTF(GPUPTWalker, "Walker::Walker %p\n", this);
202 }
203};
204
205} // namespace VegaISA
206} // namespace gem5
207
208#endif // __DEV_AMDGPU_PAGETABLE_WALKER_HH__
#define DPRINTF(x,...)
Definition trace.hh:210
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,...
The ClockedObject class extends the SimObject with a clock and accessor functions to relate ticks to ...
const std::string _name
Definition named.hh:41
virtual std::string name() const
Definition named.hh:47
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition packet.hh:295
Ports are used to interface objects to each other.
Definition port.hh:62
A RequestPort is a specialisation of a Port, which implements the default protocol for the three diff...
Definition port.hh:136
bool recvTimingResp(PacketPtr pkt)
Receive a timing response from the peer.
void recvReqRetry()
Called by the peer if sendTimingReq was called on this peer (causing recvTimingReq to be called on th...
WalkerPort(const std::string &_name, Walker *_walker)
Fault startFunctional(Addr base, Addr vaddr, PageTableEntry &pte, unsigned &logBytes)
uint64_t offsetFunc(Addr logicalAddr, int top, int lsb)
void walkStateMachine(PageTableEntry &pte, Addr &nextRead, bool &doEndWalk, Fault &fault)
void sendPackets()
Port related methods.
WalkerState(Walker *_walker, PacketPtr pkt, bool is_functional=false)
void setDevRequestor(RequestorID mid)
void recvTimingResp(PacketPtr pkt)
void walkerResponse(WalkerState *state, VegaTlbEntry &entry, PacketPtr pkt)
void setTLB(GpuTLB *_tlb)
Walker(const VegaPagetableWalkerParams &p)
bool sendTiming(WalkerState *sendingState, PacketPtr pkt)
Fault startFunctional(Addr base, Addr vaddr, PageTableEntry &pte, unsigned &logBytes, BaseMMU::Mode mode)
RequestorID getDevRequestor() const
std::list< WalkerState * > currStates
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
gem5 methods
void startTiming(PacketPtr pkt, Addr base, Addr vaddr, BaseMMU::Mode mode)
STL list class.
Definition stl.hh:51
Definition test.h:63
ClockedObject declaration and implementation.
virtual void initState()
initState() is called on each SimObject when not restoring from a checkpoint.
Definition sim_object.cc:91
atomic_var_t state
Definition helpers.cc:211
Bitfield< 4, 0 > mode
Definition misc_types.hh:74
Bitfield< 19, 16 > ta
Bitfield< 54 > p
Definition pagetable.hh:70
Bitfield< 51, 12 > base
Definition pagetable.hh:141
Bitfield< 7 > present
Definition misc.hh:1027
Bitfield< 3 > addr
Definition types.hh:84
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
std::shared_ptr< FaultBase > Fault
Definition types.hh:249
const PortID InvalidPortID
Definition types.hh:246
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition types.hh:147
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition types.hh:245
uint16_t RequestorID
Definition request.hh:95
Declaration of the Packet class.
A virtual base opaque structure used to hold state associated with the packet (e.g....
Definition packet.hh:469

Generated on Tue Jun 18 2024 16:24:00 for gem5 by doxygen 1.11.0