gem5  v22.0.0.2
amdgpu_device.hh
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31 
32 #ifndef __DEV_AMDGPU_AMDGPU_DEVICE_HH__
33 #define __DEV_AMDGPU_AMDGPU_DEVICE_HH__
34 
35 #include <map>
36 
37 #include "base/bitunion.hh"
39 #include "dev/amdgpu/amdgpu_vm.hh"
42 #include "dev/io_device.hh"
43 #include "dev/pci/device.hh"
44 #include "params/AMDGPUDevice.hh"
45 
46 namespace gem5
47 {
48 
49 class AMDGPUInterruptHandler;
50 class SDMAEngine;
51 
60 class AMDGPUDevice : public PciDevice
61 {
62  private:
66  void dispatchAccess(PacketPtr pkt, bool read);
67 
76  void readFrame(PacketPtr pkt, Addr offset);
77  void readDoorbell(PacketPtr pkt, Addr offset);
78  void readMMIO(PacketPtr pkt, Addr offset);
79 
80  void writeFrame(PacketPtr pkt, Addr offset);
82  void writeMMIO(PacketPtr pkt, Addr offset);
83 
87  using GPURegMap = std::unordered_map<uint32_t, uint64_t>;
90  std::unordered_map<uint32_t, QueueType> doorbells;
91 
96  bool isROM(Addr addr) const { return romRange.contains(addr); }
97  void readROM(PacketPtr pkt);
98 
99  std::array<uint8_t, ROM_SIZE> rom;
100 
105 
114  std::unordered_map<uint32_t, SDMAEngine *> sdmaEngs;
117 
123 
124  // VMIDs data structures
125  // map of pasids to vmids
126  std::unordered_map<uint16_t, uint16_t> idMap;
127  // map of doorbell offsets to vmids
128  std::unordered_map<Addr, uint16_t> doorbellVMIDMap;
129  // map of vmid to all queue ids using that vmid
130  std::unordered_map<uint16_t, std::set<int>> usedVMIDs;
131  // last vmid allocated by map_process PM4 packet
132  uint16_t _lastVMID;
133 
134  /*
135  * Backing store for GPU memory / framebuffer / VRAM
136  */
138 
139  public:
140  AMDGPUDevice(const AMDGPUDeviceParams &p);
141 
145  void intrPost();
146 
147  Tick writeConfig(PacketPtr pkt) override;
148  Tick readConfig(PacketPtr pkt) override;
149 
150  Tick read(PacketPtr pkt) override;
151  Tick write(PacketPtr pkt) override;
152 
153  AddrRangeList getAddrRanges() const override;
154 
158  void serialize(CheckpointOut &cp) const override;
159  void unserialize(CheckpointIn &cp) override;
160 
165  SDMAEngine* getSDMAById(int id);
167  AMDGPUVM &getVM() { return gpuvm; }
169  GPUCommandProcessor* CP() { return cp; }
170 
174  void setDoorbellType(uint32_t offset, QueueType qt);
175  void setSDMAEngine(Addr offset, SDMAEngine *eng);
176 
181  uint32_t getRegVal(uint32_t addr);
182  void setRegVal(uint32_t addr, uint32_t value);
183 
188 
189  /* HW context stuff */
190  uint16_t lastVMID() { return _lastVMID; }
191  uint16_t allocateVMID(uint16_t pasid);
192  void deallocateVmid(uint16_t vmid);
193  void deallocatePasid(uint16_t pasid);
194  void deallocateAllQueues();
195  void mapDoorbellToVMID(Addr doorbell, uint16_t vmid);
196  uint16_t getVMID(Addr doorbell) { return doorbellVMIDMap[doorbell]; }
197  std::unordered_map<uint16_t, std::set<int>>& getUsedVMIDs();
198  void insertQId(uint16_t vmid, int id);
199 };
200 
201 } // namespace gem5
202 
203 #endif // __DEV_AMDGPU_AMDGPU_DEVICE_HH__
gem5::AMDGPUDevice::read
Tick read(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: amdgpu_device.cc:344
gem5::AMDGPUDevice::isROM
bool isROM(Addr addr) const
Definition: amdgpu_device.hh:96
io_device.hh
gem5::AMDGPUDevice::_lastVMID
uint16_t _lastVMID
Definition: amdgpu_device.hh:132
gem5::AMDGPUDevice::getAddrRanges
AddrRangeList getAddrRanges() const override
Every PIO device is obliged to provide an implementation that returns the address ranges the device r...
Definition: amdgpu_device.cc:110
gem5::AMDGPUVM
Definition: amdgpu_vm.hh:91
gem5::AMDGPUDevice::gpuMemMgr
AMDGPUMemoryManager * gpuMemMgr
Blocks of the GPU.
Definition: amdgpu_device.hh:109
gem5::AMDGPUDevice::setDoorbellType
void setDoorbellType(uint32_t offset, QueueType qt)
Set handles to GPU blocks.
Definition: amdgpu_device.cc:424
gem5::AMDGPUDevice::frame_regs
GPURegMap frame_regs
Definition: amdgpu_device.hh:88
gem5::AMDGPUDevice::getSDMAEngine
SDMAEngine * getSDMAEngine(Addr offset)
Definition: amdgpu_device.cc:459
gem5::AMDGPUDevice::getSDMAById
SDMAEngine * getSDMAById(int id)
Definition: amdgpu_device.cc:437
gem5::memory::PhysicalMemory
The physical memory encapsulates all memories in the system and provides basic functionality for acce...
Definition: physical.hh:136
gem5::AMDGPUDevice::deallocateAllQueues
void deallocateAllQueues()
Definition: amdgpu_device.cc:622
gem5::AddrRange::contains
bool contains(const Addr &a) const
Determine if the range contains an address.
Definition: addr_range.hh:471
gem5::AMDGPUDevice::GPURegMap
std::unordered_map< uint32_t, uint64_t > GPURegMap
Structures to hold registers, doorbells, and some frame memory.
Definition: amdgpu_device.hh:87
gem5::AMDGPUDevice::intrPost
void intrPost()
Methods inherited from PciDevice.
Definition: amdgpu_device.cc:465
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::AMDGPUDevice::lastVMID
uint16_t lastVMID()
Definition: amdgpu_device.hh:190
gem5::AMDGPUDevice::sdma1
SDMAEngine * sdma1
Definition: amdgpu_device.hh:113
gem5::AMDGPUDevice::idMap
std::unordered_map< uint16_t, uint16_t > idMap
Definition: amdgpu_device.hh:126
gem5::AMDGPUDevice::doorbellVMIDMap
std::unordered_map< Addr, uint16_t > doorbellVMIDMap
Definition: amdgpu_device.hh:128
gem5::AMDGPUDevice::getVM
AMDGPUVM & getVM()
Definition: amdgpu_device.hh:167
gem5::AMDGPUDevice::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: amdgpu_device.cc:528
gem5::AMDGPUDevice::readConfig
Tick readConfig(PacketPtr pkt) override
Read from the PCI config space data that is stored locally.
Definition: amdgpu_device.cc:129
device.hh
gem5::AMDGPUDevice::mapDoorbellToVMID
void mapDoorbellToVMID(Addr doorbell, uint16_t vmid)
Definition: amdgpu_device.cc:629
gem5::AMDGPUDevice::writeMMIO
void writeMMIO(PacketPtr pkt, Addr offset)
Definition: amdgpu_device.cc:312
gem5::AMDGPUDevice::gpuvm
AMDGPUVM gpuvm
Definition: amdgpu_device.hh:111
gem5::AMDGPUDevice::cp
GPUCommandProcessor * cp
Definition: amdgpu_device.hh:116
gem5::AMDGPUDevice::sdmaEngs
std::unordered_map< uint32_t, SDMAEngine * > sdmaEngs
Definition: amdgpu_device.hh:114
memory_manager.hh
gem5::AMDGPUDevice::AMDGPUDevice
AMDGPUDevice(const AMDGPUDeviceParams &p)
Definition: amdgpu_device.cc:53
gem5::AMDGPUDevice::getIH
AMDGPUInterruptHandler * getIH()
Get handles to GPU blocks.
Definition: amdgpu_device.hh:164
gem5::AMDGPUInterruptHandler
Definition: interrupt_handler.hh:122
gem5::GPUCommandProcessor
Definition: gpu_command_processor.hh:70
gem5::AMDGPUDevice::writeConfig
Tick writeConfig(PacketPtr pkt) override
Write to the PCI config space data that is stored locally.
Definition: amdgpu_device.cc:157
gem5::VegaISA::p
Bitfield< 54 > p
Definition: pagetable.hh:70
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:291
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
bitunion.hh
gem5::AMDGPUDevice::setRegVal
void setRegVal(uint32_t addr, uint32_t value)
Definition: amdgpu_device.cc:416
gem5::PM4PacketProcessor
Definition: pm4_packet_processor.hh:52
gem5::AMDGPUDevice::allocateVMID
uint16_t allocateVMID(uint16_t pasid)
Definition: amdgpu_device.cc:589
gem5::AMDGPUDevice::regs
GPURegMap regs
Definition: amdgpu_device.hh:89
gem5::AMDGPUDevice::mmioReader
AMDMMIOReader mmioReader
MMIO reader to populate device registers map.
Definition: amdgpu_device.hh:104
gem5::PciDevice
PCI device, base implementation is only config space.
Definition: device.hh:269
gem5::AMDGPUDevice::checkpoint_before_mmios
bool checkpoint_before_mmios
Initial checkpoint support variables.
Definition: amdgpu_device.hh:121
gem5::AMDGPUDevice::readROM
void readROM(PacketPtr pkt)
Definition: amdgpu_device.cc:97
amdgpu_defines.hh
gem5::AMDGPUMemoryManager
Definition: memory_manager.hh:45
gem5::ArmISA::offset
Bitfield< 23, 0 > offset
Definition: types.hh:144
gem5::AMDGPUDevice
Device model for an AMD GPU.
Definition: amdgpu_device.hh:60
gem5::AMDGPUDevice::serialize
void serialize(CheckpointOut &cp) const override
Checkpoint support.
Definition: amdgpu_device.cc:471
gem5::AMDGPUDevice::dispatchAccess
void dispatchAccess(PacketPtr pkt, bool read)
Convert a PCI packet into a response.
Definition: amdgpu_device.cc:168
gem5::AMDMMIOReader
Helper class to read Linux kernel MMIO trace from amdgpu modprobes.
Definition: mmio_reader.hh:62
gem5::AMDGPUDevice::readFrame
void readFrame(PacketPtr pkt, Addr offset)
Helper methods to handle specific BAR read/writes.
Definition: amdgpu_device.cc:178
gem5::AMDGPUDevice::readDoorbell
void readDoorbell(PacketPtr pkt, Addr offset)
Definition: amdgpu_device.cc:204
gem5::SDMAEngine
System DMA Engine class for AMD dGPU.
Definition: sdma_engine.hh:48
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::AMDGPUDevice::write
Tick write(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: amdgpu_device.cc:373
gem5::AMDGPUDevice::getVMID
uint16_t getVMID(Addr doorbell)
Definition: amdgpu_device.hh:196
gem5::AMDGPUDevice::getUsedVMIDs
std::unordered_map< uint16_t, std::set< int > > & getUsedVMIDs()
Definition: amdgpu_device.cc:635
gem5::AMDGPUMemoryManager::getRequestorID
RequestorID getRequestorID() const
Get the requestorID for the memory manager.
Definition: memory_manager.hh:98
gem5::AMDGPUDevice::getMemMgr
AMDGPUMemoryManager * getMemMgr()
Definition: amdgpu_device.hh:168
gem5::AMDGPUDevice::readMMIO
void readMMIO(PacketPtr pkt, Addr offset)
Definition: amdgpu_device.cc:211
gem5::AMDGPUDevice::init_interrupt_count
int init_interrupt_count
Definition: amdgpu_device.hh:122
gem5::AMDGPUDevice::romRange
AddrRange romRange
VGA ROM methods.
Definition: amdgpu_device.hh:95
gem5::AMDGPUDevice::usedVMIDs
std::unordered_map< uint16_t, std::set< int > > usedVMIDs
Definition: amdgpu_device.hh:130
gem5::AMDGPUDevice::insertQId
void insertQId(uint16_t vmid, int id)
Definition: amdgpu_device.cc:641
gem5::AMDGPUDevice::deallocateVmid
void deallocateVmid(uint16_t vmid)
Definition: amdgpu_device.cc:604
gem5::AMDGPUDevice::deallocatePasid
void deallocatePasid(uint16_t pasid)
Definition: amdgpu_device.cc:610
gem5::AMDGPUDevice::rom
std::array< uint8_t, ROM_SIZE > rom
Definition: amdgpu_device.hh:99
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::RequestorID
uint16_t RequestorID
Definition: request.hh:95
gem5::AMDGPUDevice::deviceMem
memory::PhysicalMemory deviceMem
Definition: amdgpu_device.hh:137
gem5::AMDGPUDevice::getRegVal
uint32_t getRegVal(uint32_t addr)
Register value getter/setter.
Definition: amdgpu_device.cc:411
gem5::AMDGPUDevice::CP
GPUCommandProcessor * CP()
Definition: amdgpu_device.hh:169
gem5::AMDGPUDevice::writeFrame
void writeFrame(PacketPtr pkt, Addr offset)
Definition: amdgpu_device.cc:248
gem5::AddrRange
The AddrRange class encapsulates an address range, and supports a number of tests to check if two ran...
Definition: addr_range.hh:81
std::list< AddrRange >
amdgpu_vm.hh
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::QueueType
QueueType
Definition: amdgpu_defines.hh:41
gem5::AMDGPUDevice::pm4PktProc
PM4PacketProcessor * pm4PktProc
Definition: amdgpu_device.hh:115
gem5::AMDGPUDevice::setSDMAEngine
void setSDMAEngine(Addr offset, SDMAEngine *eng)
Definition: amdgpu_device.cc:431
gem5::AMDGPUDevice::sdma0
SDMAEngine * sdma0
Definition: amdgpu_device.hh:112
gem5::AMDGPUDevice::doorbells
std::unordered_map< uint32_t, QueueType > doorbells
Definition: amdgpu_device.hh:90
mmio_reader.hh
gem5::AMDGPUDevice::vramRequestorId
RequestorID vramRequestorId()
Methods related to translations and system/device memory.
Definition: amdgpu_device.hh:187
gem5::AMDGPUDevice::deviceIH
AMDGPUInterruptHandler * deviceIH
Definition: amdgpu_device.hh:110
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::AMDGPUDevice::writeDoorbell
void writeDoorbell(PacketPtr pkt, Addr offset)
Definition: amdgpu_device.cc:266

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