sme.cc

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 *
 * The license below extends only to copyright in the software and shall
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 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
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 * modified or unmodified, in source code or in binary form.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
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 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
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 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#include "arch/arm/insts/sme.hh"
 
namespace gem5
{
 
namespace ArmISA
{
 
std::string
SmeAddOp::generateDisassembly(Addr pc,
                              const loader::SymbolTable *symtab) const
{
    std::stringstream ss;
    printMnemonic(ss, "", false);
    ccprintf(ss, "#%d", imm);
    ss << ", ";
    printVecReg(ss, op1, true);
    ss << ", ";
    printVecPredReg(ss, gp1);
    ss << ", ";
    printVecPredReg(ss, gp2);
    return ss.str();
}
 
std::string
SmeAddVlOp::generateDisassembly(Addr pc,
                                const loader::SymbolTable *symtab) const
{
    std::stringstream ss;
    printMnemonic(ss, "", false);
    ss << ", ";
    printVecReg(ss, dest);
    ss << ", ";
    printVecReg(ss, op1);
    ss << ", ";
    ccprintf(ss, "#%d", imm);
    return ss.str();
}
 
std::string
SmeLd1xSt1xOp::generateDisassembly(Addr pc,
                                   const loader::SymbolTable *symtab) const
{
    std::stringstream ss;
    printMnemonic(ss, "", false);
    ccprintf(ss, "#%d", imm);
    ss << ", ";
    printIntReg(ss, op1);
    ss << ", ";
    printVecPredReg(ss, gp);
    ss << ", ";
    printIntReg(ss, op2);
    ss << ", ";
    printIntReg(ss, op3);
    return ss.str();
}
 
std::string
SmeLdrStrOp::generateDisassembly(Addr pc,
                                 const loader::SymbolTable *symtab) const
{
    std::stringstream ss;
    printMnemonic(ss, "", false);
    ccprintf(ss, "#%d", imm);
    ss << ", ";
    printIntReg(ss, op1, true);
    ss << ", ";
    printIntReg(ss, op2, true);
    return ss.str();
}
 
std::string
SmeMovExtractOp::generateDisassembly(Addr pc,
                                     const loader::SymbolTable *symtab) const
{
    std::stringstream ss;
    printMnemonic(ss, "", false);
    printVecReg(ss, op1, true);
    ss << ", ";
    ccprintf(ss, "#%d", imm);
    ss << ", ";
    printVecPredReg(ss, gp);
    ss << ", ";
    printIntReg(ss, op2);
    return ss.str();
}
 
std::string
SmeMovInsertOp::generateDisassembly(Addr pc,
                                    const loader::SymbolTable *symtab) const
{
    std::stringstream ss;
    printMnemonic(ss, "", false);
    ccprintf(ss, "#%d", imm);
    ss << ", ";
    printVecReg(ss, op1, true);
    ss << ", ";
    printVecPredReg(ss, gp);
    ss << ", ";
    printIntReg(ss, op2);
    return ss.str();
}
 
std::string
SmeOPOp::generateDisassembly(Addr pc,
                             const loader::SymbolTable *symtab) const
{
    std::stringstream ss;
    printMnemonic(ss, "", false);
    ccprintf(ss, "#%d", imm);
    ss << ", ";
    printVecPredReg(ss, gp1);
    ss << ", ";
    printVecPredReg(ss, gp2);
    ss << ", ";
    printVecReg(ss, op1, true);
    ss << ", ";
    printVecReg(ss, op2, true);
    return ss.str();
}
 
std::string
SmeRdsvlOp::generateDisassembly(Addr pc,
                                const loader::SymbolTable *symtab) const
{
    std::stringstream ss;
    printMnemonic(ss, "", false);
    ss << ", ";
    printVecReg(ss, dest);
    ss << ", ";
    ccprintf(ss, "#%d", imm);
    return ss.str();
}
 
std::string
SmeZeroOp::generateDisassembly(Addr pc,
                               const loader::SymbolTable *symtab) const
{
    std::stringstream ss;
    ArmStaticInst::printMnemonic(ss, "", false);
    ccprintf(ss, "#%d", imm);
    return ss.str();
}
 
} // namespace ArmISA
} // namespace gem5