gem5  v21.1.0.2
misc.hh
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28 
29 #ifndef __ARCH_SPARC_REGS_MISC_HH__
30 #define __ARCH_SPARC_REGS_MISC_HH__
31 
32 #include "base/bitunion.hh"
33 #include "base/types.hh"
34 
35 namespace gem5
36 {
37 
38 namespace SparcISA
39 {
41 {
43 // MISCREG_Y,
44 // MISCREG_CCR,
53  MISCREG_SOFTINT, /* 10 */
57 
65  MISCREG_PSTATE, /* 20 */
69 // MISCREG_CANSAVE,
70 // MISCREG_CANRESTORE,
71 // MISCREG_CLEANWIN,
72 // MISCREG_OTHERWIN,
73 // MISCREG_WSTATE,
75 
77  MISCREG_HPSTATE, /* 30 */
84 
87 
93 
103 
104  /* CPU Queue Registers */
113 
114  /* All the data for the TLB packed up in one register. */
117 };
118 
119 BitUnion64(HPSTATE)
120  Bitfield<0> tlz;
121  Bitfield<2> hpriv;
122  Bitfield<5> red;
123  Bitfield<10> ibe;
124  Bitfield<11> id; // this impl. dependent (id) field m
125 EndBitUnion(HPSTATE)
126 
127 BitUnion16(PSTATE)
128  Bitfield<1> ie;
129  Bitfield<2> priv;
130  Bitfield<3> am;
131  Bitfield<4> pef;
132  Bitfield<7, 6> mm;
133  Bitfield<8> tle;
134  Bitfield<9> cle;
135  Bitfield<10> pid0;
136  Bitfield<11> pid1;
137 EndBitUnion(PSTATE)
138 
139 BitUnion8(CCR)
140  SubBitUnion(xcc, 7, 4)
141  Bitfield<7> n;
142  Bitfield<6> z;
143  Bitfield<5> v;
144  Bitfield<4> c;
145  EndSubBitUnion(xcc)
146  SubBitUnion(icc, 3, 0)
147  Bitfield<3> n;
148  Bitfield<2> z;
149  Bitfield<1> v;
150  Bitfield<0> c;
152 EndBitUnion(CCR)
153 
154 struct STS
155 {
156  const static int st_idle = 0x00;
157  const static int st_wait = 0x01;
158  const static int st_halt = 0x02;
159  const static int st_run = 0x05;
160  const static int st_spec_run = 0x07;
161  const static int st_spec_rdy = 0x13;
162  const static int st_ready = 0x19;
163  const static int active = 0x01;
164  const static int speculative = 0x04;
165  const static int shft_id = 8;
166  const static int shft_fsm0 = 31;
167  const static int shft_fsm1 = 26;
168  const static int shft_fsm2 = 21;
169  const static int shft_fsm3 = 16;
170 };
171 
172 
174 
175 } // namespace SparcISA
176 } // namespace gem5
177 
178 #endif
gem5::SparcISA::MISCREG_ASI
@ MISCREG_ASI
Ancillary State Registers.
Definition: misc.hh:45
gem5::SparcISA::MISCREG_TICK_CMPR
@ MISCREG_TICK_CMPR
Definition: misc.hh:54
gem5::SparcISA::z
Bitfield< 6 > z
Definition: misc.hh:142
gem5::SparcISA::v
Bitfield< 5 > v
Definition: misc.hh:143
gem5::SparcISA::MISCREG_TT
@ MISCREG_TT
Definition: misc.hh:62
gem5::SparcISA::MISCREG_QUEUE_DEV_MONDO_HEAD
@ MISCREG_QUEUE_DEV_MONDO_HEAD
Definition: misc.hh:107
gem5::SparcISA::id
Bitfield< 11 > id
Definition: misc.hh:124
gem5::SparcISA::n
Bitfield< 7 > n
Definition: misc.hh:140
gem5::SparcISA::MISCREG_STICK
@ MISCREG_STICK
Definition: misc.hh:55
gem5::SparcISA::MISCREG_QUEUE_NRES_ERROR_HEAD
@ MISCREG_QUEUE_NRES_ERROR_HEAD
Definition: misc.hh:111
gem5::SparcISA::tle
Bitfield< 8 > tle
Definition: misc.hh:133
gem5::SparcISA::MISCREG_SOFTINT_SET
@ MISCREG_SOFTINT_SET
Definition: misc.hh:51
gem5::SparcISA::MISCREG_HVER
@ MISCREG_HVER
Definition: misc.hh:81
gem5::SparcISA::MISCREG_HPSTATE
@ MISCREG_HPSTATE
Hyper privileged registers.
Definition: misc.hh:77
gem5::SparcISA::BitUnion64
BitUnion64(HPSTATE) Bitfield< 0 > tlz
gem5::SparcISA::MISCREG_FPRS
@ MISCREG_FPRS
Definition: misc.hh:47
gem5::SparcISA::MISCREG_HINTP
@ MISCREG_HINTP
Definition: misc.hh:79
gem5::SparcISA::MISCREG_SCRATCHPAD_R4
@ MISCREG_SCRATCHPAD_R4
Definition: misc.hh:99
gem5::SparcISA::EndSubBitUnion
EndSubBitUnion(xcc) SubBitUnion(icc
gem5::SparcISA::MISCREG_HSTICK_CMPR
@ MISCREG_HSTICK_CMPR
Definition: misc.hh:83
gem5::SparcISA::MISCREG_SCRATCHPAD_R1
@ MISCREG_SCRATCHPAD_R1
Definition: misc.hh:96
gem5::SparcISA::MISCREG_MMU_PART_ID
@ MISCREG_MMU_PART_ID
Definition: misc.hh:91
gem5::SparcISA::MISCREG_PRIVTICK
@ MISCREG_PRIVTICK
Definition: misc.hh:63
gem5::SparcISA::NumMiscRegs
const int NumMiscRegs
Definition: misc.hh:173
gem5::SparcISA::EndBitUnion
EndBitUnion(HPSTATE) BitUnion16(PSTATE) Bitfield< 1 > ie
gem5::SparcISA::MISCREG_TL
@ MISCREG_TL
Definition: misc.hh:66
gem5::SparcISA::cle
Bitfield< 9 > cle
Definition: misc.hh:134
SubBitUnion
#define SubBitUnion(name, first, last)
Regular bitfields These define macros for read/write regular bitfield based subbitfields.
Definition: bitunion.hh:471
gem5::SparcISA::MISCREG_MMU_S_CONTEXT
@ MISCREG_MMU_S_CONTEXT
Definition: misc.hh:90
bitunion.hh
gem5::SparcISA::MiscRegIndex
MiscRegIndex
Definition: misc.hh:40
gem5::SparcISA::MISCREG_QUEUE_DEV_MONDO_TAIL
@ MISCREG_QUEUE_DEV_MONDO_TAIL
Definition: misc.hh:108
gem5::SparcISA::MISCREG_TSTATE
@ MISCREG_TSTATE
Definition: misc.hh:61
gem5::SparcISA::MISCREG_SCRATCHPAD_R7
@ MISCREG_SCRATCHPAD_R7
Definition: misc.hh:102
BitUnion8
#define BitUnion8(name)
Definition: bitunion.hh:498
gem5::SparcISA::ibe
Bitfield< 10 > ibe
Definition: misc.hh:123
gem5::SparcISA::am
Bitfield< 3 > am
Definition: misc.hh:130
gem5::SparcISA::MISCREG_QUEUE_CPU_MONDO_TAIL
@ MISCREG_QUEUE_CPU_MONDO_TAIL
Definition: misc.hh:106
gem5::SparcISA::MISCREG_QUEUE_RES_ERROR_HEAD
@ MISCREG_QUEUE_RES_ERROR_HEAD
Definition: misc.hh:109
gem5::SparcISA::MISCREG_PCR
@ MISCREG_PCR
Definition: misc.hh:48
gem5::SparcISA::mm
Bitfield< 7, 6 > mm
Definition: misc.hh:132
gem5::SparcISA::MISCREG_SCRATCHPAD_R5
@ MISCREG_SCRATCHPAD_R5
Definition: misc.hh:100
gem5::SparcISA::red
Bitfield< 5 > red
Definition: misc.hh:122
gem5::SparcISA::priv
Bitfield< 2 > priv
Definition: misc.hh:129
gem5::SparcISA::MISCREG_QUEUE_CPU_MONDO_HEAD
@ MISCREG_QUEUE_CPU_MONDO_HEAD
Definition: misc.hh:105
BitUnion16
BitUnion16(PciCommandRegister) Bitfield< 15
gem5::SparcISA::MISCREG_QUEUE_NRES_ERROR_TAIL
@ MISCREG_QUEUE_NRES_ERROR_TAIL
Definition: misc.hh:112
gem5::SparcISA::MISCREG_GSR
@ MISCREG_GSR
Definition: misc.hh:50
gem5::SparcISA::MISCREG_HTBA
@ MISCREG_HTBA
Definition: misc.hh:80
gem5::SparcISA::MISCREG_TNPC
@ MISCREG_TNPC
Definition: misc.hh:60
gem5::SparcISA::MISCREG_TICK
@ MISCREG_TICK
Definition: misc.hh:46
gem5::SparcISA::MISCREG_TBA
@ MISCREG_TBA
Definition: misc.hh:64
types.hh
gem5::SparcISA::MISCREG_FSR
@ MISCREG_FSR
Floating Point Status Register.
Definition: misc.hh:86
gem5::SparcISA::MISCREG_PSTATE
@ MISCREG_PSTATE
Definition: misc.hh:65
gem5::SparcISA::MISCREG_SCRATCHPAD_R3
@ MISCREG_SCRATCHPAD_R3
Definition: misc.hh:98
gem5::SparcISA::MISCREG_TLB_DATA
@ MISCREG_TLB_DATA
Definition: misc.hh:115
gem5::SparcISA::MISCREG_SOFTINT_CLR
@ MISCREG_SOFTINT_CLR
Definition: misc.hh:52
gem5::SparcISA::MISCREG_HTSTATE
@ MISCREG_HTSTATE
Definition: misc.hh:78
gem5::SparcISA::MISCREG_PIL
@ MISCREG_PIL
Definition: misc.hh:67
gem5::SparcISA::MISCREG_STRAND_STS_REG
@ MISCREG_STRAND_STS_REG
Definition: misc.hh:82
gem5::SparcISA::MISCREG_CWP
@ MISCREG_CWP
Definition: misc.hh:68
gem5::MipsISA::ie
Bitfield< 0 > ie
Definition: pra_constants.hh:142
gem5::SparcISA::MISCREG_SCRATCHPAD_R6
@ MISCREG_SCRATCHPAD_R6
Definition: misc.hh:101
gem5::SparcISA::MISCREG_GL
@ MISCREG_GL
Definition: misc.hh:74
gem5::SparcISA::hpriv
Bitfield< 2 > hpriv
Definition: misc.hh:121
gem5::SparcISA::MISCREG_TPC
@ MISCREG_TPC
Privilged Registers.
Definition: misc.hh:59
gem5::SparcISA::pef
Bitfield< 4 > pef
Definition: misc.hh:131
gem5::SparcISA::MISCREG_MMU_LSU_CTRL
@ MISCREG_MMU_LSU_CTRL
Definition: misc.hh:92
gem5::SparcISA::pid0
Bitfield< 10 > pid0
Definition: misc.hh:135
gem5::SparcISA::MISCREG_PIC
@ MISCREG_PIC
Definition: misc.hh:49
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::SparcISA::MISCREG_STICK_CMPR
@ MISCREG_STICK_CMPR
Definition: misc.hh:56
gem5::SparcISA::MISCREG_MMU_P_CONTEXT
@ MISCREG_MMU_P_CONTEXT
MMU Internal Registers.
Definition: misc.hh:89
gem5::SparcISA::MISCREG_NUMMISCREGS
@ MISCREG_NUMMISCREGS
Definition: misc.hh:116
gem5::SparcISA::c
Bitfield< 4 > c
Definition: misc.hh:144
gem5::SparcISA::MISCREG_SOFTINT
@ MISCREG_SOFTINT
Definition: misc.hh:53
gem5::SparcISA::MISCREG_SCRATCHPAD_R0
@ MISCREG_SCRATCHPAD_R0
Scratchpad regiscers.
Definition: misc.hh:95
gem5::SparcISA::MISCREG_SCRATCHPAD_R2
@ MISCREG_SCRATCHPAD_R2
Definition: misc.hh:97
gem5::SparcISA::pid1
Bitfield< 11 > pid1
Definition: misc.hh:136
gem5::SparcISA::MISCREG_QUEUE_RES_ERROR_TAIL
@ MISCREG_QUEUE_RES_ERROR_TAIL
Definition: misc.hh:110

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