gem5  v22.0.0.2
faults.hh
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41 
42 #ifndef __ARM_FAULTS_HH__
43 #define __ARM_FAULTS_HH__
44 
45 #include "arch/arm/pagetable.hh"
46 #include "arch/arm/regs/misc.hh"
47 #include "arch/arm/types.hh"
48 #include "base/logging.hh"
49 #include "cpu/null_static_inst.hh"
50 #include "sim/faults.hh"
51 #include "sim/full_system.hh"
52 
53 namespace gem5
54 {
55 
56 // The design of the "name" and "vect" functions is in sim/faults.hh
57 
58 namespace ArmISA
59 {
60 typedef Addr FaultOffset;
61 
62 class ArmStaticInst;
63 
64 class ArmFault : public FaultBase
65 {
66  protected:
68  uint32_t issRaw;
69 
70  // Helper variables for ARMv8 exception handling
71  bool bStep; // True if the Arm Faul exception is a software Step exception
72  bool from64; // True if the exception is generated from the AArch64 state
73  bool to64; // True if the exception is taken in AArch64 state
74  ExceptionLevel fromEL; // Source exception level
75  ExceptionLevel toEL; // Target exception level
76  OperatingMode fromMode; // Source operating mode (aarch32)
77  OperatingMode toMode; // Next operating mode (aarch32)
78 
79  // This variable is true if the above fault specific informations
80  // have been updated. This is to prevent that a client is using their
81  // un-updated default constructed value.
83 
84  bool hypRouted; // True if the fault has been routed to Hypervisor
85  bool span; // True if the fault is setting the PSTATE.PAN bit
86 
87  virtual Addr getVector(ThreadContext *tc);
89 
90  public:
96  {
98  InstructionCacheMaintenance, // Short-desc. format only
107  TLBConflictAbort, // Requires LPAE
111  AddressSizeLL, // AArch64 only
112 
113  // Not real faults. These are faults to allow the translation function
114  // to inform the memory access function not to proceed for a prefetch
115  // that misses in the TLB or that targets an uncacheable address
118 
121  };
122 
131 
133  {
134  S1PTW, // DataAbort, PrefetchAbort: Stage 1 Page Table Walk,
135  OVA, // DataAbort, PrefetchAbort: stage 1 Virtual Address for stage 2 faults
136  SAS, // DataAbort: Syndrome Access Size
137  SSE, // DataAbort: Syndrome Sign Extend
138  SRT, // DataAbort: Syndrome Register Transfer
139  CM, // DataAbort: Cache Maintenance/Address Translation Op
140  OFA, // DataAbort: Override fault Address. This is needed when
141  // the abort is triggered by a CMO. The faulting address is
142  // then the address specified in the register argument of the
143  // instruction and not the cacheline address (See FAR doc)
144 
145  // AArch64 only
146  SF, // DataAbort: width of the accessed register is SixtyFour
147  AR // DataAbort: Acquire/Release semantics
148  };
149 
151  {
155  };
156 
158  {
159  NODEBUG = 0,
164  };
165 
166  struct FaultVals
167  {
169 
171 
172  // Offsets used for exceptions taken in AArch64 state
173  const uint16_t currELTOffset;
174  const uint16_t currELHOffset;
175  const uint16_t lowerEL64Offset;
176  const uint16_t lowerEL32Offset;
177 
179 
180  const uint8_t armPcOffset;
181  const uint8_t thumbPcOffset;
182  // The following two values are used in place of armPcOffset and
183  // thumbPcOffset when the exception return address is saved into ELR
184  // registers (exceptions taken in HYP mode or in AArch64 state)
185  const uint8_t armPcElrOffset;
186  const uint8_t thumbPcElrOffset;
187 
188  const bool hypTrappable;
189  const bool abortDisable;
190  const bool fiqDisable;
191 
192  // Exception class used to appropriately set the syndrome register
193  // (exceptions taken in HYP mode or in AArch64 state)
195 
196  FaultVals(const FaultName& name_, FaultOffset offset_,
197  uint16_t curr_elt_offset, uint16_t curr_elh_offset,
198  uint16_t lower_el64_offset,
199  uint16_t lower_el32_offset,
200  OperatingMode next_mode, uint8_t arm_pc_offset,
201  uint8_t thumb_pc_offset, uint8_t arm_pc_elr_offset,
202  uint8_t thumb_pc_elr_offset, bool hyp_trappable,
203  bool abort_disable, bool fiq_disable,
204  ExceptionClass ec_)
205  : name(name_), offset(offset_), currELTOffset(curr_elt_offset),
206  currELHOffset(curr_elh_offset), lowerEL64Offset(lower_el64_offset),
207  lowerEL32Offset(lower_el32_offset), nextMode(next_mode),
208  armPcOffset(arm_pc_offset), thumbPcOffset(thumb_pc_offset),
209  armPcElrOffset(arm_pc_elr_offset),
210  thumbPcElrOffset(thumb_pc_elr_offset),
211  hypTrappable(hyp_trappable), abortDisable(abort_disable),
212  fiqDisable(fiq_disable), ec(ec_) {}
213  };
214 
215  ArmFault(ExtMachInst mach_inst = 0, uint32_t _iss = 0) :
216  machInst(mach_inst), issRaw(_iss), bStep(false), from64(false),
218  faultUpdated(false), hypRouted(false), span(false) {}
219 
220  // Returns the actual syndrome register to use based on the target
221  // exception level
223  // Returns the actual fault address register to use based on the target
224  // exception level
226 
227  void invoke(ThreadContext *tc, const StaticInstPtr &inst =
228  nullStaticInstPtr) override;
229  void invoke32(ThreadContext *tc, const StaticInstPtr &inst =
231  void invoke64(ThreadContext *tc, const StaticInstPtr &inst =
233  void update(ThreadContext *tc);
234  bool isResetSPSR(){ return bStep; }
235 
236  bool vectorCatch(ThreadContext *tc, const StaticInstPtr &inst);
237 
239  virtual void annotate(AnnotationIDs id, uint64_t val) {}
240  virtual FaultOffset offset(ThreadContext *tc) = 0;
241  virtual FaultOffset offset64(ThreadContext *tc) = 0;
242  virtual OperatingMode nextMode() = 0;
243  virtual bool routeToMonitor(ThreadContext *tc) const = 0;
244  virtual bool routeToHyp(ThreadContext *tc) const { return false; }
245  virtual uint8_t armPcOffset(bool is_hyp) = 0;
246  virtual uint8_t thumbPcOffset(bool is_hyp) = 0;
247  virtual uint8_t armPcElrOffset() = 0;
248  virtual uint8_t thumbPcElrOffset() = 0;
249  virtual bool abortDisable(ThreadContext *tc) = 0;
250  virtual bool fiqDisable(ThreadContext *tc) = 0;
251  virtual ExceptionClass ec(ThreadContext *tc) const = 0;
252  virtual bool il(ThreadContext *tc) const = 0;
253  virtual uint32_t iss() const = 0;
254  virtual uint32_t vectorCatchFlag() const { return 0x0; }
255  virtual bool isStage2() const { return false; }
256  virtual FSR getFsr(ThreadContext *tc) const { return 0; }
257  virtual void setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg);
258  virtual bool getFaultVAddr(Addr &va) const { return false; }
259  OperatingMode getToMode() const { return toMode; }
260 };
261 
262 template<typename T>
263 class ArmFaultVals : public ArmFault
264 {
265  protected:
266  static FaultVals vals;
267 
268  public:
269  ArmFaultVals<T>(ExtMachInst mach_inst = 0, uint32_t _iss = 0) :
270  ArmFault(mach_inst, _iss) {}
271  FaultName name() const override { return vals.name; }
272  FaultOffset offset(ThreadContext *tc) override;
273 
274  FaultOffset offset64(ThreadContext *tc) override;
275 
276  OperatingMode nextMode() override { return vals.nextMode; }
277 
278  virtual bool
279  routeToMonitor(ThreadContext *tc) const override
280  {
281  return false;
282  }
283 
284  uint8_t
285  armPcOffset(bool is_hyp) override
286  {
287  return is_hyp ? vals.armPcElrOffset
288  : vals.armPcOffset;
289  }
290 
291  uint8_t
292  thumbPcOffset(bool is_hyp) override
293  {
294  return is_hyp ? vals.thumbPcElrOffset
296  }
297 
298  uint8_t armPcElrOffset() override { return vals.armPcElrOffset; }
299  uint8_t thumbPcElrOffset() override { return vals.thumbPcElrOffset; }
300  bool abortDisable(ThreadContext* tc) override { return vals.abortDisable; }
301  bool fiqDisable(ThreadContext* tc) override { return vals.fiqDisable; }
302 
304  ExceptionClass ec(ThreadContext *tc) const override { return vals.ec; }
305  bool
306  il(ThreadContext *tc) const override
307  {
308  // ESR.IL = 1 if exception cause is unknown (EC = 0)
309  return ec(tc) == EC_UNKNOWN || !machInst.thumb || machInst.bigThumb;
310  }
311  uint32_t iss() const override { return issRaw; }
312 };
313 
314 class Reset : public ArmFaultVals<Reset>
315 {
316  protected:
317  Addr getVector(ThreadContext *tc) override;
318 
319  public:
320  void invoke(ThreadContext *tc, const StaticInstPtr &inst =
321  nullStaticInstPtr) override;
322 };
323 
324 class UndefinedInstruction : public ArmFaultVals<UndefinedInstruction>
325 {
326  protected:
327  bool unknown;
328  bool disabled;
330  const char *mnemonic;
331 
332  public:
334  bool _unknown,
335  const char *_mnemonic = NULL,
336  bool _disabled = false) :
338  unknown(_unknown), disabled(_disabled),
339  overrideEc(EC_INVALID), mnemonic(_mnemonic)
340  {}
341  UndefinedInstruction(ExtMachInst mach_inst, uint32_t _iss,
342  ExceptionClass _overrideEc, const char *_mnemonic = NULL) :
343  ArmFaultVals<UndefinedInstruction>(mach_inst, _iss),
344  unknown(false), disabled(true), overrideEc(_overrideEc),
345  mnemonic(_mnemonic)
346  {}
347 
348  void invoke(ThreadContext *tc, const StaticInstPtr &inst =
349  nullStaticInstPtr) override;
350  bool routeToHyp(ThreadContext *tc) const override;
351  uint32_t vectorCatchFlag() const override { return 0x02000002; }
352 
354  ExceptionClass ec(ThreadContext *tc) const override;
355  uint32_t iss() const override;
356 };
357 
358 class SupervisorCall : public ArmFaultVals<SupervisorCall>
359 {
360  protected:
362  public:
363  SupervisorCall(ExtMachInst mach_inst, uint32_t _iss,
364  ExceptionClass _overrideEc = EC_INVALID) :
365  ArmFaultVals<SupervisorCall>(mach_inst, _iss),
366  overrideEc(_overrideEc)
367  {
368  bStep = true;
369  }
370 
371  void invoke(ThreadContext *tc, const StaticInstPtr &inst =
372  nullStaticInstPtr) override;
373  bool routeToHyp(ThreadContext *tc) const override;
374  uint32_t vectorCatchFlag() const override { return 0x04000404; }
375 
377  ExceptionClass ec(ThreadContext *tc) const override;
378  uint32_t iss() const override;
379 };
380 
381 class SecureMonitorCall : public ArmFaultVals<SecureMonitorCall>
382 {
383  public:
385  ArmFaultVals<SecureMonitorCall>(mach_inst)
386  {
387  bStep = true;
388  }
389 
390  void invoke(ThreadContext *tc, const StaticInstPtr &inst =
391  nullStaticInstPtr) override;
392  uint32_t vectorCatchFlag() const override { return 0x00000400; }
393 
395  ExceptionClass ec(ThreadContext *tc) const override;
396  uint32_t iss() const override;
397 };
398 
399 class SupervisorTrap : public ArmFaultVals<SupervisorTrap>
400 {
401  protected:
404 
405  public:
406  SupervisorTrap(ExtMachInst mach_inst, uint32_t _iss,
407  ExceptionClass _overrideEc = EC_INVALID) :
408  ArmFaultVals<SupervisorTrap>(mach_inst, _iss),
409  overrideEc(_overrideEc)
410  {}
411 
412  bool routeToHyp(ThreadContext *tc) const override;
413 
415  ExceptionClass ec(ThreadContext *tc) const override;
416  uint32_t iss() const override;
417 };
418 
419 class SecureMonitorTrap : public ArmFaultVals<SecureMonitorTrap>
420 {
421  protected:
424 
425  public:
426  SecureMonitorTrap(ExtMachInst mach_inst, uint32_t _iss,
427  ExceptionClass _overrideEc = EC_INVALID) :
428  ArmFaultVals<SecureMonitorTrap>(mach_inst, _iss),
429  overrideEc(_overrideEc)
430  {}
431 
433  ExceptionClass ec(ThreadContext *tc) const override;
434 };
435 
436 class HypervisorCall : public ArmFaultVals<HypervisorCall>
437 {
438  public:
439  HypervisorCall(ExtMachInst mach_inst, uint32_t _imm);
440 
441  bool routeToHyp(ThreadContext *tc) const override;
442  bool routeToMonitor(ThreadContext *tc) const override;
443  uint32_t vectorCatchFlag() const override { return 0xFFFFFFFF; }
444 
446  ExceptionClass ec(ThreadContext *tc) const override;
447 };
448 
449 class HypervisorTrap : public ArmFaultVals<HypervisorTrap>
450 {
451  protected:
454 
455  public:
456  HypervisorTrap(ExtMachInst mach_inst, uint32_t _iss,
457  ExceptionClass _overrideEc = EC_INVALID) :
458  ArmFaultVals<HypervisorTrap>(mach_inst, _iss),
459  overrideEc(_overrideEc)
460  {}
461 
463  ExceptionClass ec(ThreadContext *tc) const override;
464 };
465 
466 template <class T>
467 class AbortFault : public ArmFaultVals<T>
468 {
469  protected:
483  bool write;
485  uint8_t source;
486  uint8_t srcEncoded;
487  bool stage2;
488  bool s1ptw;
491 
492  public:
493  AbortFault(Addr _faultAddr, bool _write, TlbEntry::DomainType _domain,
494  uint8_t _source, bool _stage2,
497  faultAddr(_faultAddr), OVAddr(0), write(_write),
498  domain(_domain), source(_source), srcEncoded(0),
499  stage2(_stage2), s1ptw(false), tranMethod(_tranMethod),
500  debugType(_debug)
501  {}
502 
503  bool getFaultVAddr(Addr &va) const override;
504 
505  void invoke(ThreadContext *tc, const StaticInstPtr &inst =
506  nullStaticInstPtr) override;
507 
508  FSR getFsr(ThreadContext *tc) const override;
509  uint8_t getFaultStatusCode(ThreadContext *tc) const;
510  bool abortDisable(ThreadContext *tc) override;
511  bool isStage2() const override { return stage2; }
512  void annotate(ArmFault::AnnotationIDs id, uint64_t val) override;
513  void setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg) override;
514  bool isMMUFault() const;
515 };
516 
517 class PrefetchAbort : public AbortFault<PrefetchAbort>
518 {
519  public:
523 
524  PrefetchAbort(Addr _addr, uint8_t _source, bool _stage2 = false,
527  AbortFault<PrefetchAbort>(_addr, false, TlbEntry::DomainType::NoAccess,
528  _source, _stage2, _tranMethod, _debug)
529  {}
530 
531  // @todo: external aborts should be routed if SCR.EA == 1
532  bool routeToMonitor(ThreadContext *tc) const override;
533  bool routeToHyp(ThreadContext *tc) const override;
534  uint32_t vectorCatchFlag() const override { return 0x08000808; }
535 
537  ExceptionClass ec(ThreadContext *tc) const override;
538  bool il(ThreadContext *tc) const override { return true; }
539  uint32_t iss() const override;
540 };
541 
542 class DataAbort : public AbortFault<DataAbort>
543 {
544  public:
548  bool isv;
549  uint8_t sas;
550  uint8_t sse;
551  uint8_t srt;
552  uint8_t cm;
553 
554  // AArch64 only
555  bool sf;
556  bool ar;
557 
558  DataAbort(Addr _addr, TlbEntry::DomainType _domain, bool _write, uint8_t _source,
559  bool _stage2=false,
562  AbortFault<DataAbort>(_addr, _write, _domain, _source, _stage2,
563  _tranMethod, _debug_type),
564  isv(false), sas (0), sse(0), srt(0), cm(0), sf(false), ar(false)
565  {}
566 
567  // @todo: external aborts should be routed if SCR.EA == 1
568  bool routeToMonitor(ThreadContext *tc) const override;
569  bool routeToHyp(ThreadContext *tc) const override;
570  void annotate(AnnotationIDs id, uint64_t val) override;
571  uint32_t vectorCatchFlag() const override { return 0x10001010; }
572 
574  ExceptionClass ec(ThreadContext *tc) const override;
575  bool il(ThreadContext *tc) const override;
576  uint32_t iss() const override;
577 };
578 
579 class VirtualDataAbort : public AbortFault<VirtualDataAbort>
580 {
581  public:
585 
586  VirtualDataAbort(Addr _addr, TlbEntry::DomainType _domain, bool _write,
587  uint8_t _source) :
588  AbortFault<VirtualDataAbort>(_addr, _write, _domain, _source, false)
589  {}
590 
591  void invoke(ThreadContext *tc, const StaticInstPtr &inst) override;
592 };
593 
594 class Interrupt : public ArmFaultVals<Interrupt>
595 {
596  public:
597  bool routeToMonitor(ThreadContext *tc) const override;
598  bool routeToHyp(ThreadContext *tc) const override;
599  bool abortDisable(ThreadContext *tc) override;
600  uint32_t vectorCatchFlag() const override { return 0x40004040; }
601 };
602 
603 class VirtualInterrupt : public ArmFaultVals<VirtualInterrupt>
604 {
605  public:
607 };
608 
609 class FastInterrupt : public ArmFaultVals<FastInterrupt>
610 {
611  public:
612  bool routeToMonitor(ThreadContext *tc) const override;
613  bool routeToHyp(ThreadContext *tc) const override;
614  bool abortDisable(ThreadContext *tc) override;
615  bool fiqDisable(ThreadContext *tc) override;
616  uint32_t vectorCatchFlag() const override { return 0x80008080; }
617 };
618 
619 class VirtualFastInterrupt : public ArmFaultVals<VirtualFastInterrupt>
620 {
621  public:
623 };
624 
626 class PCAlignmentFault : public ArmFaultVals<PCAlignmentFault>
627 {
628  protected:
631  public:
632  PCAlignmentFault(Addr fault_pc) : faultPC(fault_pc)
633  {}
634  void invoke(ThreadContext *tc, const StaticInstPtr &inst =
635  nullStaticInstPtr) override;
636  bool routeToHyp(ThreadContext *tc) const override;
637 
639  bool il(ThreadContext *tc) const override { return true; }
640 };
641 
643 class SPAlignmentFault : public ArmFaultVals<SPAlignmentFault>
644 {
645  public:
647  bool routeToHyp(ThreadContext *tc) const override;
648 
650  bool il(ThreadContext *tc) const override { return true; }
651 };
652 
654 class SystemError : public ArmFaultVals<SystemError>
655 {
656  public:
657  SystemError();
658  void invoke(ThreadContext *tc, const StaticInstPtr &inst =
659  nullStaticInstPtr) override;
660  bool routeToMonitor(ThreadContext *tc) const override;
661  bool routeToHyp(ThreadContext *tc) const override;
662 
664  bool il(ThreadContext *tc) const override { return true; }
665 };
666 
668 class SoftwareBreakpoint : public ArmFaultVals<SoftwareBreakpoint>
669 {
670  public:
671  SoftwareBreakpoint(ExtMachInst mach_inst, uint32_t _iss);
672  bool routeToHyp(ThreadContext *tc) const override;
673 
675  ExceptionClass ec(ThreadContext *tc) const override;
676 };
677 
678 class HardwareBreakpoint : public ArmFaultVals<HardwareBreakpoint>
679 {
680  private:
682  public:
683  void invoke(ThreadContext *tc, const StaticInstPtr &inst =
684  nullStaticInstPtr) override;
685  HardwareBreakpoint(Addr _vaddr, uint32_t _iss);
686  bool routeToHyp(ThreadContext *tc) const override;
687 
689  ExceptionClass ec(ThreadContext *tc) const override;
690  bool il(ThreadContext *tc) const override { return true; }
691 };
692 
693 class Watchpoint : public ArmFaultVals<Watchpoint>
694 {
695  private:
697  bool write;
698  bool cm;
699 
700  public:
701  Watchpoint(ExtMachInst mach_inst, Addr vaddr, bool _write, bool _cm);
702  void invoke(ThreadContext *tc, const StaticInstPtr &inst =
703  nullStaticInstPtr) override;
704  bool routeToHyp(ThreadContext *tc) const override;
705  void annotate(AnnotationIDs id, uint64_t val) override;
706 
708  ExceptionClass ec(ThreadContext *tc) const override;
709  bool il(ThreadContext *tc) const override { return true; }
710  uint32_t iss() const override;
711 };
712 
713 class SoftwareStepFault : public ArmFaultVals<SoftwareStepFault>
714 {
715  private:
716  bool isldx;
717  bool stepped;
718 
719  public:
720  SoftwareStepFault(ExtMachInst mach_inst, bool is_ldx, bool stepped);
721  bool routeToHyp(ThreadContext *tc) const override;
722 
724  ExceptionClass ec(ThreadContext *tc) const override;
725  bool il(ThreadContext *tc) const override { return true; }
726  uint32_t iss() const override;
727 };
728 
729 // A fault that flushes the pipe, excluding the faulting instructions
730 class ArmSev : public ArmFaultVals<ArmSev>
731 {
732  public:
733  ArmSev() {}
734  void invoke(ThreadContext *tc, const StaticInstPtr &inst =
735  nullStaticInstPtr) override;
736 };
737 
739 class IllegalInstSetStateFault : public ArmFaultVals<IllegalInstSetStateFault>
740 {
741  public:
743  bool routeToHyp(ThreadContext *tc) const override;
744 
746  bool il(ThreadContext *tc) const override { return true; }
747 };
748 
749 /*
750  * Explicitly declare template static member variables to avoid warnings
751  * in some clang versions
752  */
777 
788 bool getFaultVAddr(Fault fault, Addr &va);
789 
790 } // namespace ArmISA
791 } // namespace gem5
792 
793 #endif // __ARM_FAULTS_HH__
gem5::ArmISA::ArmFault::FaultVals::thumbPcElrOffset
const uint8_t thumbPcElrOffset
Definition: faults.hh:186
gem5::ArmISA::MISCREG_DFAR
@ MISCREG_DFAR
Definition: misc.hh:284
gem5::ArmISA::ArmFault::NODEBUG
@ NODEBUG
Definition: faults.hh:159
gem5::ArmISA::ArmFault::fromEL
ExceptionLevel fromEL
Definition: faults.hh:74
gem5::ArmISA::AbortFault::annotate
void annotate(ArmFault::AnnotationIDs id, uint64_t val) override
Definition: faults.cc:1223
gem5::ArmISA::AbortFault::setSyndrome
void setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg) override
Definition: faults.cc:1150
gem5::ArmISA::ArmFault::FaultVals::ec
const ExceptionClass ec
Definition: faults.hh:194
gem5::ArmISA::ArmFault::NumFaultSources
@ NumFaultSources
Definition: faults.hh:119
gem5::ArmISA::SupervisorTrap::ec
ExceptionClass ec(ThreadContext *tc) const override
Syndrome methods.
Definition: faults.cc:1051
gem5::ArmISA::UndefinedInstruction::mnemonic
const char * mnemonic
Definition: faults.hh:330
gem5::ArmISA::SPAlignmentFault::SPAlignmentFault
SPAlignmentFault()
Definition: faults.cc:1569
gem5::ArmISA::DataAbort::routeToMonitor
bool routeToMonitor(ThreadContext *tc) const override
Definition: faults.cc:1365
gem5::ArmISA::UndefinedInstruction::ec
ExceptionClass ec(ThreadContext *tc) const override
Syndrome methods.
Definition: faults.cc:915
gem5::ArmISA::ArmFaultVals::thumbPcElrOffset
uint8_t thumbPcElrOffset() override
Definition: faults.hh:299
gem5::ArmISA::SoftwareBreakpoint::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1616
gem5::ArmISA::ArmFault::FaultVals::lowerEL32Offset
const uint16_t lowerEL32Offset
Definition: faults.hh:176
gem5::ArmISA::ArmFault::AddressSizeLL
@ AddressSizeLL
Definition: faults.hh:111
gem5::ArmISA::DataAbort::sf
bool sf
Definition: faults.hh:555
gem5::ArmISA::PrefetchAbort::FsrIndex
static const MiscRegIndex FsrIndex
Definition: faults.hh:520
gem5::ArmISA::ArmFault::bStep
bool bStep
Definition: faults.hh:71
gem5::ArmISA::AbortFault::AbortFault
AbortFault(Addr _faultAddr, bool _write, TlbEntry::DomainType _domain, uint8_t _source, bool _stage2, ArmFault::TranMethod _tranMethod=ArmFault::UnknownTran, ArmFault::DebugType _debug=ArmFault::NODEBUG)
Definition: faults.hh:493
gem5::ArmISA::ArmFault::FaultSourceInvalid
@ FaultSourceInvalid
Definition: faults.hh:120
gem5::ArmISA::PCAlignmentFault::faultPC
Addr faultPC
The unaligned value of the PC.
Definition: faults.hh:630
gem5::ArmISA::ArmFault::abortDisable
virtual bool abortDisable(ThreadContext *tc)=0
gem5::ArmISA::VirtualDataAbort
Definition: faults.hh:579
gem5::ArmISA::ArmStaticInst
Definition: static_inst.hh:65
gem5::ArmISA::ArmFault::BRKPOINT
@ BRKPOINT
Definition: faults.hh:160
gem5::ArmISA::IllegalInstSetStateFault::il
bool il(ThreadContext *tc) const override
Syndrome methods.
Definition: faults.hh:746
gem5::ArmISA::HypervisorCall
Definition: faults.hh:436
gem5::ArmISA::PrefetchAbort::vectorCatchFlag
uint32_t vectorCatchFlag() const override
Definition: faults.hh:534
gem5::ArmISA::ArmFault::issRaw
uint32_t issRaw
Definition: faults.hh:68
gem5::ArmISA::ArmFaultVals::il
bool il(ThreadContext *tc) const override
Definition: faults.hh:306
gem5::ArmISA::ArmFault::AR
@ AR
Definition: faults.hh:147
gem5::ArmISA::HypervisorTrap::HypervisorTrap
HypervisorTrap(ExtMachInst mach_inst, uint32_t _iss, ExceptionClass _overrideEc=EC_INVALID)
Definition: faults.hh:456
gem5::ArmISA::SystemError::SystemError
SystemError()
Definition: faults.cc:1580
gem5::ArmISA::HypervisorTrap::overrideEc
ExceptionClass overrideEc
Definition: faults.hh:453
gem5::ArmISA::ArmFaultVals::vals
static FaultVals vals
Definition: faults.hh:266
gem5::ArmISA::SecureMonitorCall::ec
ExceptionClass ec(ThreadContext *tc) const override
Syndrome methods.
Definition: faults.cc:1028
gem5::ArmISA::ArmFault::from64
bool from64
Definition: faults.hh:72
gem5::ArmISA::HypervisorCall::vectorCatchFlag
uint32_t vectorCatchFlag() const override
Definition: faults.hh:443
gem5::ArmISA::MODE_UNDEFINED
@ MODE_UNDEFINED
Definition: types.hh:295
gem5::ArmISA::HardwareBreakpoint::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1636
gem5::ArmISA::ArmFault::SynchExtAbtOnTranslTableWalkLL
@ SynchExtAbtOnTranslTableWalkLL
Definition: faults.hh:99
gem5::ArmISA::ArmFault::PrefetchUncacheable
@ PrefetchUncacheable
Definition: faults.hh:117
gem5::ArmISA::UndefinedInstruction::UndefinedInstruction
UndefinedInstruction(ExtMachInst mach_inst, bool _unknown, const char *_mnemonic=NULL, bool _disabled=false)
Definition: faults.hh:333
gem5::ArmISA::ArmFault::VECTORCATCH
@ VECTORCATCH
Definition: faults.hh:161
gem5::ArmISA::Interrupt::vectorCatchFlag
uint32_t vectorCatchFlag() const override
Definition: faults.hh:600
gem5::ArmISA::SupervisorCall::vectorCatchFlag
uint32_t vectorCatchFlag() const override
Definition: faults.hh:374
gem5::ArmISA::SupervisorCall
Definition: faults.hh:358
gem5::ArmISA::HypervisorTrap
Definition: faults.hh:449
gem5::ArmISA::PrefetchAbort::HFarIndex
static const MiscRegIndex HFarIndex
Definition: faults.hh:522
gem5::ArmISA::HypervisorTrap::ec
ExceptionClass ec(ThreadContext *tc) const override
Syndrome methods.
Definition: faults.cc:951
gem5::ArmISA::UndefinedInstruction
Definition: faults.hh:324
gem5::ArmISA::UndefinedInstruction::overrideEc
ExceptionClass overrideEc
Definition: faults.hh:329
pagetable.hh
gem5::ArmISA::UndefinedInstruction::disabled
bool disabled
Definition: faults.hh:328
gem5::ArmISA::ArmFault::SynchronousExternalAbort
@ SynchronousExternalAbort
Definition: faults.hh:106
gem5::ArmISA::ArmFault::LpaeTran
@ LpaeTran
Definition: faults.hh:152
gem5::ArmISA::ArmFaultVals::abortDisable
bool abortDisable(ThreadContext *tc) override
Definition: faults.hh:300
gem5::ArmISA::ArmFault::faultUpdated
bool faultUpdated
Definition: faults.hh:82
gem5::ArmISA::ArmFault::PrefetchTLBMiss
@ PrefetchTLBMiss
Definition: faults.hh:116
gem5::ArmISA::ArmFault::SSE
@ SSE
Definition: faults.hh:137
gem5::ArmISA::UndefinedInstruction::unknown
bool unknown
Definition: faults.hh:327
gem5::ArmISA::DataAbort::iss
uint32_t iss() const override
Definition: faults.cc:1401
gem5::ArmISA::FastInterrupt::vectorCatchFlag
uint32_t vectorCatchFlag() const override
Definition: faults.hh:616
gem5::ArmISA::PCAlignmentFault::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1563
gem5::ArmISA::ArmFault::ArmFault
ArmFault(ExtMachInst mach_inst=0, uint32_t _iss=0)
Definition: faults.hh:215
gem5::ArmISA::HypervisorCall::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:939
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:769
gem5::ArmISA::ArmFault::armPcElrOffset
virtual uint8_t armPcElrOffset()=0
gem5::ArmISA::HardwareBreakpoint::il
bool il(ThreadContext *tc) const override
Definition: faults.hh:690
gem5::ArmISA::Watchpoint::vAddr
Addr vAddr
Definition: faults.hh:696
gem5::ArmISA::AbortFault::getFaultStatusCode
uint8_t getFaultStatusCode(ThreadContext *tc) const
Definition: faults.cc:1161
gem5::ArmISA::PrefetchAbort::routeToMonitor
bool routeToMonitor(ThreadContext *tc) const override
Definition: faults.cc:1303
gem5::ArmISA::ArmSev
Definition: faults.hh:730
gem5::ArmISA::PCAlignmentFault
PC alignment fault (AArch64 only)
Definition: faults.hh:626
gem5::ArmISA::MISCREG_HIFAR
@ MISCREG_HIFAR
Definition: misc.hh:291
gem5::ArmISA::ArmFault::DomainLL
@ DomainLL
Definition: faults.hh:103
gem5::ArmISA::Interrupt::routeToMonitor
bool routeToMonitor(ThreadContext *tc) const override
Definition: faults.cc:1476
gem5::ArmISA::SupervisorTrap::SupervisorTrap
SupervisorTrap(ExtMachInst mach_inst, uint32_t _iss, ExceptionClass _overrideEc=EC_INVALID)
Definition: faults.hh:406
gem5::ArmISA::ArmFault::SynchPtyErrOnMemoryAccess
@ SynchPtyErrOnMemoryAccess
Definition: faults.hh:108
gem5::ArmISA::ArmFault::offset64
virtual FaultOffset offset64(ThreadContext *tc)=0
gem5::ArmISA::ArmFault::DebugEvent
@ DebugEvent
Definition: faults.hh:105
gem5::ArmISA::Watchpoint::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1708
gem5::ArmISA::AbortFault::debugType
ArmFault::DebugType debugType
Definition: faults.hh:490
gem5::ArmISA::ArmFault::FaultVals
Definition: faults.hh:166
gem5::ArmISA::Watchpoint
Definition: faults.hh:693
gem5::ArmISA::ArmFault::FaultVals::hypTrappable
const bool hypTrappable
Definition: faults.hh:188
gem5::ArmISA::PrefetchAbort::FarIndex
static const MiscRegIndex FarIndex
Definition: faults.hh:521
gem5::ArmISA::ArmFault::getToMode
OperatingMode getToMode() const
Definition: faults.hh:259
gem5::ArmISA::SupervisorTrap::iss
uint32_t iss() const override
Definition: faults.cc:1041
gem5::ArmISA::UndefinedInstruction::vectorCatchFlag
uint32_t vectorCatchFlag() const override
Definition: faults.hh:351
gem5::ArmISA::HardwareBreakpoint::vAddr
Addr vAddr
Definition: faults.hh:681
gem5::ArmISA::ArmFault::thumbPcOffset
virtual uint8_t thumbPcOffset(bool is_hyp)=0
gem5::ArmISA::VirtualDataAbort::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst) override
Definition: faults.cc:1467
gem5::ArmISA::SoftwareStepFault::isldx
bool isldx
Definition: faults.hh:716
gem5::ArmISA::ArmFault::setSyndrome
virtual void setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg)
Definition: faults.cc:398
gem5::ArmISA::ArmFault::to64
bool to64
Definition: faults.hh:73
gem5::ArmISA::getFaultVAddr
bool getFaultVAddr(Fault fault, Addr &va)
Returns true if the fault passed as a first argument was triggered by a memory access,...
Definition: faults.cc:1835
faults.hh
types.hh
gem5::ArmISA::ArmFault::FaultVals::currELTOffset
const uint16_t currELTOffset
Definition: faults.hh:173
gem5::ArmISA::ArmFault::FaultVals::thumbPcOffset
const uint8_t thumbPcOffset
Definition: faults.hh:181
gem5::ArmISA::SoftwareBreakpoint::ec
ExceptionClass ec(ThreadContext *tc) const override
Syndrome methods.
Definition: faults.cc:1626
gem5::ArmISA::ArmFaultVals::thumbPcOffset
uint8_t thumbPcOffset(bool is_hyp) override
Definition: faults.hh:292
gem5::ArmISA::SystemError::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1600
gem5::ArmISA::ArmFault::getVector64
Addr getVector64(ThreadContext *tc)
Definition: faults.cc:343
gem5::ArmISA::SystemError::routeToMonitor
bool routeToMonitor(ThreadContext *tc) const override
Definition: faults.cc:1591
gem5::ArmISA::TlbEntry
Definition: pagetable.hh:165
gem5::ArmISA::ArmFault::PermissionLL
@ PermissionLL
Definition: faults.hh:104
gem5::ArmISA::TlbEntry::DomainType
DomainType
Definition: pagetable.hh:177
gem5::ArmISA::SecureMonitorTrap
Definition: faults.hh:419
gem5::ArmISA::ArmSev::ArmSev
ArmSev()
Definition: faults.hh:733
gem5::ArmISA::ArmFault::AsynchronousExternalAbort
@ AsynchronousExternalAbort
Definition: faults.hh:109
gem5::ArmISA::PCAlignmentFault::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:1554
gem5::RefCountingPtr< StaticInst >
gem5::ArmISA::ArmFault::VmsaTran
@ VmsaTran
Definition: faults.hh:153
gem5::ArmISA::DataAbort
Definition: faults.hh:542
gem5::ArmISA::AbortFault::getFsr
FSR getFsr(ThreadContext *tc) const override
Definition: faults.cc:1187
gem5::ArmISA::PrefetchAbort::il
bool il(ThreadContext *tc) const override
Definition: faults.hh:538
gem5::ArmISA::SupervisorCall::iss
uint32_t iss() const override
Definition: faults.cc:899
gem5::ArmISA::MISCREG_IFSR
@ MISCREG_IFSR
Definition: misc.hh:272
gem5::ArmISA::ArmFaultVals::nextMode
OperatingMode nextMode() override
Definition: faults.hh:276
gem5::ArmISA::ArmFault::OFA
@ OFA
Definition: faults.hh:140
gem5::ArmISA::ArmFault::iss
virtual uint32_t iss() const =0
gem5::ArmISA::FastInterrupt::abortDisable
bool abortDisable(ThreadContext *tc) override
Definition: faults.cc:1529
gem5::ArmISA::Watchpoint::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:1699
gem5::ArmISA::ArmFault::instrAnnotate
ArmStaticInst * instrAnnotate(const StaticInstPtr &inst)
Definition: faults.cc:747
gem5::ArmISA::DataAbort::FarIndex
static const MiscRegIndex FarIndex
Definition: faults.hh:546
gem5::nullStaticInstPtr
const StaticInstPtr nullStaticInstPtr
Statically allocated null StaticInstPtr.
Definition: null_static_inst.cc:36
gem5::ArmISA::ArmFault::thumbPcElrOffset
virtual uint8_t thumbPcElrOffset()=0
gem5::ArmISA::ArmFaultVals
Definition: faults.hh:263
gem5::ArmISA::SystemError::il
bool il(ThreadContext *tc) const override
Syndrome methods.
Definition: faults.hh:664
gem5::ArmISA::PCAlignmentFault::il
bool il(ThreadContext *tc) const override
Syndrome methods.
Definition: faults.hh:639
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::ArmISA::EC_UNKNOWN
@ EC_UNKNOWN
Definition: types.hh:303
gem5::ArmISA::ArmFault::offset
virtual FaultOffset offset(ThreadContext *tc)=0
gem5::ArmISA::Reset
Definition: faults.hh:314
gem5::ArmISA::SoftwareStepFault
Definition: faults.hh:713
gem5::ArmISA::HardwareBreakpoint
Definition: faults.hh:678
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:248
gem5::ArmISA::ArmFault::FaultSource
FaultSource
Generic fault source enums used to index into {short/long/aarch64}DescFaultSources[] to get the actua...
Definition: faults.hh:95
gem5::ArmISA::ArmFault::getSyndromeReg64
MiscRegIndex getSyndromeReg64() const
Definition: faults.cc:366
gem5::ArmISA::SecureMonitorCall::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:1019
gem5::ArmISA::AbortFault::domain
TlbEntry::DomainType domain
Definition: faults.hh:484
gem5::ArmISA::DataAbort::DataAbort
DataAbort(Addr _addr, TlbEntry::DomainType _domain, bool _write, uint8_t _source, bool _stage2=false, ArmFault::TranMethod _tranMethod=ArmFault::UnknownTran, ArmFault::DebugType _debug_type=ArmFault::NODEBUG)
Definition: faults.hh:558
gem5::ArmISA::ArmFaultVals::armPcElrOffset
uint8_t armPcElrOffset() override
Definition: faults.hh:298
gem5::ArmISA::ArmFault::toEL
ExceptionLevel toEL
Definition: faults.hh:75
gem5::ArmISA::SecureMonitorCall
Definition: faults.hh:381
gem5::ArmISA::DataAbort::ec
ExceptionClass ec(ThreadContext *tc) const override
Syndrome methods.
Definition: faults.cc:1330
gem5::ArmISA::DataAbort::vectorCatchFlag
uint32_t vectorCatchFlag() const override
Definition: faults.hh:571
gem5::ArmISA::SecureMonitorTrap::ec
ExceptionClass ec(ThreadContext *tc) const override
Syndrome methods.
Definition: faults.cc:1060
gem5::ArmISA::FastInterrupt::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1521
gem5::ArmISA::ArmFault::hypRouted
bool hypRouted
Definition: faults.hh:84
gem5::ArmISA::SupervisorTrap::machInst
ExtMachInst machInst
Definition: faults.hh:402
gem5::ArmISA::ArmFault::vectorCatchFlag
virtual uint32_t vectorCatchFlag() const
Definition: faults.hh:254
gem5::ArmISA::SupervisorCall::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:865
gem5::ArmISA::ArmFault::SynchPtyErrOnTranslTableWalkLL
@ SynchPtyErrOnTranslTableWalkLL
Definition: faults.hh:100
gem5::ArmISA::ArmFault::shortDescFaultSources
static uint8_t shortDescFaultSources[NumFaultSources]
Encodings of the fault sources when the short-desc.
Definition: faults.hh:125
gem5::ArmISA::DataAbort::sas
uint8_t sas
Definition: faults.hh:549
gem5::ArmISA::ArmFault::FaultVals::name
const FaultName name
Definition: faults.hh:168
gem5::ArmISA::SupervisorTrap
Definition: faults.hh:399
gem5::ArmISA::ArmFault::update
void update(ThreadContext *tc)
Definition: faults.cc:428
gem5::ArmISA::VirtualFastInterrupt
Definition: faults.hh:619
gem5::ArmISA::HypervisorTrap::machInst
ExtMachInst machInst
Definition: faults.hh:452
gem5::ArmISA::ArmFaultVals::offset64
FaultOffset offset64(ThreadContext *tc) override
Definition: faults.cc:978
gem5::ArmISA::PCAlignmentFault::PCAlignmentFault
PCAlignmentFault(Addr fault_pc)
Definition: faults.hh:632
gem5::ArmISA::UndefinedInstruction::UndefinedInstruction
UndefinedInstruction(ExtMachInst mach_inst, uint32_t _iss, ExceptionClass _overrideEc, const char *_mnemonic=NULL)
Definition: faults.hh:341
gem5::ArmISA::ArmFault::getFaultVAddr
virtual bool getFaultVAddr(Addr &va) const
Definition: faults.hh:258
gem5::ArmISA::SoftwareStepFault::il
bool il(ThreadContext *tc) const override
Definition: faults.hh:725
gem5::ArmISA::Watchpoint::cm
bool cm
Definition: faults.hh:698
gem5::ArmISA::ArmFault::armPcOffset
virtual uint8_t armPcOffset(bool is_hyp)=0
gem5::ArmISA::SecureMonitorCall::iss
uint32_t iss() const override
Definition: faults.cc:907
gem5::ArmISA::UndefinedInstruction::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:828
gem5::ArmISA::AbortFault::abortDisable
bool abortDisable(ThreadContext *tc) override
Definition: faults.cc:1212
gem5::ArmISA::UndefinedInstruction::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:805
gem5::ArmISA::ArmFault::FaultVals::offset
const FaultOffset offset
Definition: faults.hh:170
gem5::ArmISA::SupervisorTrap::overrideEc
ExceptionClass overrideEc
Definition: faults.hh:403
gem5::ArmISA::ArmFault::WPOINT_NOCM
@ WPOINT_NOCM
Definition: faults.hh:163
gem5::PowerISA::AlignmentFault
Definition: faults.hh:82
gem5::ArmISA::ArmFault::FaultVals::armPcOffset
const uint8_t armPcOffset
Definition: faults.hh:180
gem5::ArmISA::MISCREG_IFAR
@ MISCREG_IFAR
Definition: misc.hh:287
gem5::ArmISA::DataAbort::srt
uint8_t srt
Definition: faults.hh:551
gem5::ArmISA::ArmFault::FaultVals::lowerEL64Offset
const uint16_t lowerEL64Offset
Definition: faults.hh:175
gem5::ArmISA::VirtualInterrupt::VirtualInterrupt
VirtualInterrupt()
Definition: faults.cc:1505
gem5::ArmISA::DataAbort::annotate
void annotate(AnnotationIDs id, uint64_t val) override
Definition: faults.cc:1429
gem5::ArmISA::ArmFault::SF
@ SF
Definition: faults.hh:146
gem5::ArmISA::Watchpoint::il
bool il(ThreadContext *tc) const override
Definition: faults.hh:709
gem5::ArmISA::DataAbort::il
bool il(ThreadContext *tc) const override
Definition: faults.cc:1359
gem5::ArmISA::ArmFault::nextMode
virtual OperatingMode nextMode()=0
gem5::ArmISA::FastInterrupt::fiqDisable
bool fiqDisable(ThreadContext *tc) override
Definition: faults.cc:1539
gem5::ArmISA::ArmFault::FaultVals::abortDisable
const bool abortDisable
Definition: faults.hh:189
gem5::ArmISA::PrefetchAbort::iss
uint32_t iss() const override
Definition: faults.cc:1291
gem5::ArmISA::DataAbort::cm
uint8_t cm
Definition: faults.hh:552
gem5::ArmISA::MISCREG_HDFAR
@ MISCREG_HDFAR
Definition: misc.hh:290
null_static_inst.hh
gem5::ArmISA::AbortFault::isStage2
bool isStage2() const override
Definition: faults.hh:511
gem5::ArmISA::VirtualDataAbort::HFarIndex
static const MiscRegIndex HFarIndex
Definition: faults.hh:584
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::PrefetchAbort::PrefetchAbort
PrefetchAbort(Addr _addr, uint8_t _source, bool _stage2=false, ArmFault::TranMethod _tranMethod=ArmFault::UnknownTran, ArmFault::DebugType _debug=ArmFault::NODEBUG)
Definition: faults.hh:524
gem5::ArmISA::SoftwareBreakpoint
Software Breakpoint (AArch64 only)
Definition: faults.hh:668
gem5::ArmISA::ArmFaultVals::offset
FaultOffset offset(ThreadContext *tc) override
Definition: faults.cc:958
gem5::ArmISA::ArmFault::AsynchPtyErrOnMemoryAccess
@ AsynchPtyErrOnMemoryAccess
Definition: faults.hh:110
gem5::ArmISA::PrefetchAbort
Definition: faults.hh:517
gem5::ArmISA::SoftwareStepFault::iss
uint32_t iss() const override
Definition: faults.cc:1771
gem5::ArmISA::MISCREG_DFSR
@ MISCREG_DFSR
Definition: misc.hh:269
gem5::ArmISA::HypervisorCall::ec
ExceptionClass ec(ThreadContext *tc) const override
Syndrome methods.
Definition: faults.cc:945
gem5::ArmISA::MiscRegIndex
MiscRegIndex
Definition: misc.hh:59
gem5::ArmISA::HardwareBreakpoint::ec
ExceptionClass ec(ThreadContext *tc) const override
Syndrome methods.
Definition: faults.cc:1645
gem5::ArmISA::ArmFaultVals::routeToMonitor
virtual bool routeToMonitor(ThreadContext *tc) const override
Definition: faults.hh:279
gem5::ArmISA::DataAbort::FsrIndex
static const MiscRegIndex FsrIndex
Definition: faults.hh:545
gem5::ArmISA::va
Bitfield< 8 > va
Definition: misc_types.hh:276
gem5::ArmISA::ArmFault::getFsr
virtual FSR getFsr(ThreadContext *tc) const
Definition: faults.hh:256
gem5::ArmISA::ArmFault::InstructionCacheMaintenance
@ InstructionCacheMaintenance
Definition: faults.hh:98
gem5::ArmISA::AbortFault::getFaultVAddr
bool getFaultVAddr(Addr &va) const override
Definition: faults.cc:1259
gem5::ArmISA::AbortFault::OVAddr
Addr OVAddr
Original virtual address.
Definition: faults.hh:482
gem5::ArmISA::ExceptionClass
ExceptionClass
Definition: types.hh:300
gem5::ArmISA::SoftwareStepFault::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1751
full_system.hh
gem5::FaultName
const typedef char * FaultName
Definition: faults.hh:53
gem5::ArmISA::ArmFault::getFaultAddrReg64
MiscRegIndex getFaultAddrReg64() const
Definition: faults.cc:382
gem5::ArmISA::HardwareBreakpoint::HardwareBreakpoint
HardwareBreakpoint(Addr _vaddr, uint32_t _iss)
Definition: faults.cc:1631
gem5::ArmISA::Reset::getVector
Addr getVector(ThreadContext *tc) override
Definition: faults.cc:759
gem5::ArmISA::AbortFault::srcEncoded
uint8_t srcEncoded
Definition: faults.hh:486
gem5::ArmISA::ArmFault
Definition: faults.hh:64
gem5::ArmISA::ArmFault::FaultVals::currELHOffset
const uint16_t currELHOffset
Definition: faults.hh:174
gem5::ArmISA::AbortFault::faultAddr
Addr faultAddr
The virtual address the fault occured at.
Definition: faults.hh:476
gem5::ArmISA::FaultOffset
Addr FaultOffset
Definition: faults.hh:60
gem5::ArmISA::ArmFault::FaultVals::fiqDisable
const bool fiqDisable
Definition: faults.hh:190
gem5::X86ISA::ExtMachInst
Definition: types.hh:212
gem5::ArmISA::ArmFault::aarch64FaultSources
static uint8_t aarch64FaultSources[NumFaultSources]
Encodings of the fault sources in AArch64 state.
Definition: faults.hh:130
gem5::ArmISA::SupervisorCall::overrideEc
ExceptionClass overrideEc
Definition: faults.hh:361
gem5::ArmISA::Watchpoint::Watchpoint
Watchpoint(ExtMachInst mach_inst, Addr vaddr, bool _write, bool _cm)
Definition: faults.cc:1681
gem5::ArmISA::PrefetchAbort::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1315
gem5::ArmISA::EL0
@ EL0
Definition: types.hh:273
gem5::ArmISA::ArmFaultVals::armPcOffset
uint8_t armPcOffset(bool is_hyp) override
Definition: faults.hh:285
gem5::ArmISA::ArmFault::TranMethod
TranMethod
Definition: faults.hh:150
gem5::ArmISA::SupervisorCall::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:884
gem5::ArmISA::ArmFault::invoke64
void invoke64(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)
Definition: faults.cc:637
gem5::ArmISA::ArmFault::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:477
gem5::ArmISA::SupervisorTrap::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1034
gem5::ArmISA::DataAbort::isv
bool isv
Definition: faults.hh:548
gem5::ArmISA::Watchpoint::annotate
void annotate(AnnotationIDs id, uint64_t val) override
Definition: faults.cc:1718
gem5::ArmISA::SystemError
System error (AArch64 only)
Definition: faults.hh:654
gem5::ArmISA::AbortFault::isMMUFault
bool isMMUFault() const
Definition: faults.cc:1242
gem5::ArmISA::ArmFault::getVector
virtual Addr getVector(ThreadContext *tc)
Definition: faults.cc:311
gem5::ArmISA::ArmFault::isResetSPSR
bool isResetSPSR()
Definition: faults.hh:234
gem5::ArmISA::ArmFaultVals::name
FaultName name() const override
Definition: faults.hh:271
gem5::ArmISA::ArmFault::CM
@ CM
Definition: faults.hh:139
gem5::FaultBase
Definition: translation_gen.test.cc:49
gem5::ArmISA::Watchpoint::iss
uint32_t iss() const override
Definition: faults.cc:1688
gem5::ArmISA::FastInterrupt
Definition: faults.hh:609
gem5::ArmISA::SPAlignmentFault
Stack pointer alignment fault (AArch64 only)
Definition: faults.hh:643
gem5::ArmISA::AbortFault::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:1068
gem5::ArmISA::ArmFault::span
bool span
Definition: faults.hh:85
gem5::ArmISA::ArmFault::TranslationLL
@ TranslationLL
Definition: faults.hh:101
gem5::ArmISA::AbortFault::stage2
bool stage2
Definition: faults.hh:487
misc.hh
gem5::ArmISA::ArmFault::WPOINT_CM
@ WPOINT_CM
Definition: faults.hh:162
gem5::ArmISA::SecureMonitorCall::SecureMonitorCall
SecureMonitorCall(ExtMachInst mach_inst)
Definition: faults.hh:384
gem5::ArmISA::ArmFaultVals::ec
ExceptionClass ec(ThreadContext *tc) const override
Syndrome methods.
Definition: faults.hh:304
gem5::ArmISA::ArmFault::ec
virtual ExceptionClass ec(ThreadContext *tc) const =0
gem5::ArmISA::SoftwareBreakpoint::SoftwareBreakpoint
SoftwareBreakpoint(ExtMachInst mach_inst, uint32_t _iss)
Definition: faults.cc:1611
gem5::ArmISA::ArmFault::AnnotationIDs
AnnotationIDs
Definition: faults.hh:132
gem5::ArmISA::ArmFault::DebugType
DebugType
Definition: faults.hh:157
gem5::ArmISA::ArmFault::annotate
virtual void annotate(AnnotationIDs id, uint64_t val)
Definition: faults.hh:239
logging.hh
gem5::ArmISA::ArmFault::TLBConflictAbort
@ TLBConflictAbort
Definition: faults.hh:107
gem5::ArmISA::ArmFault::il
virtual bool il(ThreadContext *tc) const =0
gem5::ArmISA::ArmFault::AccessFlagLL
@ AccessFlagLL
Definition: faults.hh:102
gem5::ArmISA::SoftwareStepFault::ec
ExceptionClass ec(ThreadContext *tc) const override
Syndrome methods.
Definition: faults.cc:1761
gem5::ArmISA::UndefinedInstruction::iss
uint32_t iss() const override
Definition: faults.cc:836
gem5::ArmISA::EC_INVALID
@ EC_INVALID
Definition: types.hh:302
gem5::ArmISA::FastInterrupt::routeToMonitor
bool routeToMonitor(ThreadContext *tc) const override
Definition: faults.cc:1509
gem5::ArmISA::ArmFault::S1PTW
@ S1PTW
Definition: faults.hh:134
gem5::ArmISA::VirtualDataAbort::VirtualDataAbort
VirtualDataAbort(Addr _addr, TlbEntry::DomainType _domain, bool _write, uint8_t _source)
Definition: faults.hh:586
gem5::ArmISA::Reset::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:777
gem5::ArmISA::ArmFault::FaultVals::nextMode
const OperatingMode nextMode
Definition: faults.hh:178
gem5::ArmISA::ArmSev::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:1782
gem5::ArmISA::ArmFault::toMode
OperatingMode toMode
Definition: faults.hh:77
gem5::ArmISA::ArmFault::routeToHyp
virtual bool routeToHyp(ThreadContext *tc) const
Definition: faults.hh:244
gem5::ArmISA::ArmFault::SRT
@ SRT
Definition: faults.hh:138
gem5::ArmISA::HardwareBreakpoint::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:1655
gem5::ArmISA::DataAbort::sse
uint8_t sse
Definition: faults.hh:550
gem5::ArmISA::ArmFault::vectorCatch
bool vectorCatch(ThreadContext *tc, const StaticInstPtr &inst)
Definition: faults.cc:733
gem5::ArmISA::Interrupt::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1488
gem5::ArmISA::AbortFault::write
bool write
Definition: faults.hh:483
gem5::MipsISA::vaddr
vaddr
Definition: pra_constants.hh:278
gem5::ArmISA::PrefetchAbort::ec
ExceptionClass ec(ThreadContext *tc) const override
Syndrome methods.
Definition: faults.cc:1266
gem5::ArmISA::DataAbort::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1377
gem5::ArmISA::HypervisorCall::routeToMonitor
bool routeToMonitor(ThreadContext *tc) const override
Definition: faults.cc:933
gem5::ArmISA::DataAbort::ar
bool ar
Definition: faults.hh:556
gem5::ArmISA::IllegalInstSetStateFault::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1828
gem5::ArmISA::SystemError::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:1584
gem5::ArmISA::ArmFault::machInst
ExtMachInst machInst
Definition: faults.hh:67
gem5::ArmISA::SPAlignmentFault::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1573
gem5::ArmISA::ArmFault::fromMode
OperatingMode fromMode
Definition: faults.hh:76
gem5::ArmISA::SecureMonitorTrap::machInst
ExtMachInst machInst
Definition: faults.hh:422
gem5::ArmISA::SupervisorCall::ec
ExceptionClass ec(ThreadContext *tc) const override
Syndrome methods.
Definition: faults.cc:892
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::ArmISA::ArmFault::invoke32
void invoke32(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)
Definition: faults.cc:504
gem5::ArmISA::ArmFault::routeToMonitor
virtual bool routeToMonitor(ThreadContext *tc) const =0
gem5::ArmISA::IllegalInstSetStateFault::IllegalInstSetStateFault
IllegalInstSetStateFault()
Definition: faults.cc:1824
gem5::ArmISA::AbortFault::source
uint8_t source
Definition: faults.hh:485
gem5::ArmISA::ArmFault::isStage2
virtual bool isStage2() const
Definition: faults.hh:255
gem5::ArmISA::SecureMonitorTrap::SecureMonitorTrap
SecureMonitorTrap(ExtMachInst mach_inst, uint32_t _iss, ExceptionClass _overrideEc=EC_INVALID)
Definition: faults.hh:426
gem5::ArmISA::VirtualInterrupt
Definition: faults.hh:603
gem5::ArmISA::Interrupt
Definition: faults.hh:594
gem5::ArmISA::ArmFault::longDescFaultSources
static uint8_t longDescFaultSources[NumFaultSources]
Encodings of the fault sources when the long-desc.
Definition: faults.hh:128
gem5::ArmISA::AbortFault
Definition: faults.hh:467
gem5::ArmISA::ArmFault::SAS
@ SAS
Definition: faults.hh:136
gem5::ArmISA::DataAbort::HFarIndex
static const MiscRegIndex HFarIndex
Definition: faults.hh:547
gem5::ArmISA::SecureMonitorCall::vectorCatchFlag
uint32_t vectorCatchFlag() const override
Definition: faults.hh:392
gem5::ArmISA::SPAlignmentFault::il
bool il(ThreadContext *tc) const override
Syndrome methods.
Definition: faults.hh:650
gem5::ArmISA::ArmFault::UnknownTran
@ UnknownTran
Definition: faults.hh:154
gem5::ArmISA::OperatingMode
OperatingMode
Definition: types.hh:279
gem5::ArmISA::ArmFault::OVA
@ OVA
Definition: faults.hh:135
gem5::ArmISA::SoftwareStepFault::stepped
bool stepped
Definition: faults.hh:717
gem5::ArmISA::ArmFault::FaultVals::FaultVals
FaultVals(const FaultName &name_, FaultOffset offset_, uint16_t curr_elt_offset, uint16_t curr_elh_offset, uint16_t lower_el64_offset, uint16_t lower_el32_offset, OperatingMode next_mode, uint8_t arm_pc_offset, uint8_t thumb_pc_offset, uint8_t arm_pc_elr_offset, uint8_t thumb_pc_elr_offset, bool hyp_trappable, bool abort_disable, bool fiq_disable, ExceptionClass ec_)
Definition: faults.hh:196
gem5::ArmISA::AbortFault::s1ptw
bool s1ptw
Definition: faults.hh:488
gem5::ArmISA::VirtualFastInterrupt::VirtualFastInterrupt
VirtualFastInterrupt()
Definition: faults.cc:1550
gem5::ArmISA::SecureMonitorTrap::overrideEc
ExceptionClass overrideEc
Definition: faults.hh:423
gem5::ArmISA::ArmFaultVals::fiqDisable
bool fiqDisable(ThreadContext *tc) override
Definition: faults.hh:301
gem5::ArmISA::SoftwareStepFault::SoftwareStepFault
SoftwareStepFault(ExtMachInst mach_inst, bool is_ldx, bool stepped)
Definition: faults.cc:1742
gem5::ArmISA::VirtualDataAbort::FsrIndex
static const MiscRegIndex FsrIndex
Definition: faults.hh:582
gem5::ArmISA::ArmFaultVals::iss
uint32_t iss() const override
Definition: faults.hh:311
gem5::ArmISA::Interrupt::abortDisable
bool abortDisable(ThreadContext *tc) override
Definition: faults.cc:1496
gem5::ArmISA::VirtualDataAbort::FarIndex
static const MiscRegIndex FarIndex
Definition: faults.hh:583
gem5::ArmISA::ExceptionLevel
ExceptionLevel
Definition: types.hh:271
gem5::ArmISA::Watchpoint::ec
ExceptionClass ec(ThreadContext *tc) const override
Syndrome methods.
Definition: faults.cc:1733
gem5::ArmISA::AbortFault::tranMethod
ArmFault::TranMethod tranMethod
Definition: faults.hh:489
gem5::ArmISA::HypervisorCall::HypervisorCall
HypervisorCall(ExtMachInst mach_inst, uint32_t _imm)
Definition: faults.cc:926
gem5::ArmISA::ArmFault::fiqDisable
virtual bool fiqDisable(ThreadContext *tc)=0
gem5::ArmISA::SupervisorCall::SupervisorCall
SupervisorCall(ExtMachInst mach_inst, uint32_t _iss, ExceptionClass _overrideEc=EC_INVALID)
Definition: faults.hh:363
gem5::ArmISA::Watchpoint::write
bool write
Definition: faults.hh:697
gem5::ArmISA::IllegalInstSetStateFault
Illegal Instruction Set State fault (AArch64 only)
Definition: faults.hh:739
gem5::ArmISA::ArmFault::FaultVals::armPcElrOffset
const uint8_t armPcElrOffset
Definition: faults.hh:185

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