gem5  v21.1.0.2
faults.hh
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41 
42 #ifndef __ARM_FAULTS_HH__
43 #define __ARM_FAULTS_HH__
44 
45 #include "arch/arm/pagetable.hh"
46 #include "arch/arm/regs/misc.hh"
47 #include "arch/arm/types.hh"
48 #include "base/logging.hh"
49 #include "cpu/null_static_inst.hh"
50 #include "sim/faults.hh"
51 #include "sim/full_system.hh"
52 
53 namespace gem5
54 {
55 
56 // The design of the "name" and "vect" functions is in sim/faults.hh
57 
58 namespace ArmISA
59 {
60 typedef Addr FaultOffset;
61 
62 class ArmStaticInst;
63 
64 class ArmFault : public FaultBase
65 {
66  protected:
68  uint32_t issRaw;
69 
70  // Helper variables for ARMv8 exception handling
71  bool bStep; // True if the Arm Faul exception is a software Step exception
72  bool from64; // True if the exception is generated from the AArch64 state
73  bool to64; // True if the exception is taken in AArch64 state
74  ExceptionLevel fromEL; // Source exception level
75  ExceptionLevel toEL; // Target exception level
76  OperatingMode fromMode; // Source operating mode (aarch32)
77  OperatingMode toMode; // Next operating mode (aarch32)
78 
79  // This variable is true if the above fault specific informations
80  // have been updated. This is to prevent that a client is using their
81  // un-updated default constructed value.
83 
84  bool hypRouted; // True if the fault has been routed to Hypervisor
85  bool span; // True if the fault is setting the PSTATE.PAN bit
86 
87  virtual Addr getVector(ThreadContext *tc);
89 
90  public:
96  {
98  InstructionCacheMaintenance, // Short-desc. format only
107  TLBConflictAbort, // Requires LPAE
111  AddressSizeLL, // AArch64 only
112 
113  // Not real faults. These are faults to allow the translation function
114  // to inform the memory access function not to proceed for a prefetch
115  // that misses in the TLB or that targets an uncacheable address
118 
121  };
122 
131 
133  {
134  S1PTW, // DataAbort, PrefetchAbort: Stage 1 Page Table Walk,
135  OVA, // DataAbort, PrefetchAbort: stage 1 Virtual Address for stage 2 faults
136  SAS, // DataAbort: Syndrome Access Size
137  SSE, // DataAbort: Syndrome Sign Extend
138  SRT, // DataAbort: Syndrome Register Transfer
139  CM, // DataAbort: Cache Maintenance/Address Translation Op
140  OFA, // DataAbort: Override fault Address. This is needed when
141  // the abort is triggered by a CMO. The faulting address is
142  // then the address specified in the register argument of the
143  // instruction and not the cacheline address (See FAR doc)
144 
145  // AArch64 only
146  SF, // DataAbort: width of the accessed register is SixtyFour
147  AR // DataAbort: Acquire/Release semantics
148  };
149 
151  {
155  };
156 
158  {
159  NODEBUG = 0,
164  };
165 
166  struct FaultVals
167  {
169 
171 
172  // Offsets used for exceptions taken in AArch64 state
173  const uint16_t currELTOffset;
174  const uint16_t currELHOffset;
175  const uint16_t lowerEL64Offset;
176  const uint16_t lowerEL32Offset;
177 
179 
180  const uint8_t armPcOffset;
181  const uint8_t thumbPcOffset;
182  // The following two values are used in place of armPcOffset and
183  // thumbPcOffset when the exception return address is saved into ELR
184  // registers (exceptions taken in HYP mode or in AArch64 state)
185  const uint8_t armPcElrOffset;
186  const uint8_t thumbPcElrOffset;
187 
188  const bool hypTrappable;
189  const bool abortDisable;
190  const bool fiqDisable;
191 
192  // Exception class used to appropriately set the syndrome register
193  // (exceptions taken in HYP mode or in AArch64 state)
195 
197  FaultVals(const FaultName& name_, const FaultOffset& offset_,
198  const uint16_t& currELTOffset_, const uint16_t& currELHOffset_,
199  const uint16_t& lowerEL64Offset_,
200  const uint16_t& lowerEL32Offset_,
201  const OperatingMode& nextMode_, const uint8_t& armPcOffset_,
202  const uint8_t& thumbPcOffset_, const uint8_t& armPcElrOffset_,
203  const uint8_t& thumbPcElrOffset_, const bool& hypTrappable_,
204  const bool& abortDisable_, const bool& fiqDisable_,
205  const ExceptionClass& ec_)
206  : name(name_), offset(offset_), currELTOffset(currELTOffset_),
207  currELHOffset(currELHOffset_), lowerEL64Offset(lowerEL64Offset_),
208  lowerEL32Offset(lowerEL32Offset_), nextMode(nextMode_),
209  armPcOffset(armPcOffset_), thumbPcOffset(thumbPcOffset_),
210  armPcElrOffset(armPcElrOffset_), thumbPcElrOffset(thumbPcElrOffset_),
211  hypTrappable(hypTrappable_), abortDisable(abortDisable_),
212  fiqDisable(fiqDisable_), ec(ec_) {}
213  };
214 
215  ArmFault(ExtMachInst _machInst = 0, uint32_t _iss = 0) :
216  machInst(_machInst), issRaw(_iss), bStep(false), from64(false),
218  faultUpdated(false), hypRouted(false), span(false) {}
219 
220  // Returns the actual syndrome register to use based on the target
221  // exception level
223  // Returns the actual fault address register to use based on the target
224  // exception level
226 
227  void invoke(ThreadContext *tc, const StaticInstPtr &inst =
228  nullStaticInstPtr) override;
229  void invoke64(ThreadContext *tc, const StaticInstPtr &inst =
231  void update(ThreadContext *tc);
232  bool isResetSPSR(){ return bStep; }
233 
234  bool vectorCatch(ThreadContext *tc, const StaticInstPtr &inst);
235 
237  virtual void annotate(AnnotationIDs id, uint64_t val) {}
238  virtual FaultStat& countStat() = 0;
239  virtual FaultOffset offset(ThreadContext *tc) = 0;
240  virtual FaultOffset offset64(ThreadContext *tc) = 0;
241  virtual OperatingMode nextMode() = 0;
242  virtual bool routeToMonitor(ThreadContext *tc) const = 0;
243  virtual bool routeToHyp(ThreadContext *tc) const { return false; }
244  virtual uint8_t armPcOffset(bool isHyp) = 0;
245  virtual uint8_t thumbPcOffset(bool isHyp) = 0;
246  virtual uint8_t armPcElrOffset() = 0;
247  virtual uint8_t thumbPcElrOffset() = 0;
248  virtual bool abortDisable(ThreadContext *tc) = 0;
249  virtual bool fiqDisable(ThreadContext *tc) = 0;
250  virtual ExceptionClass ec(ThreadContext *tc) const = 0;
251  virtual uint32_t vectorCatchFlag() const { return 0x0; }
252  virtual uint32_t iss() const = 0;
253  virtual bool isStage2() const { return false; }
254  virtual FSR getFsr(ThreadContext *tc) const { return 0; }
255  virtual void setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg);
256  virtual bool getFaultVAddr(Addr &va) const { return false; }
257  OperatingMode getToMode() const { return toMode; }
258 };
259 
260 template<typename T>
261 class ArmFaultVals : public ArmFault
262 {
263  protected:
264  static FaultVals vals;
265 
266  public:
267  ArmFaultVals<T>(ExtMachInst _machInst = 0, uint32_t _iss = 0) :
268  ArmFault(_machInst, _iss) {}
269  FaultName name() const override { return vals.name; }
270  FaultStat & countStat() override { return vals.count; }
271  FaultOffset offset(ThreadContext *tc) override;
272 
273  FaultOffset offset64(ThreadContext *tc) override;
274 
275  OperatingMode nextMode() override { return vals.nextMode; }
276  virtual bool routeToMonitor(ThreadContext *tc) const override {
277  return false;
278  }
279  uint8_t armPcOffset(bool isHyp) override {
280  return isHyp ? vals.armPcElrOffset
281  : vals.armPcOffset;
282  }
283  uint8_t thumbPcOffset(bool isHyp) override {
284  return isHyp ? vals.thumbPcElrOffset
286  }
287  uint8_t armPcElrOffset() override { return vals.armPcElrOffset; }
288  uint8_t thumbPcElrOffset() override { return vals.thumbPcElrOffset; }
289  bool abortDisable(ThreadContext* tc) override { return vals.abortDisable; }
290  bool fiqDisable(ThreadContext* tc) override { return vals.fiqDisable; }
291  ExceptionClass ec(ThreadContext *tc) const override { return vals.ec; }
292  uint32_t iss() const override { return issRaw; }
293 };
294 
295 class Reset : public ArmFaultVals<Reset>
296 {
297  protected:
298  Addr getVector(ThreadContext *tc) override;
299 
300  public:
301  void invoke(ThreadContext *tc, const StaticInstPtr &inst =
302  nullStaticInstPtr) override;
303 };
304 
305 class UndefinedInstruction : public ArmFaultVals<UndefinedInstruction>
306 {
307  protected:
308  bool unknown;
309  bool disabled;
311  const char *mnemonic;
312 
313  public:
315  bool _unknown,
316  const char *_mnemonic = NULL,
317  bool _disabled = false) :
319  unknown(_unknown), disabled(_disabled),
320  overrideEc(EC_INVALID), mnemonic(_mnemonic)
321  {}
322  UndefinedInstruction(ExtMachInst _machInst, uint32_t _iss,
323  ExceptionClass _overrideEc, const char *_mnemonic = NULL) :
324  ArmFaultVals<UndefinedInstruction>(_machInst, _iss),
325  unknown(false), disabled(true), overrideEc(_overrideEc),
326  mnemonic(_mnemonic)
327  {}
328 
329  void invoke(ThreadContext *tc, const StaticInstPtr &inst =
330  nullStaticInstPtr) override;
331  bool routeToHyp(ThreadContext *tc) const override;
332  ExceptionClass ec(ThreadContext *tc) const override;
333  uint32_t iss() const override;
334  uint32_t vectorCatchFlag() const override { return 0x02000002; }
335 };
336 
337 class SupervisorCall : public ArmFaultVals<SupervisorCall>
338 {
339  protected:
341  public:
342  SupervisorCall(ExtMachInst _machInst, uint32_t _iss,
343  ExceptionClass _overrideEc = EC_INVALID) :
344  ArmFaultVals<SupervisorCall>(_machInst, _iss),
345  overrideEc(_overrideEc)
346  {
347  bStep = true;
348  }
349 
350  void invoke(ThreadContext *tc, const StaticInstPtr &inst =
351  nullStaticInstPtr) override;
352  bool routeToHyp(ThreadContext *tc) const override;
353  ExceptionClass ec(ThreadContext *tc) const override;
354  uint32_t iss() const override;
355  uint32_t vectorCatchFlag() const override { return 0x04000404; }
356 };
357 
358 class SecureMonitorCall : public ArmFaultVals<SecureMonitorCall>
359 {
360  public:
362  ArmFaultVals<SecureMonitorCall>(_machInst)
363  {
364  bStep = true;
365  }
366 
367  void invoke(ThreadContext *tc, const StaticInstPtr &inst =
368  nullStaticInstPtr) override;
369  ExceptionClass ec(ThreadContext *tc) const override;
370  uint32_t iss() const override;
371  uint32_t vectorCatchFlag() const override { return 0x00000400; }
372 };
373 
374 class SupervisorTrap : public ArmFaultVals<SupervisorTrap>
375 {
376  protected:
379 
380  public:
381  SupervisorTrap(ExtMachInst _machInst, uint32_t _iss,
382  ExceptionClass _overrideEc = EC_INVALID) :
383  ArmFaultVals<SupervisorTrap>(_machInst, _iss),
384  overrideEc(_overrideEc)
385  {}
386 
387  bool routeToHyp(ThreadContext *tc) const override;
388  uint32_t iss() const override;
389  ExceptionClass ec(ThreadContext *tc) const override;
390 };
391 
392 class SecureMonitorTrap : public ArmFaultVals<SecureMonitorTrap>
393 {
394  protected:
397 
398  public:
399  SecureMonitorTrap(ExtMachInst _machInst, uint32_t _iss,
400  ExceptionClass _overrideEc = EC_INVALID) :
401  ArmFaultVals<SecureMonitorTrap>(_machInst, _iss),
402  overrideEc(_overrideEc)
403  {}
404 
405  ExceptionClass ec(ThreadContext *tc) const override;
406 };
407 
408 class HypervisorCall : public ArmFaultVals<HypervisorCall>
409 {
410  public:
411  HypervisorCall(ExtMachInst _machInst, uint32_t _imm);
412 
413  bool routeToHyp(ThreadContext *tc) const override;
414  bool routeToMonitor(ThreadContext *tc) const override;
415  ExceptionClass ec(ThreadContext *tc) const override;
416  uint32_t vectorCatchFlag() const override { return 0xFFFFFFFF; }
417 };
418 
419 class HypervisorTrap : public ArmFaultVals<HypervisorTrap>
420 {
421  protected:
424 
425  public:
426  HypervisorTrap(ExtMachInst _machInst, uint32_t _iss,
427  ExceptionClass _overrideEc = EC_INVALID) :
428  ArmFaultVals<HypervisorTrap>(_machInst, _iss),
429  overrideEc(_overrideEc)
430  {}
431 
432  ExceptionClass ec(ThreadContext *tc) const override;
433 };
434 
435 template <class T>
436 class AbortFault : public ArmFaultVals<T>
437 {
438  protected:
452  bool write;
454  uint8_t source;
455  uint8_t srcEncoded;
456  bool stage2;
457  bool s1ptw;
460 
461  public:
462  AbortFault(Addr _faultAddr, bool _write, TlbEntry::DomainType _domain,
463  uint8_t _source, bool _stage2,
466  faultAddr(_faultAddr), OVAddr(0), write(_write),
467  domain(_domain), source(_source), srcEncoded(0),
468  stage2(_stage2), s1ptw(false), tranMethod(_tranMethod),
469  debugType(_debug)
470  {}
471 
472  bool getFaultVAddr(Addr &va) const override;
473 
474  void invoke(ThreadContext *tc, const StaticInstPtr &inst =
475  nullStaticInstPtr) override;
476 
477  FSR getFsr(ThreadContext *tc) const override;
478  uint8_t getFaultStatusCode(ThreadContext *tc) const;
479  bool abortDisable(ThreadContext *tc) override;
480  uint32_t iss() const override;
481  bool isStage2() const override { return stage2; }
482  void annotate(ArmFault::AnnotationIDs id, uint64_t val) override;
483  void setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg) override;
484  bool isMMUFault() const;
485 };
486 
487 class PrefetchAbort : public AbortFault<PrefetchAbort>
488 {
489  public:
493 
494  PrefetchAbort(Addr _addr, uint8_t _source, bool _stage2 = false,
497  AbortFault<PrefetchAbort>(_addr, false, TlbEntry::DomainType::NoAccess,
498  _source, _stage2, _tranMethod, _debug)
499  {}
500 
501  ExceptionClass ec(ThreadContext *tc) const override;
502  // @todo: external aborts should be routed if SCR.EA == 1
503  bool routeToMonitor(ThreadContext *tc) const override;
504  bool routeToHyp(ThreadContext *tc) const override;
505  uint32_t vectorCatchFlag() const override { return 0x08000808; }
506 };
507 
508 class DataAbort : public AbortFault<DataAbort>
509 {
510  public:
514  bool isv;
515  uint8_t sas;
516  uint8_t sse;
517  uint8_t srt;
518  uint8_t cm;
519 
520  // AArch64 only
521  bool sf;
522  bool ar;
523 
524  DataAbort(Addr _addr, TlbEntry::DomainType _domain, bool _write, uint8_t _source,
525  bool _stage2=false,
528  AbortFault<DataAbort>(_addr, _write, _domain, _source, _stage2,
529  _tranMethod, _debug_type),
530  isv(false), sas (0), sse(0), srt(0), cm(0), sf(false), ar(false)
531  {}
532 
533  ExceptionClass ec(ThreadContext *tc) const override;
534  // @todo: external aborts should be routed if SCR.EA == 1
535  bool routeToMonitor(ThreadContext *tc) const override;
536  bool routeToHyp(ThreadContext *tc) const override;
537  uint32_t iss() const override;
538  void annotate(AnnotationIDs id, uint64_t val) override;
539  uint32_t vectorCatchFlag() const override { return 0x10001010; }
540 };
541 
542 class VirtualDataAbort : public AbortFault<VirtualDataAbort>
543 {
544  public:
548 
549  VirtualDataAbort(Addr _addr, TlbEntry::DomainType _domain, bool _write,
550  uint8_t _source) :
551  AbortFault<VirtualDataAbort>(_addr, _write, _domain, _source, false)
552  {}
553 
554  void invoke(ThreadContext *tc, const StaticInstPtr &inst) override;
555 };
556 
557 class Interrupt : public ArmFaultVals<Interrupt>
558 {
559  public:
560  bool routeToMonitor(ThreadContext *tc) const override;
561  bool routeToHyp(ThreadContext *tc) const override;
562  bool abortDisable(ThreadContext *tc) override;
563  uint32_t vectorCatchFlag() const override { return 0x40004040; }
564 };
565 
566 class VirtualInterrupt : public ArmFaultVals<VirtualInterrupt>
567 {
568  public:
570 };
571 
572 class FastInterrupt : public ArmFaultVals<FastInterrupt>
573 {
574  public:
575  bool routeToMonitor(ThreadContext *tc) const override;
576  bool routeToHyp(ThreadContext *tc) const override;
577  bool abortDisable(ThreadContext *tc) override;
578  bool fiqDisable(ThreadContext *tc) override;
579  uint32_t vectorCatchFlag() const override { return 0x80008080; }
580 };
581 
582 class VirtualFastInterrupt : public ArmFaultVals<VirtualFastInterrupt>
583 {
584  public:
586 };
587 
589 class PCAlignmentFault : public ArmFaultVals<PCAlignmentFault>
590 {
591  protected:
594  public:
595  PCAlignmentFault(Addr _faultPC) : faultPC(_faultPC)
596  {}
597  void invoke(ThreadContext *tc, const StaticInstPtr &inst =
598  nullStaticInstPtr) override;
599  bool routeToHyp(ThreadContext *tc) const override;
600 };
601 
603 class SPAlignmentFault : public ArmFaultVals<SPAlignmentFault>
604 {
605  public:
607  bool routeToHyp(ThreadContext *tc) const override;
608 };
609 
611 class SystemError : public ArmFaultVals<SystemError>
612 {
613  public:
614  SystemError();
615  void invoke(ThreadContext *tc, const StaticInstPtr &inst =
616  nullStaticInstPtr) override;
617  bool routeToMonitor(ThreadContext *tc) const override;
618  bool routeToHyp(ThreadContext *tc) const override;
619 };
620 
622 class SoftwareBreakpoint : public ArmFaultVals<SoftwareBreakpoint>
623 {
624  public:
625  SoftwareBreakpoint(ExtMachInst _mach_inst, uint32_t _iss);
626 
627  bool routeToHyp(ThreadContext *tc) const override;
628  ExceptionClass ec(ThreadContext *tc) const override;
629 };
630 
631 class HardwareBreakpoint : public ArmFaultVals<HardwareBreakpoint>
632 {
633  private:
635  public:
636  void invoke(ThreadContext *tc, const StaticInstPtr &inst =
637  nullStaticInstPtr) override;
638  HardwareBreakpoint(Addr _vaddr, uint32_t _iss);
639  bool routeToHyp(ThreadContext *tc) const override;
640  ExceptionClass ec(ThreadContext *tc) const override;
641 };
642 
643 class Watchpoint : public ArmFaultVals<Watchpoint>
644 {
645  private:
647  bool write;
648  bool cm;
649 
650  public:
651  Watchpoint(ExtMachInst _mach_inst, Addr _vaddr, bool _write, bool _cm);
652  void invoke(ThreadContext *tc, const StaticInstPtr &inst =
653  nullStaticInstPtr) override;
654  bool routeToHyp(ThreadContext *tc) const override;
655  uint32_t iss() const override;
656  ExceptionClass ec(ThreadContext *tc) const override;
657  void annotate(AnnotationIDs id, uint64_t val) override;
658 };
659 
660 class SoftwareStepFault : public ArmFaultVals<SoftwareStepFault>
661 {
662  private:
663  bool isldx;
664  bool stepped;
665 
666  public:
667  SoftwareStepFault(ExtMachInst _mach_inst, bool is_ldx, bool stepped);
668  bool routeToHyp(ThreadContext *tc) const override;
669  uint32_t iss() const override;
670  ExceptionClass ec(ThreadContext *tc) const override;
671 };
672 
673 // A fault that flushes the pipe, excluding the faulting instructions
674 class ArmSev : public ArmFaultVals<ArmSev>
675 {
676  public:
677  ArmSev () {}
678  void invoke(ThreadContext *tc, const StaticInstPtr &inst =
679  nullStaticInstPtr) override;
680 };
681 
683 class IllegalInstSetStateFault : public ArmFaultVals<IllegalInstSetStateFault>
684 {
685  public:
687 
688  bool routeToHyp(ThreadContext *tc) const override;
689 };
690 
691 /*
692  * Explicitly declare template static member variables to avoid warnings
693  * in some clang versions
694  */
719 
730 bool getFaultVAddr(Fault fault, Addr &va);
731 
732 } // namespace ArmISA
733 } // namespace gem5
734 
735 #endif // __ARM_FAULTS_HH__
gem5::ArmISA::ArmFault::FaultVals::thumbPcElrOffset
const uint8_t thumbPcElrOffset
Definition: faults.hh:186
gem5::statistics::Scalar
This is a simple scalar statistic, like a counter.
Definition: statistics.hh:1927
gem5::ArmISA::MISCREG_DFAR
@ MISCREG_DFAR
Definition: misc.hh:283
gem5::ArmISA::ArmFault::NODEBUG
@ NODEBUG
Definition: faults.hh:159
gem5::ArmISA::ArmFault::fromEL
ExceptionLevel fromEL
Definition: faults.hh:74
gem5::ArmISA::AbortFault::annotate
void annotate(ArmFault::AnnotationIDs id, uint64_t val) override
Definition: faults.cc:1219
gem5::ArmISA::AbortFault::setSyndrome
void setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg) override
Definition: faults.cc:1146
gem5::ArmISA::ArmFault::FaultVals::ec
const ExceptionClass ec
Definition: faults.hh:194
gem5::ArmISA::ArmFault::NumFaultSources
@ NumFaultSources
Definition: faults.hh:119
gem5::ArmISA::SupervisorTrap::ec
ExceptionClass ec(ThreadContext *tc) const override
Definition: faults.cc:1048
gem5::ArmISA::UndefinedInstruction::mnemonic
const char * mnemonic
Definition: faults.hh:311
gem5::ArmISA::SPAlignmentFault::SPAlignmentFault
SPAlignmentFault()
Definition: faults.cc:1558
gem5::ArmISA::DataAbort::routeToMonitor
bool routeToMonitor(ThreadContext *tc) const override
Definition: faults.cc:1355
gem5::ArmISA::UndefinedInstruction::ec
ExceptionClass ec(ThreadContext *tc) const override
Definition: faults.cc:912
gem5::ArmISA::ArmFaultVals::thumbPcElrOffset
uint8_t thumbPcElrOffset() override
Definition: faults.hh:288
gem5::ArmISA::SoftwareBreakpoint::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1605
gem5::ArmISA::ArmFault::FaultVals::lowerEL32Offset
const uint16_t lowerEL32Offset
Definition: faults.hh:176
gem5::ArmISA::ArmFault::AddressSizeLL
@ AddressSizeLL
Definition: faults.hh:111
gem5::ArmISA::DataAbort::sf
bool sf
Definition: faults.hh:521
gem5::ArmISA::ArmFaultVals::armPcOffset
uint8_t armPcOffset(bool isHyp) override
Definition: faults.hh:279
gem5::ArmISA::PrefetchAbort::FsrIndex
static const MiscRegIndex FsrIndex
Definition: faults.hh:490
gem5::ArmISA::ArmFault::bStep
bool bStep
Definition: faults.hh:71
gem5::ArmISA::Watchpoint::Watchpoint
Watchpoint(ExtMachInst _mach_inst, Addr _vaddr, bool _write, bool _cm)
Definition: faults.cc:1670
gem5::ArmISA::AbortFault::AbortFault
AbortFault(Addr _faultAddr, bool _write, TlbEntry::DomainType _domain, uint8_t _source, bool _stage2, ArmFault::TranMethod _tranMethod=ArmFault::UnknownTran, ArmFault::DebugType _debug=ArmFault::NODEBUG)
Definition: faults.hh:462
gem5::ArmISA::ArmFault::FaultSourceInvalid
@ FaultSourceInvalid
Definition: faults.hh:120
gem5::ArmISA::PCAlignmentFault::faultPC
Addr faultPC
The unaligned value of the PC.
Definition: faults.hh:593
gem5::ArmISA::ArmFault::abortDisable
virtual bool abortDisable(ThreadContext *tc)=0
gem5::ArmISA::VirtualDataAbort
Definition: faults.hh:542
gem5::ArmISA::ArmStaticInst
Definition: static_inst.hh:63
gem5::ArmISA::ArmFault::BRKPOINT
@ BRKPOINT
Definition: faults.hh:160
gem5::ArmISA::HypervisorCall
Definition: faults.hh:408
gem5::ArmISA::PrefetchAbort::vectorCatchFlag
uint32_t vectorCatchFlag() const override
Definition: faults.hh:505
gem5::ArmISA::ArmFault::issRaw
uint32_t issRaw
Definition: faults.hh:68
gem5::ArmISA::ArmFault::AR
@ AR
Definition: faults.hh:147
gem5::ArmISA::SystemError::SystemError
SystemError()
Definition: faults.cc:1569
gem5::ArmISA::HypervisorTrap::overrideEc
ExceptionClass overrideEc
Definition: faults.hh:423
gem5::ArmISA::ArmFaultVals::vals
static FaultVals vals
Definition: faults.hh:264
gem5::ArmISA::SecureMonitorCall::ec
ExceptionClass ec(ThreadContext *tc) const override
Definition: faults.cc:1025
gem5::ArmISA::ArmFault::from64
bool from64
Definition: faults.hh:72
gem5::ArmISA::HypervisorCall::vectorCatchFlag
uint32_t vectorCatchFlag() const override
Definition: faults.hh:416
gem5::ArmISA::MODE_UNDEFINED
@ MODE_UNDEFINED
Definition: types.hh:288
gem5::ArmISA::HardwareBreakpoint::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1625
gem5::ArmISA::ArmFault::SynchExtAbtOnTranslTableWalkLL
@ SynchExtAbtOnTranslTableWalkLL
Definition: faults.hh:99
gem5::ArmISA::ArmFault::PrefetchUncacheable
@ PrefetchUncacheable
Definition: faults.hh:117
gem5::ArmISA::ArmFault::VECTORCATCH
@ VECTORCATCH
Definition: faults.hh:161
gem5::ArmISA::Interrupt::vectorCatchFlag
uint32_t vectorCatchFlag() const override
Definition: faults.hh:563
gem5::ArmISA::SupervisorCall::vectorCatchFlag
uint32_t vectorCatchFlag() const override
Definition: faults.hh:355
gem5::ArmISA::SupervisorCall
Definition: faults.hh:337
gem5::ArmISA::HypervisorTrap
Definition: faults.hh:419
gem5::ArmISA::PrefetchAbort::HFarIndex
static const MiscRegIndex HFarIndex
Definition: faults.hh:492
gem5::ArmISA::HypervisorTrap::ec
ExceptionClass ec(ThreadContext *tc) const override
Definition: faults.cc:948
gem5::ArmISA::UndefinedInstruction
Definition: faults.hh:305
gem5::ArmISA::UndefinedInstruction::overrideEc
ExceptionClass overrideEc
Definition: faults.hh:310
pagetable.hh
gem5::ArmISA::UndefinedInstruction::disabled
bool disabled
Definition: faults.hh:309
gem5::ArmISA::ArmFault::SynchronousExternalAbort
@ SynchronousExternalAbort
Definition: faults.hh:106
gem5::ArmISA::ArmFaultVals::thumbPcOffset
uint8_t thumbPcOffset(bool isHyp) override
Definition: faults.hh:283
gem5::ArmISA::ArmFault::LpaeTran
@ LpaeTran
Definition: faults.hh:152
gem5::ArmISA::ArmFaultVals::abortDisable
bool abortDisable(ThreadContext *tc) override
Definition: faults.hh:289
gem5::ArmISA::ArmFault::faultUpdated
bool faultUpdated
Definition: faults.hh:82
gem5::ArmISA::ArmFault::PrefetchTLBMiss
@ PrefetchTLBMiss
Definition: faults.hh:116
gem5::ArmISA::ArmFault::SSE
@ SSE
Definition: faults.hh:137
gem5::ArmISA::UndefinedInstruction::unknown
bool unknown
Definition: faults.hh:308
gem5::ArmISA::DataAbort::iss
uint32_t iss() const override
Definition: faults.cc:1391
gem5::ArmISA::FastInterrupt::vectorCatchFlag
uint32_t vectorCatchFlag() const override
Definition: faults.hh:579
gem5::ArmISA::PCAlignmentFault::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1552
gem5::ArmISA::HypervisorCall::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:936
gem5::ArmISA::UndefinedInstruction::UndefinedInstruction
UndefinedInstruction(ExtMachInst _machInst, bool _unknown, const char *_mnemonic=NULL, bool _disabled=false)
Definition: faults.hh:314
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::ArmISA::ArmFault::armPcElrOffset
virtual uint8_t armPcElrOffset()=0
gem5::ArmISA::Watchpoint::vAddr
Addr vAddr
Definition: faults.hh:646
gem5::ArmISA::AbortFault::getFaultStatusCode
uint8_t getFaultStatusCode(ThreadContext *tc) const
Definition: faults.cc:1157
gem5::ArmISA::PrefetchAbort::routeToMonitor
bool routeToMonitor(ThreadContext *tc) const override
Definition: faults.cc:1299
gem5::ArmISA::ArmSev
Definition: faults.hh:674
gem5::ArmISA::PCAlignmentFault
PC alignment fault (AArch64 only)
Definition: faults.hh:589
gem5::ArmISA::MISCREG_HIFAR
@ MISCREG_HIFAR
Definition: misc.hh:290
gem5::ArmISA::ArmFault::DomainLL
@ DomainLL
Definition: faults.hh:103
gem5::ArmISA::Interrupt::routeToMonitor
bool routeToMonitor(ThreadContext *tc) const override
Definition: faults.cc:1465
gem5::ArmISA::ArmFault::SynchPtyErrOnMemoryAccess
@ SynchPtyErrOnMemoryAccess
Definition: faults.hh:108
gem5::ArmISA::ArmFault::offset64
virtual FaultOffset offset64(ThreadContext *tc)=0
gem5::ArmISA::ArmFault::DebugEvent
@ DebugEvent
Definition: faults.hh:105
gem5::ArmISA::Watchpoint::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1700
gem5::ArmISA::AbortFault::debugType
ArmFault::DebugType debugType
Definition: faults.hh:459
gem5::ArmISA::ArmFault::FaultVals
Definition: faults.hh:166
gem5::ArmISA::Watchpoint
Definition: faults.hh:643
gem5::ArmISA::ArmFault::FaultVals::hypTrappable
const bool hypTrappable
Definition: faults.hh:188
gem5::ArmISA::PrefetchAbort::FarIndex
static const MiscRegIndex FarIndex
Definition: faults.hh:491
gem5::ArmISA::ArmFault::getToMode
OperatingMode getToMode() const
Definition: faults.hh:257
gem5::ArmISA::SupervisorTrap::iss
uint32_t iss() const override
Definition: faults.cc:1038
gem5::ArmISA::UndefinedInstruction::vectorCatchFlag
uint32_t vectorCatchFlag() const override
Definition: faults.hh:334
gem5::ArmISA::HardwareBreakpoint::vAddr
Addr vAddr
Definition: faults.hh:634
gem5::ArmISA::VirtualDataAbort::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst) override
Definition: faults.cc:1456
gem5::ArmISA::SoftwareStepFault::isldx
bool isldx
Definition: faults.hh:663
gem5::ArmISA::UndefinedInstruction::UndefinedInstruction
UndefinedInstruction(ExtMachInst _machInst, uint32_t _iss, ExceptionClass _overrideEc, const char *_mnemonic=NULL)
Definition: faults.hh:322
gem5::ArmISA::ArmFault::setSyndrome
virtual void setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg)
Definition: faults.cc:398
gem5::ArmISA::ArmFault::to64
bool to64
Definition: faults.hh:73
gem5::ArmISA::getFaultVAddr
bool getFaultVAddr(Fault fault, Addr &va)
Returns true if the fault passed as a first argument was triggered by a memory access,...
Definition: faults.cc:1831
faults.hh
types.hh
gem5::ArmISA::ArmFault::FaultVals::currELTOffset
const uint16_t currELTOffset
Definition: faults.hh:173
gem5::ArmISA::ArmFault::FaultVals::thumbPcOffset
const uint8_t thumbPcOffset
Definition: faults.hh:181
gem5::ArmISA::SoftwareBreakpoint::ec
ExceptionClass ec(ThreadContext *tc) const override
Definition: faults.cc:1615
gem5::ArmISA::SystemError::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1589
gem5::ArmISA::ArmFault::getVector64
Addr getVector64(ThreadContext *tc)
Definition: faults.cc:343
gem5::ArmISA::SystemError::routeToMonitor
bool routeToMonitor(ThreadContext *tc) const override
Definition: faults.cc:1580
gem5::ArmISA::TlbEntry
Definition: pagetable.hh:86
gem5::ArmISA::ArmFault::PermissionLL
@ PermissionLL
Definition: faults.hh:104
gem5::ArmISA::TlbEntry::DomainType
DomainType
Definition: pagetable.hh:96
gem5::ArmISA::SecureMonitorTrap
Definition: faults.hh:392
gem5::ArmISA::ArmSev::ArmSev
ArmSev()
Definition: faults.hh:677
gem5::ArmISA::ArmFault::AsynchronousExternalAbort
@ AsynchronousExternalAbort
Definition: faults.hh:109
gem5::ArmISA::PCAlignmentFault::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:1543
gem5::RefCountingPtr< StaticInst >
gem5::ArmISA::ArmFault::VmsaTran
@ VmsaTran
Definition: faults.hh:153
gem5::ArmISA::DataAbort
Definition: faults.hh:508
gem5::ArmISA::AbortFault::getFsr
FSR getFsr(ThreadContext *tc) const override
Definition: faults.cc:1183
gem5::ArmISA::SupervisorCall::iss
uint32_t iss() const override
Definition: faults.cc:896
gem5::ArmISA::MISCREG_IFSR
@ MISCREG_IFSR
Definition: misc.hh:271
gem5::ArmISA::ArmFaultVals::nextMode
OperatingMode nextMode() override
Definition: faults.hh:275
gem5::ArmISA::ArmFault::OFA
@ OFA
Definition: faults.hh:140
gem5::ArmISA::ArmFault::iss
virtual uint32_t iss() const =0
gem5::ArmISA::FastInterrupt::abortDisable
bool abortDisable(ThreadContext *tc) override
Definition: faults.cc:1518
gem5::ArmISA::Watchpoint::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:1691
gem5::ArmISA::ArmFault::countStat
virtual FaultStat & countStat()=0
gem5::ArmISA::ArmFault::instrAnnotate
ArmStaticInst * instrAnnotate(const StaticInstPtr &inst)
Definition: faults.cc:744
gem5::ArmISA::DataAbort::FarIndex
static const MiscRegIndex FarIndex
Definition: faults.hh:512
gem5::ArmISA::HypervisorTrap::HypervisorTrap
HypervisorTrap(ExtMachInst _machInst, uint32_t _iss, ExceptionClass _overrideEc=EC_INVALID)
Definition: faults.hh:426
gem5::nullStaticInstPtr
const StaticInstPtr nullStaticInstPtr
Statically allocated null StaticInstPtr.
Definition: null_static_inst.cc:36
gem5::ArmISA::ArmFault::thumbPcElrOffset
virtual uint8_t thumbPcElrOffset()=0
gem5::ArmISA::ArmFaultVals
Definition: faults.hh:261
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::ArmISA::ArmFault::offset
virtual FaultOffset offset(ThreadContext *tc)=0
gem5::ArmISA::Reset
Definition: faults.hh:295
gem5::ArmISA::SoftwareStepFault
Definition: faults.hh:660
gem5::ArmISA::HardwareBreakpoint
Definition: faults.hh:631
gem5::ArmISA::ArmFault::thumbPcOffset
virtual uint8_t thumbPcOffset(bool isHyp)=0
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::ArmISA::ArmFault::FaultSource
FaultSource
Generic fault source enums used to index into {short/long/aarch64}DescFaultSources[] to get the actua...
Definition: faults.hh:95
gem5::ArmISA::ArmFault::getSyndromeReg64
MiscRegIndex getSyndromeReg64() const
Definition: faults.cc:366
gem5::ArmISA::SecureMonitorCall::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:1016
gem5::ArmISA::AbortFault::domain
TlbEntry::DomainType domain
Definition: faults.hh:453
gem5::ArmISA::DataAbort::DataAbort
DataAbort(Addr _addr, TlbEntry::DomainType _domain, bool _write, uint8_t _source, bool _stage2=false, ArmFault::TranMethod _tranMethod=ArmFault::UnknownTran, ArmFault::DebugType _debug_type=ArmFault::NODEBUG)
Definition: faults.hh:524
gem5::ArmISA::ArmFaultVals::armPcElrOffset
uint8_t armPcElrOffset() override
Definition: faults.hh:287
gem5::ArmISA::ArmFault::toEL
ExceptionLevel toEL
Definition: faults.hh:75
gem5::ArmISA::SecureMonitorCall
Definition: faults.hh:358
gem5::ArmISA::DataAbort::ec
ExceptionClass ec(ThreadContext *tc) const override
Definition: faults.cc:1326
gem5::ArmISA::DataAbort::vectorCatchFlag
uint32_t vectorCatchFlag() const override
Definition: faults.hh:539
gem5::ArmISA::SecureMonitorTrap::ec
ExceptionClass ec(ThreadContext *tc) const override
Definition: faults.cc:1057
gem5::ArmISA::FastInterrupt::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1510
gem5::ArmISA::ArmFault::hypRouted
bool hypRouted
Definition: faults.hh:84
gem5::ArmISA::SupervisorTrap::machInst
ExtMachInst machInst
Definition: faults.hh:377
gem5::ArmISA::ArmFault::vectorCatchFlag
virtual uint32_t vectorCatchFlag() const
Definition: faults.hh:251
gem5::ArmISA::SupervisorCall::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:862
gem5::ArmISA::ArmFault::SynchPtyErrOnTranslTableWalkLL
@ SynchPtyErrOnTranslTableWalkLL
Definition: faults.hh:100
gem5::ArmISA::ArmFault::shortDescFaultSources
static uint8_t shortDescFaultSources[NumFaultSources]
Encodings of the fault sources when the short-desc.
Definition: faults.hh:125
gem5::ArmISA::DataAbort::sas
uint8_t sas
Definition: faults.hh:515
gem5::ArmISA::ArmFault::FaultVals::name
const FaultName name
Definition: faults.hh:168
gem5::ArmISA::SupervisorTrap
Definition: faults.hh:374
gem5::ArmISA::ArmFault::update
void update(ThreadContext *tc)
Definition: faults.cc:439
gem5::ArmISA::ArmFault::FaultVals::FaultVals
FaultVals(const FaultName &name_, const FaultOffset &offset_, const uint16_t &currELTOffset_, const uint16_t &currELHOffset_, const uint16_t &lowerEL64Offset_, const uint16_t &lowerEL32Offset_, const OperatingMode &nextMode_, const uint8_t &armPcOffset_, const uint8_t &thumbPcOffset_, const uint8_t &armPcElrOffset_, const uint8_t &thumbPcElrOffset_, const bool &hypTrappable_, const bool &abortDisable_, const bool &fiqDisable_, const ExceptionClass &ec_)
Definition: faults.hh:197
gem5::ArmISA::VirtualFastInterrupt
Definition: faults.hh:582
gem5::ArmISA::HypervisorTrap::machInst
ExtMachInst machInst
Definition: faults.hh:422
gem5::ArmISA::ArmFaultVals::offset64
FaultOffset offset64(ThreadContext *tc) override
Definition: faults.cc:975
gem5::ArmISA::ArmFault::getFaultVAddr
virtual bool getFaultVAddr(Addr &va) const
Definition: faults.hh:256
gem5::ArmISA::ArmFaultVals::countStat
FaultStat & countStat() override
Definition: faults.hh:270
gem5::ArmISA::Watchpoint::cm
bool cm
Definition: faults.hh:648
gem5::ArmISA::SecureMonitorCall::iss
uint32_t iss() const override
Definition: faults.cc:904
gem5::ArmISA::UndefinedInstruction::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:825
gem5::ArmISA::AbortFault::iss
uint32_t iss() const override
Definition: faults.cc:1238
gem5::ArmISA::AbortFault::abortDisable
bool abortDisable(ThreadContext *tc) override
Definition: faults.cc:1208
gem5::ArmISA::UndefinedInstruction::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:802
gem5::ArmISA::ArmFault::FaultVals::offset
const FaultOffset offset
Definition: faults.hh:170
gem5::ArmISA::SupervisorTrap::overrideEc
ExceptionClass overrideEc
Definition: faults.hh:378
gem5::ArmISA::ArmFault::WPOINT_NOCM
@ WPOINT_NOCM
Definition: faults.hh:163
gem5::PowerISA::AlignmentFault
Definition: faults.hh:82
gem5::ArmISA::SupervisorCall::SupervisorCall
SupervisorCall(ExtMachInst _machInst, uint32_t _iss, ExceptionClass _overrideEc=EC_INVALID)
Definition: faults.hh:342
gem5::ArmISA::ArmFault::FaultVals::armPcOffset
const uint8_t armPcOffset
Definition: faults.hh:180
gem5::ArmISA::MISCREG_IFAR
@ MISCREG_IFAR
Definition: misc.hh:286
gem5::ArmISA::DataAbort::srt
uint8_t srt
Definition: faults.hh:517
gem5::ArmISA::ArmFault::FaultVals::lowerEL64Offset
const uint16_t lowerEL64Offset
Definition: faults.hh:175
gem5::ArmISA::VirtualInterrupt::VirtualInterrupt
VirtualInterrupt()
Definition: faults.cc:1494
gem5::ArmISA::ArmFault::ArmFault
ArmFault(ExtMachInst _machInst=0, uint32_t _iss=0)
Definition: faults.hh:215
gem5::ArmISA::DataAbort::annotate
void annotate(AnnotationIDs id, uint64_t val) override
Definition: faults.cc:1418
gem5::ArmISA::ArmFault::SF
@ SF
Definition: faults.hh:146
gem5::ArmISA::ArmFault::FaultVals::count
FaultStat count
Definition: faults.hh:196
gem5::ArmISA::ArmFault::nextMode
virtual OperatingMode nextMode()=0
gem5::ArmISA::FastInterrupt::fiqDisable
bool fiqDisable(ThreadContext *tc) override
Definition: faults.cc:1528
gem5::ArmISA::SupervisorTrap::SupervisorTrap
SupervisorTrap(ExtMachInst _machInst, uint32_t _iss, ExceptionClass _overrideEc=EC_INVALID)
Definition: faults.hh:381
gem5::ArmISA::ArmFault::FaultVals::abortDisable
const bool abortDisable
Definition: faults.hh:189
gem5::ArmISA::DataAbort::cm
uint8_t cm
Definition: faults.hh:518
gem5::ArmISA::SecureMonitorTrap::SecureMonitorTrap
SecureMonitorTrap(ExtMachInst _machInst, uint32_t _iss, ExceptionClass _overrideEc=EC_INVALID)
Definition: faults.hh:399
gem5::ArmISA::MISCREG_HDFAR
@ MISCREG_HDFAR
Definition: misc.hh:289
null_static_inst.hh
gem5::ArmISA::AbortFault::isStage2
bool isStage2() const override
Definition: faults.hh:481
gem5::ArmISA::VirtualDataAbort::HFarIndex
static const MiscRegIndex HFarIndex
Definition: faults.hh:547
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::SoftwareBreakpoint::SoftwareBreakpoint
SoftwareBreakpoint(ExtMachInst _mach_inst, uint32_t _iss)
Definition: faults.cc:1600
gem5::ArmISA::PrefetchAbort::PrefetchAbort
PrefetchAbort(Addr _addr, uint8_t _source, bool _stage2=false, ArmFault::TranMethod _tranMethod=ArmFault::UnknownTran, ArmFault::DebugType _debug=ArmFault::NODEBUG)
Definition: faults.hh:494
gem5::ArmISA::SoftwareBreakpoint
System error (AArch64 only)
Definition: faults.hh:622
gem5::ArmISA::ArmFaultVals::offset
FaultOffset offset(ThreadContext *tc) override
Definition: faults.cc:955
gem5::ArmISA::ArmFault::AsynchPtyErrOnMemoryAccess
@ AsynchPtyErrOnMemoryAccess
Definition: faults.hh:110
gem5::ArmISA::PrefetchAbort
Definition: faults.hh:487
gem5::ArmISA::SoftwareStepFault::iss
uint32_t iss() const override
Definition: faults.cc:1763
gem5::ArmISA::PCAlignmentFault::PCAlignmentFault
PCAlignmentFault(Addr _faultPC)
Definition: faults.hh:595
gem5::ArmISA::MISCREG_DFSR
@ MISCREG_DFSR
Definition: misc.hh:268
gem5::ArmISA::HypervisorCall::ec
ExceptionClass ec(ThreadContext *tc) const override
Definition: faults.cc:942
gem5::ArmISA::MiscRegIndex
MiscRegIndex
Definition: misc.hh:59
gem5::ArmISA::HardwareBreakpoint::ec
ExceptionClass ec(ThreadContext *tc) const override
Definition: faults.cc:1634
gem5::ArmISA::ArmFaultVals::routeToMonitor
virtual bool routeToMonitor(ThreadContext *tc) const override
Definition: faults.hh:276
gem5::ArmISA::DataAbort::FsrIndex
static const MiscRegIndex FsrIndex
Definition: faults.hh:511
gem5::ArmISA::va
Bitfield< 8 > va
Definition: misc_types.hh:275
gem5::ArmISA::ArmFault::getFsr
virtual FSR getFsr(ThreadContext *tc) const
Definition: faults.hh:254
gem5::ArmISA::ArmFault::InstructionCacheMaintenance
@ InstructionCacheMaintenance
Definition: faults.hh:98
gem5::ArmISA::AbortFault::getFaultVAddr
bool getFaultVAddr(Addr &va) const override
Definition: faults.cc:1267
gem5::ArmISA::AbortFault::OVAddr
Addr OVAddr
Original virtual address.
Definition: faults.hh:451
gem5::ArmISA::ExceptionClass
ExceptionClass
Definition: types.hh:293
gem5::ArmISA::SoftwareStepFault::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1743
full_system.hh
gem5::FaultName
const typedef char * FaultName
Definition: faults.hh:53
gem5::ArmISA::ArmFault::getFaultAddrReg64
MiscRegIndex getFaultAddrReg64() const
Definition: faults.cc:382
gem5::ArmISA::HardwareBreakpoint::HardwareBreakpoint
HardwareBreakpoint(Addr _vaddr, uint32_t _iss)
Definition: faults.cc:1620
gem5::ArmISA::Reset::getVector
Addr getVector(ThreadContext *tc) override
Definition: faults.cc:756
gem5::ArmISA::AbortFault::srcEncoded
uint8_t srcEncoded
Definition: faults.hh:455
gem5::ArmISA::ArmFault
Definition: faults.hh:64
gem5::ArmISA::ArmFault::FaultVals::currELHOffset
const uint16_t currELHOffset
Definition: faults.hh:174
gem5::ArmISA::AbortFault::faultAddr
Addr faultAddr
The virtual address the fault occured at.
Definition: faults.hh:445
gem5::ArmISA::FaultOffset
Addr FaultOffset
Definition: faults.hh:60
gem5::ArmISA::ArmFault::FaultVals::fiqDisable
const bool fiqDisable
Definition: faults.hh:190
gem5::X86ISA::ExtMachInst
Definition: types.hh:206
gem5::ArmISA::ArmFault::aarch64FaultSources
static uint8_t aarch64FaultSources[NumFaultSources]
Encodings of the fault sources in AArch64 state.
Definition: faults.hh:130
gem5::ArmISA::SupervisorCall::overrideEc
ExceptionClass overrideEc
Definition: faults.hh:340
gem5::ArmISA::PrefetchAbort::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1311
gem5::ArmISA::EL0
@ EL0
Definition: types.hh:266
gem5::ArmISA::ArmFault::TranMethod
TranMethod
Definition: faults.hh:150
gem5::ArmISA::SupervisorCall::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:881
gem5::ArmISA::ArmFault::invoke64
void invoke64(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)
Definition: faults.cc:636
gem5::ArmISA::ArmFault::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:489
gem5::ArmISA::SupervisorTrap::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1031
gem5::ArmISA::DataAbort::isv
bool isv
Definition: faults.hh:514
gem5::ArmISA::Watchpoint::annotate
void annotate(AnnotationIDs id, uint64_t val) override
Definition: faults.cc:1710
gem5::ArmISA::SystemError
System error (AArch64 only)
Definition: faults.hh:611
gem5::ArmISA::AbortFault::isMMUFault
bool isMMUFault() const
Definition: faults.cc:1250
gem5::ArmISA::ArmFault::getVector
virtual Addr getVector(ThreadContext *tc)
Definition: faults.cc:311
gem5::ArmISA::ArmFault::isResetSPSR
bool isResetSPSR()
Definition: faults.hh:232
gem5::ArmISA::ArmFaultVals::name
FaultName name() const override
Definition: faults.hh:269
gem5::ArmISA::ArmFault::CM
@ CM
Definition: faults.hh:139
gem5::FaultBase
Definition: faults.hh:58
gem5::ArmISA::Watchpoint::iss
uint32_t iss() const override
Definition: faults.cc:1677
gem5::ArmISA::FastInterrupt
Definition: faults.hh:572
gem5::ArmISA::SPAlignmentFault
Stack pointer alignment fault (AArch64 only)
Definition: faults.hh:603
gem5::ArmISA::AbortFault::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:1065
gem5::ArmISA::ArmFault::span
bool span
Definition: faults.hh:85
gem5::ArmISA::ArmFault::TranslationLL
@ TranslationLL
Definition: faults.hh:101
gem5::ArmISA::AbortFault::stage2
bool stage2
Definition: faults.hh:456
gem5::ArmISA::SecureMonitorCall::SecureMonitorCall
SecureMonitorCall(ExtMachInst _machInst)
Definition: faults.hh:361
gem5::ArmISA::SoftwareStepFault::SoftwareStepFault
SoftwareStepFault(ExtMachInst _mach_inst, bool is_ldx, bool stepped)
Definition: faults.cc:1734
misc.hh
gem5::ArmISA::ArmFault::WPOINT_CM
@ WPOINT_CM
Definition: faults.hh:162
gem5::ArmISA::ArmFaultVals::ec
ExceptionClass ec(ThreadContext *tc) const override
Definition: faults.hh:291
gem5::ArmISA::ArmFault::ec
virtual ExceptionClass ec(ThreadContext *tc) const =0
gem5::ArmISA::ArmFault::AnnotationIDs
AnnotationIDs
Definition: faults.hh:132
gem5::ArmISA::ArmFault::DebugType
DebugType
Definition: faults.hh:157
gem5::ArmISA::ArmFault::annotate
virtual void annotate(AnnotationIDs id, uint64_t val)
Definition: faults.hh:237
logging.hh
gem5::ArmISA::ArmFault::TLBConflictAbort
@ TLBConflictAbort
Definition: faults.hh:107
gem5::ArmISA::ArmFault::AccessFlagLL
@ AccessFlagLL
Definition: faults.hh:102
gem5::ArmISA::SoftwareStepFault::ec
ExceptionClass ec(ThreadContext *tc) const override
Definition: faults.cc:1753
gem5::ArmISA::UndefinedInstruction::iss
uint32_t iss() const override
Definition: faults.cc:833
gem5::ArmISA::EC_INVALID
@ EC_INVALID
Definition: types.hh:295
gem5::ArmISA::FastInterrupt::routeToMonitor
bool routeToMonitor(ThreadContext *tc) const override
Definition: faults.cc:1498
gem5::ArmISA::ArmFault::S1PTW
@ S1PTW
Definition: faults.hh:134
gem5::ArmISA::VirtualDataAbort::VirtualDataAbort
VirtualDataAbort(Addr _addr, TlbEntry::DomainType _domain, bool _write, uint8_t _source)
Definition: faults.hh:549
gem5::ArmISA::Reset::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:774
gem5::ArmISA::ArmFault::FaultVals::nextMode
const OperatingMode nextMode
Definition: faults.hh:178
gem5::ArmISA::HypervisorCall::HypervisorCall
HypervisorCall(ExtMachInst _machInst, uint32_t _imm)
Definition: faults.cc:923
gem5::ArmISA::ArmSev::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:1779
gem5::ArmISA::ArmFault::toMode
OperatingMode toMode
Definition: faults.hh:77
gem5::ArmISA::ArmFault::routeToHyp
virtual bool routeToHyp(ThreadContext *tc) const
Definition: faults.hh:243
gem5::ArmISA::ArmFault::SRT
@ SRT
Definition: faults.hh:138
gem5::ArmISA::HardwareBreakpoint::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:1644
gem5::ArmISA::DataAbort::sse
uint8_t sse
Definition: faults.hh:516
gem5::ArmISA::ArmFault::vectorCatch
bool vectorCatch(ThreadContext *tc, const StaticInstPtr &inst)
Definition: faults.cc:730
gem5::ArmISA::Interrupt::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1477
gem5::ArmISA::AbortFault::write
bool write
Definition: faults.hh:452
gem5::ArmISA::PrefetchAbort::ec
ExceptionClass ec(ThreadContext *tc) const override
Definition: faults.cc:1274
gem5::ArmISA::DataAbort::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1367
gem5::ArmISA::HypervisorCall::routeToMonitor
bool routeToMonitor(ThreadContext *tc) const override
Definition: faults.cc:930
gem5::ArmISA::DataAbort::ar
bool ar
Definition: faults.hh:522
gem5::ArmISA::IllegalInstSetStateFault::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1824
gem5::ArmISA::SystemError::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:1573
gem5::ArmISA::ArmFault::machInst
ExtMachInst machInst
Definition: faults.hh:67
gem5::ArmISA::ArmFault::armPcOffset
virtual uint8_t armPcOffset(bool isHyp)=0
gem5::ArmISA::SPAlignmentFault::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1562
gem5::ArmISA::ArmFault::fromMode
OperatingMode fromMode
Definition: faults.hh:76
gem5::ArmISA::SecureMonitorTrap::machInst
ExtMachInst machInst
Definition: faults.hh:395
gem5::ArmISA::SupervisorCall::ec
ExceptionClass ec(ThreadContext *tc) const override
Definition: faults.cc:889
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::ArmISA::ArmFault::routeToMonitor
virtual bool routeToMonitor(ThreadContext *tc) const =0
gem5::ArmISA::IllegalInstSetStateFault::IllegalInstSetStateFault
IllegalInstSetStateFault()
Definition: faults.cc:1820
gem5::ArmISA::AbortFault::source
uint8_t source
Definition: faults.hh:454
gem5::ArmISA::ArmFault::isStage2
virtual bool isStage2() const
Definition: faults.hh:253
gem5::ArmISA::VirtualInterrupt
Definition: faults.hh:566
gem5::ArmISA::Interrupt
Definition: faults.hh:557
gem5::ArmISA::ArmFault::longDescFaultSources
static uint8_t longDescFaultSources[NumFaultSources]
Encodings of the fault sources when the long-desc.
Definition: faults.hh:128
gem5::ArmISA::AbortFault
Definition: faults.hh:436
gem5::ArmISA::ArmFault::SAS
@ SAS
Definition: faults.hh:136
gem5::ArmISA::DataAbort::HFarIndex
static const MiscRegIndex HFarIndex
Definition: faults.hh:513
gem5::ArmISA::SecureMonitorCall::vectorCatchFlag
uint32_t vectorCatchFlag() const override
Definition: faults.hh:371
gem5::ArmISA::ArmFault::UnknownTran
@ UnknownTran
Definition: faults.hh:154
gem5::ArmISA::OperatingMode
OperatingMode
Definition: types.hh:272
gem5::ArmISA::ArmFault::OVA
@ OVA
Definition: faults.hh:135
gem5::ArmISA::SoftwareStepFault::stepped
bool stepped
Definition: faults.hh:664
gem5::ArmISA::AbortFault::s1ptw
bool s1ptw
Definition: faults.hh:457
gem5::ArmISA::VirtualFastInterrupt::VirtualFastInterrupt
VirtualFastInterrupt()
Definition: faults.cc:1539
gem5::ArmISA::SecureMonitorTrap::overrideEc
ExceptionClass overrideEc
Definition: faults.hh:396
gem5::ArmISA::ArmFaultVals::fiqDisable
bool fiqDisable(ThreadContext *tc) override
Definition: faults.hh:290
gem5::ArmISA::VirtualDataAbort::FsrIndex
static const MiscRegIndex FsrIndex
Definition: faults.hh:545
gem5::ArmISA::ArmFaultVals::iss
uint32_t iss() const override
Definition: faults.hh:292
gem5::ArmISA::Interrupt::abortDisable
bool abortDisable(ThreadContext *tc) override
Definition: faults.cc:1485
gem5::ArmISA::VirtualDataAbort::FarIndex
static const MiscRegIndex FarIndex
Definition: faults.hh:546
gem5::ArmISA::ExceptionLevel
ExceptionLevel
Definition: types.hh:264
gem5::ArmISA::Watchpoint::ec
ExceptionClass ec(ThreadContext *tc) const override
Definition: faults.cc:1725
gem5::ArmISA::AbortFault::tranMethod
ArmFault::TranMethod tranMethod
Definition: faults.hh:458
gem5::ArmISA::ArmFault::fiqDisable
virtual bool fiqDisable(ThreadContext *tc)=0
gem5::ArmISA::Watchpoint::write
bool write
Definition: faults.hh:647
gem5::ArmISA::IllegalInstSetStateFault
Illegal Instruction Set State fault (AArch64 only)
Definition: faults.hh:683
gem5::ArmISA::ArmFault::FaultVals::armPcElrOffset
const uint8_t armPcElrOffset
Definition: faults.hh:185

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