gem5  v21.2.1.1
faults.hh
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41 
42 #ifndef __ARM_FAULTS_HH__
43 #define __ARM_FAULTS_HH__
44 
45 #include "arch/arm/pagetable.hh"
46 #include "arch/arm/regs/misc.hh"
47 #include "arch/arm/types.hh"
48 #include "base/logging.hh"
49 #include "cpu/null_static_inst.hh"
50 #include "sim/faults.hh"
51 #include "sim/full_system.hh"
52 
53 namespace gem5
54 {
55 
56 // The design of the "name" and "vect" functions is in sim/faults.hh
57 
58 namespace ArmISA
59 {
60 typedef Addr FaultOffset;
61 
62 class ArmStaticInst;
63 
64 class ArmFault : public FaultBase
65 {
66  protected:
68  uint32_t issRaw;
69 
70  // Helper variables for ARMv8 exception handling
71  bool bStep; // True if the Arm Faul exception is a software Step exception
72  bool from64; // True if the exception is generated from the AArch64 state
73  bool to64; // True if the exception is taken in AArch64 state
74  ExceptionLevel fromEL; // Source exception level
75  ExceptionLevel toEL; // Target exception level
76  OperatingMode fromMode; // Source operating mode (aarch32)
77  OperatingMode toMode; // Next operating mode (aarch32)
78 
79  // This variable is true if the above fault specific informations
80  // have been updated. This is to prevent that a client is using their
81  // un-updated default constructed value.
83 
84  bool hypRouted; // True if the fault has been routed to Hypervisor
85  bool span; // True if the fault is setting the PSTATE.PAN bit
86 
87  virtual Addr getVector(ThreadContext *tc);
89 
90  public:
96  {
98  InstructionCacheMaintenance, // Short-desc. format only
107  TLBConflictAbort, // Requires LPAE
111  AddressSizeLL, // AArch64 only
112 
113  // Not real faults. These are faults to allow the translation function
114  // to inform the memory access function not to proceed for a prefetch
115  // that misses in the TLB or that targets an uncacheable address
118 
121  };
122 
131 
133  {
134  S1PTW, // DataAbort, PrefetchAbort: Stage 1 Page Table Walk,
135  OVA, // DataAbort, PrefetchAbort: stage 1 Virtual Address for stage 2 faults
136  SAS, // DataAbort: Syndrome Access Size
137  SSE, // DataAbort: Syndrome Sign Extend
138  SRT, // DataAbort: Syndrome Register Transfer
139  CM, // DataAbort: Cache Maintenance/Address Translation Op
140  OFA, // DataAbort: Override fault Address. This is needed when
141  // the abort is triggered by a CMO. The faulting address is
142  // then the address specified in the register argument of the
143  // instruction and not the cacheline address (See FAR doc)
144 
145  // AArch64 only
146  SF, // DataAbort: width of the accessed register is SixtyFour
147  AR // DataAbort: Acquire/Release semantics
148  };
149 
151  {
155  };
156 
158  {
159  NODEBUG = 0,
164  };
165 
166  struct FaultVals
167  {
169 
171 
172  // Offsets used for exceptions taken in AArch64 state
173  const uint16_t currELTOffset;
174  const uint16_t currELHOffset;
175  const uint16_t lowerEL64Offset;
176  const uint16_t lowerEL32Offset;
177 
179 
180  const uint8_t armPcOffset;
181  const uint8_t thumbPcOffset;
182  // The following two values are used in place of armPcOffset and
183  // thumbPcOffset when the exception return address is saved into ELR
184  // registers (exceptions taken in HYP mode or in AArch64 state)
185  const uint8_t armPcElrOffset;
186  const uint8_t thumbPcElrOffset;
187 
188  const bool hypTrappable;
189  const bool abortDisable;
190  const bool fiqDisable;
191 
192  // Exception class used to appropriately set the syndrome register
193  // (exceptions taken in HYP mode or in AArch64 state)
195 
196  FaultVals(const FaultName& name_, const FaultOffset& offset_,
197  const uint16_t& currELTOffset_, const uint16_t& currELHOffset_,
198  const uint16_t& lowerEL64Offset_,
199  const uint16_t& lowerEL32Offset_,
200  const OperatingMode& nextMode_, const uint8_t& armPcOffset_,
201  const uint8_t& thumbPcOffset_, const uint8_t& armPcElrOffset_,
202  const uint8_t& thumbPcElrOffset_, const bool& hypTrappable_,
203  const bool& abortDisable_, const bool& fiqDisable_,
204  const ExceptionClass& ec_)
205  : name(name_), offset(offset_), currELTOffset(currELTOffset_),
206  currELHOffset(currELHOffset_), lowerEL64Offset(lowerEL64Offset_),
207  lowerEL32Offset(lowerEL32Offset_), nextMode(nextMode_),
208  armPcOffset(armPcOffset_), thumbPcOffset(thumbPcOffset_),
209  armPcElrOffset(armPcElrOffset_), thumbPcElrOffset(thumbPcElrOffset_),
210  hypTrappable(hypTrappable_), abortDisable(abortDisable_),
211  fiqDisable(fiqDisable_), ec(ec_) {}
212  };
213 
214  ArmFault(ExtMachInst _machInst = 0, uint32_t _iss = 0) :
215  machInst(_machInst), issRaw(_iss), bStep(false), from64(false),
217  faultUpdated(false), hypRouted(false), span(false) {}
218 
219  // Returns the actual syndrome register to use based on the target
220  // exception level
222  // Returns the actual fault address register to use based on the target
223  // exception level
225 
226  void invoke(ThreadContext *tc, const StaticInstPtr &inst =
227  nullStaticInstPtr) override;
228  void invoke32(ThreadContext *tc, const StaticInstPtr &inst =
230  void invoke64(ThreadContext *tc, const StaticInstPtr &inst =
232  void update(ThreadContext *tc);
233  bool isResetSPSR(){ return bStep; }
234 
235  bool vectorCatch(ThreadContext *tc, const StaticInstPtr &inst);
236 
238  virtual void annotate(AnnotationIDs id, uint64_t val) {}
239  virtual FaultOffset offset(ThreadContext *tc) = 0;
240  virtual FaultOffset offset64(ThreadContext *tc) = 0;
241  virtual OperatingMode nextMode() = 0;
242  virtual bool routeToMonitor(ThreadContext *tc) const = 0;
243  virtual bool routeToHyp(ThreadContext *tc) const { return false; }
244  virtual uint8_t armPcOffset(bool isHyp) = 0;
245  virtual uint8_t thumbPcOffset(bool isHyp) = 0;
246  virtual uint8_t armPcElrOffset() = 0;
247  virtual uint8_t thumbPcElrOffset() = 0;
248  virtual bool abortDisable(ThreadContext *tc) = 0;
249  virtual bool fiqDisable(ThreadContext *tc) = 0;
250  virtual ExceptionClass ec(ThreadContext *tc) const = 0;
251  virtual uint32_t vectorCatchFlag() const { return 0x0; }
252  virtual uint32_t iss() const = 0;
253  virtual bool isStage2() const { return false; }
254  virtual FSR getFsr(ThreadContext *tc) const { return 0; }
255  virtual void setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg);
256  virtual bool getFaultVAddr(Addr &va) const { return false; }
257  OperatingMode getToMode() const { return toMode; }
258 };
259 
260 template<typename T>
261 class ArmFaultVals : public ArmFault
262 {
263  protected:
264  static FaultVals vals;
265 
266  public:
267  ArmFaultVals<T>(ExtMachInst _machInst = 0, uint32_t _iss = 0) :
268  ArmFault(_machInst, _iss) {}
269  FaultName name() const override { return vals.name; }
270  FaultOffset offset(ThreadContext *tc) override;
271 
272  FaultOffset offset64(ThreadContext *tc) override;
273 
274  OperatingMode nextMode() override { return vals.nextMode; }
275  virtual bool routeToMonitor(ThreadContext *tc) const override {
276  return false;
277  }
278  uint8_t armPcOffset(bool isHyp) override {
279  return isHyp ? vals.armPcElrOffset
280  : vals.armPcOffset;
281  }
282  uint8_t thumbPcOffset(bool isHyp) override {
283  return isHyp ? vals.thumbPcElrOffset
285  }
286  uint8_t armPcElrOffset() override { return vals.armPcElrOffset; }
287  uint8_t thumbPcElrOffset() override { return vals.thumbPcElrOffset; }
288  bool abortDisable(ThreadContext* tc) override { return vals.abortDisable; }
289  bool fiqDisable(ThreadContext* tc) override { return vals.fiqDisable; }
290  ExceptionClass ec(ThreadContext *tc) const override { return vals.ec; }
291  uint32_t iss() const override { return issRaw; }
292 };
293 
294 class Reset : public ArmFaultVals<Reset>
295 {
296  protected:
297  Addr getVector(ThreadContext *tc) override;
298 
299  public:
300  void invoke(ThreadContext *tc, const StaticInstPtr &inst =
301  nullStaticInstPtr) override;
302 };
303 
304 class UndefinedInstruction : public ArmFaultVals<UndefinedInstruction>
305 {
306  protected:
307  bool unknown;
308  bool disabled;
310  const char *mnemonic;
311 
312  public:
314  bool _unknown,
315  const char *_mnemonic = NULL,
316  bool _disabled = false) :
318  unknown(_unknown), disabled(_disabled),
319  overrideEc(EC_INVALID), mnemonic(_mnemonic)
320  {}
321  UndefinedInstruction(ExtMachInst _machInst, uint32_t _iss,
322  ExceptionClass _overrideEc, const char *_mnemonic = NULL) :
323  ArmFaultVals<UndefinedInstruction>(_machInst, _iss),
324  unknown(false), disabled(true), overrideEc(_overrideEc),
325  mnemonic(_mnemonic)
326  {}
327 
328  void invoke(ThreadContext *tc, const StaticInstPtr &inst =
329  nullStaticInstPtr) override;
330  bool routeToHyp(ThreadContext *tc) const override;
331  ExceptionClass ec(ThreadContext *tc) const override;
332  uint32_t iss() const override;
333  uint32_t vectorCatchFlag() const override { return 0x02000002; }
334 };
335 
336 class SupervisorCall : public ArmFaultVals<SupervisorCall>
337 {
338  protected:
340  public:
341  SupervisorCall(ExtMachInst _machInst, uint32_t _iss,
342  ExceptionClass _overrideEc = EC_INVALID) :
343  ArmFaultVals<SupervisorCall>(_machInst, _iss),
344  overrideEc(_overrideEc)
345  {
346  bStep = true;
347  }
348 
349  void invoke(ThreadContext *tc, const StaticInstPtr &inst =
350  nullStaticInstPtr) override;
351  bool routeToHyp(ThreadContext *tc) const override;
352  ExceptionClass ec(ThreadContext *tc) const override;
353  uint32_t iss() const override;
354  uint32_t vectorCatchFlag() const override { return 0x04000404; }
355 };
356 
357 class SecureMonitorCall : public ArmFaultVals<SecureMonitorCall>
358 {
359  public:
361  ArmFaultVals<SecureMonitorCall>(_machInst)
362  {
363  bStep = true;
364  }
365 
366  void invoke(ThreadContext *tc, const StaticInstPtr &inst =
367  nullStaticInstPtr) override;
368  ExceptionClass ec(ThreadContext *tc) const override;
369  uint32_t iss() const override;
370  uint32_t vectorCatchFlag() const override { return 0x00000400; }
371 };
372 
373 class SupervisorTrap : public ArmFaultVals<SupervisorTrap>
374 {
375  protected:
378 
379  public:
380  SupervisorTrap(ExtMachInst _machInst, uint32_t _iss,
381  ExceptionClass _overrideEc = EC_INVALID) :
382  ArmFaultVals<SupervisorTrap>(_machInst, _iss),
383  overrideEc(_overrideEc)
384  {}
385 
386  bool routeToHyp(ThreadContext *tc) const override;
387  uint32_t iss() const override;
388  ExceptionClass ec(ThreadContext *tc) const override;
389 };
390 
391 class SecureMonitorTrap : public ArmFaultVals<SecureMonitorTrap>
392 {
393  protected:
396 
397  public:
398  SecureMonitorTrap(ExtMachInst _machInst, uint32_t _iss,
399  ExceptionClass _overrideEc = EC_INVALID) :
400  ArmFaultVals<SecureMonitorTrap>(_machInst, _iss),
401  overrideEc(_overrideEc)
402  {}
403 
404  ExceptionClass ec(ThreadContext *tc) const override;
405 };
406 
407 class HypervisorCall : public ArmFaultVals<HypervisorCall>
408 {
409  public:
410  HypervisorCall(ExtMachInst _machInst, uint32_t _imm);
411 
412  bool routeToHyp(ThreadContext *tc) const override;
413  bool routeToMonitor(ThreadContext *tc) const override;
414  ExceptionClass ec(ThreadContext *tc) const override;
415  uint32_t vectorCatchFlag() const override { return 0xFFFFFFFF; }
416 };
417 
418 class HypervisorTrap : public ArmFaultVals<HypervisorTrap>
419 {
420  protected:
423 
424  public:
425  HypervisorTrap(ExtMachInst _machInst, uint32_t _iss,
426  ExceptionClass _overrideEc = EC_INVALID) :
427  ArmFaultVals<HypervisorTrap>(_machInst, _iss),
428  overrideEc(_overrideEc)
429  {}
430 
431  ExceptionClass ec(ThreadContext *tc) const override;
432 };
433 
434 template <class T>
435 class AbortFault : public ArmFaultVals<T>
436 {
437  protected:
451  bool write;
453  uint8_t source;
454  uint8_t srcEncoded;
455  bool stage2;
456  bool s1ptw;
459 
460  public:
461  AbortFault(Addr _faultAddr, bool _write, TlbEntry::DomainType _domain,
462  uint8_t _source, bool _stage2,
465  faultAddr(_faultAddr), OVAddr(0), write(_write),
466  domain(_domain), source(_source), srcEncoded(0),
467  stage2(_stage2), s1ptw(false), tranMethod(_tranMethod),
468  debugType(_debug)
469  {}
470 
471  bool getFaultVAddr(Addr &va) const override;
472 
473  void invoke(ThreadContext *tc, const StaticInstPtr &inst =
474  nullStaticInstPtr) override;
475 
476  FSR getFsr(ThreadContext *tc) const override;
477  uint8_t getFaultStatusCode(ThreadContext *tc) const;
478  bool abortDisable(ThreadContext *tc) override;
479  uint32_t iss() const override;
480  bool isStage2() const override { return stage2; }
481  void annotate(ArmFault::AnnotationIDs id, uint64_t val) override;
482  void setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg) override;
483  bool isMMUFault() const;
484 };
485 
486 class PrefetchAbort : public AbortFault<PrefetchAbort>
487 {
488  public:
492 
493  PrefetchAbort(Addr _addr, uint8_t _source, bool _stage2 = false,
496  AbortFault<PrefetchAbort>(_addr, false, TlbEntry::DomainType::NoAccess,
497  _source, _stage2, _tranMethod, _debug)
498  {}
499 
500  ExceptionClass ec(ThreadContext *tc) const override;
501  // @todo: external aborts should be routed if SCR.EA == 1
502  bool routeToMonitor(ThreadContext *tc) const override;
503  bool routeToHyp(ThreadContext *tc) const override;
504  uint32_t vectorCatchFlag() const override { return 0x08000808; }
505 };
506 
507 class DataAbort : public AbortFault<DataAbort>
508 {
509  public:
513  bool isv;
514  uint8_t sas;
515  uint8_t sse;
516  uint8_t srt;
517  uint8_t cm;
518 
519  // AArch64 only
520  bool sf;
521  bool ar;
522 
523  DataAbort(Addr _addr, TlbEntry::DomainType _domain, bool _write, uint8_t _source,
524  bool _stage2=false,
527  AbortFault<DataAbort>(_addr, _write, _domain, _source, _stage2,
528  _tranMethod, _debug_type),
529  isv(false), sas (0), sse(0), srt(0), cm(0), sf(false), ar(false)
530  {}
531 
532  ExceptionClass ec(ThreadContext *tc) const override;
533  // @todo: external aborts should be routed if SCR.EA == 1
534  bool routeToMonitor(ThreadContext *tc) const override;
535  bool routeToHyp(ThreadContext *tc) const override;
536  uint32_t iss() const override;
537  void annotate(AnnotationIDs id, uint64_t val) override;
538  uint32_t vectorCatchFlag() const override { return 0x10001010; }
539 };
540 
541 class VirtualDataAbort : public AbortFault<VirtualDataAbort>
542 {
543  public:
547 
548  VirtualDataAbort(Addr _addr, TlbEntry::DomainType _domain, bool _write,
549  uint8_t _source) :
550  AbortFault<VirtualDataAbort>(_addr, _write, _domain, _source, false)
551  {}
552 
553  void invoke(ThreadContext *tc, const StaticInstPtr &inst) override;
554 };
555 
556 class Interrupt : public ArmFaultVals<Interrupt>
557 {
558  public:
559  bool routeToMonitor(ThreadContext *tc) const override;
560  bool routeToHyp(ThreadContext *tc) const override;
561  bool abortDisable(ThreadContext *tc) override;
562  uint32_t vectorCatchFlag() const override { return 0x40004040; }
563 };
564 
565 class VirtualInterrupt : public ArmFaultVals<VirtualInterrupt>
566 {
567  public:
569 };
570 
571 class FastInterrupt : public ArmFaultVals<FastInterrupt>
572 {
573  public:
574  bool routeToMonitor(ThreadContext *tc) const override;
575  bool routeToHyp(ThreadContext *tc) const override;
576  bool abortDisable(ThreadContext *tc) override;
577  bool fiqDisable(ThreadContext *tc) override;
578  uint32_t vectorCatchFlag() const override { return 0x80008080; }
579 };
580 
581 class VirtualFastInterrupt : public ArmFaultVals<VirtualFastInterrupt>
582 {
583  public:
585 };
586 
588 class PCAlignmentFault : public ArmFaultVals<PCAlignmentFault>
589 {
590  protected:
593  public:
594  PCAlignmentFault(Addr _faultPC) : faultPC(_faultPC)
595  {}
596  void invoke(ThreadContext *tc, const StaticInstPtr &inst =
597  nullStaticInstPtr) override;
598  bool routeToHyp(ThreadContext *tc) const override;
599 };
600 
602 class SPAlignmentFault : public ArmFaultVals<SPAlignmentFault>
603 {
604  public:
606  bool routeToHyp(ThreadContext *tc) const override;
607 };
608 
610 class SystemError : public ArmFaultVals<SystemError>
611 {
612  public:
613  SystemError();
614  void invoke(ThreadContext *tc, const StaticInstPtr &inst =
615  nullStaticInstPtr) override;
616  bool routeToMonitor(ThreadContext *tc) const override;
617  bool routeToHyp(ThreadContext *tc) const override;
618 };
619 
621 class SoftwareBreakpoint : public ArmFaultVals<SoftwareBreakpoint>
622 {
623  public:
624  SoftwareBreakpoint(ExtMachInst _mach_inst, uint32_t _iss);
625 
626  bool routeToHyp(ThreadContext *tc) const override;
627  ExceptionClass ec(ThreadContext *tc) const override;
628 };
629 
630 class HardwareBreakpoint : public ArmFaultVals<HardwareBreakpoint>
631 {
632  private:
634  public:
635  void invoke(ThreadContext *tc, const StaticInstPtr &inst =
636  nullStaticInstPtr) override;
637  HardwareBreakpoint(Addr _vaddr, uint32_t _iss);
638  bool routeToHyp(ThreadContext *tc) const override;
639  ExceptionClass ec(ThreadContext *tc) const override;
640 };
641 
642 class Watchpoint : public ArmFaultVals<Watchpoint>
643 {
644  private:
646  bool write;
647  bool cm;
648 
649  public:
650  Watchpoint(ExtMachInst _mach_inst, Addr _vaddr, bool _write, bool _cm);
651  void invoke(ThreadContext *tc, const StaticInstPtr &inst =
652  nullStaticInstPtr) override;
653  bool routeToHyp(ThreadContext *tc) const override;
654  uint32_t iss() const override;
655  ExceptionClass ec(ThreadContext *tc) const override;
656  void annotate(AnnotationIDs id, uint64_t val) override;
657 };
658 
659 class SoftwareStepFault : public ArmFaultVals<SoftwareStepFault>
660 {
661  private:
662  bool isldx;
663  bool stepped;
664 
665  public:
666  SoftwareStepFault(ExtMachInst _mach_inst, bool is_ldx, bool stepped);
667  bool routeToHyp(ThreadContext *tc) const override;
668  uint32_t iss() const override;
669  ExceptionClass ec(ThreadContext *tc) const override;
670 };
671 
672 // A fault that flushes the pipe, excluding the faulting instructions
673 class ArmSev : public ArmFaultVals<ArmSev>
674 {
675  public:
676  ArmSev () {}
677  void invoke(ThreadContext *tc, const StaticInstPtr &inst =
678  nullStaticInstPtr) override;
679 };
680 
682 class IllegalInstSetStateFault : public ArmFaultVals<IllegalInstSetStateFault>
683 {
684  public:
686 
687  bool routeToHyp(ThreadContext *tc) const override;
688 };
689 
690 /*
691  * Explicitly declare template static member variables to avoid warnings
692  * in some clang versions
693  */
718 
729 bool getFaultVAddr(Fault fault, Addr &va);
730 
731 } // namespace ArmISA
732 } // namespace gem5
733 
734 #endif // __ARM_FAULTS_HH__
gem5::ArmISA::ArmFault::FaultVals::thumbPcElrOffset
const uint8_t thumbPcElrOffset
Definition: faults.hh:186
gem5::ArmISA::MISCREG_DFAR
@ MISCREG_DFAR
Definition: misc.hh:283
gem5::ArmISA::ArmFault::NODEBUG
@ NODEBUG
Definition: faults.hh:159
gem5::ArmISA::ArmFault::fromEL
ExceptionLevel fromEL
Definition: faults.hh:74
gem5::ArmISA::AbortFault::annotate
void annotate(ArmFault::AnnotationIDs id, uint64_t val) override
Definition: faults.cc:1235
gem5::ArmISA::AbortFault::setSyndrome
void setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg) override
Definition: faults.cc:1162
gem5::ArmISA::ArmFault::FaultVals::ec
const ExceptionClass ec
Definition: faults.hh:194
gem5::ArmISA::ArmFault::NumFaultSources
@ NumFaultSources
Definition: faults.hh:119
gem5::ArmISA::SupervisorTrap::ec
ExceptionClass ec(ThreadContext *tc) const override
Definition: faults.cc:1063
gem5::ArmISA::UndefinedInstruction::mnemonic
const char * mnemonic
Definition: faults.hh:310
gem5::ArmISA::SPAlignmentFault::SPAlignmentFault
SPAlignmentFault()
Definition: faults.cc:1574
gem5::ArmISA::DataAbort::routeToMonitor
bool routeToMonitor(ThreadContext *tc) const override
Definition: faults.cc:1371
gem5::ArmISA::UndefinedInstruction::ec
ExceptionClass ec(ThreadContext *tc) const override
Definition: faults.cc:927
gem5::ArmISA::ArmFaultVals::thumbPcElrOffset
uint8_t thumbPcElrOffset() override
Definition: faults.hh:287
gem5::ArmISA::SoftwareBreakpoint::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1621
gem5::ArmISA::ArmFault::FaultVals::lowerEL32Offset
const uint16_t lowerEL32Offset
Definition: faults.hh:176
gem5::ArmISA::ArmFault::AddressSizeLL
@ AddressSizeLL
Definition: faults.hh:111
gem5::ArmISA::DataAbort::sf
bool sf
Definition: faults.hh:520
gem5::ArmISA::ArmFaultVals::armPcOffset
uint8_t armPcOffset(bool isHyp) override
Definition: faults.hh:278
gem5::ArmISA::PrefetchAbort::FsrIndex
static const MiscRegIndex FsrIndex
Definition: faults.hh:489
gem5::ArmISA::ArmFault::bStep
bool bStep
Definition: faults.hh:71
gem5::ArmISA::Watchpoint::Watchpoint
Watchpoint(ExtMachInst _mach_inst, Addr _vaddr, bool _write, bool _cm)
Definition: faults.cc:1686
gem5::ArmISA::AbortFault::AbortFault
AbortFault(Addr _faultAddr, bool _write, TlbEntry::DomainType _domain, uint8_t _source, bool _stage2, ArmFault::TranMethod _tranMethod=ArmFault::UnknownTran, ArmFault::DebugType _debug=ArmFault::NODEBUG)
Definition: faults.hh:461
gem5::ArmISA::ArmFault::FaultSourceInvalid
@ FaultSourceInvalid
Definition: faults.hh:120
gem5::ArmISA::PCAlignmentFault::faultPC
Addr faultPC
The unaligned value of the PC.
Definition: faults.hh:592
gem5::ArmISA::ArmFault::abortDisable
virtual bool abortDisable(ThreadContext *tc)=0
gem5::ArmISA::VirtualDataAbort
Definition: faults.hh:541
gem5::ArmISA::ArmStaticInst
Definition: static_inst.hh:65
gem5::ArmISA::ArmFault::BRKPOINT
@ BRKPOINT
Definition: faults.hh:160
gem5::ArmISA::HypervisorCall
Definition: faults.hh:407
gem5::ArmISA::PrefetchAbort::vectorCatchFlag
uint32_t vectorCatchFlag() const override
Definition: faults.hh:504
gem5::ArmISA::ArmFault::issRaw
uint32_t issRaw
Definition: faults.hh:68
gem5::ArmISA::ArmFault::AR
@ AR
Definition: faults.hh:147
gem5::ArmISA::SystemError::SystemError
SystemError()
Definition: faults.cc:1585
gem5::ArmISA::HypervisorTrap::overrideEc
ExceptionClass overrideEc
Definition: faults.hh:422
gem5::ArmISA::ArmFaultVals::vals
static FaultVals vals
Definition: faults.hh:264
gem5::ArmISA::SecureMonitorCall::ec
ExceptionClass ec(ThreadContext *tc) const override
Definition: faults.cc:1040
gem5::ArmISA::ArmFault::from64
bool from64
Definition: faults.hh:72
gem5::ArmISA::HypervisorCall::vectorCatchFlag
uint32_t vectorCatchFlag() const override
Definition: faults.hh:415
gem5::ArmISA::MODE_UNDEFINED
@ MODE_UNDEFINED
Definition: types.hh:288
gem5::ArmISA::HardwareBreakpoint::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1641
gem5::ArmISA::ArmFault::SynchExtAbtOnTranslTableWalkLL
@ SynchExtAbtOnTranslTableWalkLL
Definition: faults.hh:99
gem5::ArmISA::ArmFault::PrefetchUncacheable
@ PrefetchUncacheable
Definition: faults.hh:117
gem5::ArmISA::ArmFault::VECTORCATCH
@ VECTORCATCH
Definition: faults.hh:161
gem5::ArmISA::Interrupt::vectorCatchFlag
uint32_t vectorCatchFlag() const override
Definition: faults.hh:562
gem5::ArmISA::SupervisorCall::vectorCatchFlag
uint32_t vectorCatchFlag() const override
Definition: faults.hh:354
gem5::ArmISA::SupervisorCall
Definition: faults.hh:336
gem5::ArmISA::HypervisorTrap
Definition: faults.hh:418
gem5::ArmISA::PrefetchAbort::HFarIndex
static const MiscRegIndex HFarIndex
Definition: faults.hh:491
gem5::ArmISA::HypervisorTrap::ec
ExceptionClass ec(ThreadContext *tc) const override
Definition: faults.cc:963
gem5::ArmISA::UndefinedInstruction
Definition: faults.hh:304
gem5::ArmISA::UndefinedInstruction::overrideEc
ExceptionClass overrideEc
Definition: faults.hh:309
pagetable.hh
gem5::ArmISA::UndefinedInstruction::disabled
bool disabled
Definition: faults.hh:308
gem5::ArmISA::ArmFault::SynchronousExternalAbort
@ SynchronousExternalAbort
Definition: faults.hh:106
gem5::ArmISA::ArmFaultVals::thumbPcOffset
uint8_t thumbPcOffset(bool isHyp) override
Definition: faults.hh:282
gem5::ArmISA::ArmFault::LpaeTran
@ LpaeTran
Definition: faults.hh:152
gem5::ArmISA::ArmFaultVals::abortDisable
bool abortDisable(ThreadContext *tc) override
Definition: faults.hh:288
gem5::ArmISA::ArmFault::faultUpdated
bool faultUpdated
Definition: faults.hh:82
gem5::ArmISA::ArmFault::PrefetchTLBMiss
@ PrefetchTLBMiss
Definition: faults.hh:116
gem5::ArmISA::ArmFault::SSE
@ SSE
Definition: faults.hh:137
gem5::ArmISA::UndefinedInstruction::unknown
bool unknown
Definition: faults.hh:307
gem5::ArmISA::DataAbort::iss
uint32_t iss() const override
Definition: faults.cc:1407
gem5::ArmISA::FastInterrupt::vectorCatchFlag
uint32_t vectorCatchFlag() const override
Definition: faults.hh:578
gem5::ArmISA::PCAlignmentFault::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1568
gem5::ArmISA::HypervisorCall::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:951
gem5::ArmISA::UndefinedInstruction::UndefinedInstruction
UndefinedInstruction(ExtMachInst _machInst, bool _unknown, const char *_mnemonic=NULL, bool _disabled=false)
Definition: faults.hh:313
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::ArmISA::ArmFault::armPcElrOffset
virtual uint8_t armPcElrOffset()=0
gem5::ArmISA::Watchpoint::vAddr
Addr vAddr
Definition: faults.hh:645
gem5::ArmISA::AbortFault::getFaultStatusCode
uint8_t getFaultStatusCode(ThreadContext *tc) const
Definition: faults.cc:1173
gem5::ArmISA::PrefetchAbort::routeToMonitor
bool routeToMonitor(ThreadContext *tc) const override
Definition: faults.cc:1315
gem5::ArmISA::ArmSev
Definition: faults.hh:673
gem5::ArmISA::PCAlignmentFault
PC alignment fault (AArch64 only)
Definition: faults.hh:588
gem5::ArmISA::MISCREG_HIFAR
@ MISCREG_HIFAR
Definition: misc.hh:290
gem5::ArmISA::ArmFault::DomainLL
@ DomainLL
Definition: faults.hh:103
gem5::ArmISA::Interrupt::routeToMonitor
bool routeToMonitor(ThreadContext *tc) const override
Definition: faults.cc:1481
gem5::ArmISA::ArmFault::SynchPtyErrOnMemoryAccess
@ SynchPtyErrOnMemoryAccess
Definition: faults.hh:108
gem5::ArmISA::ArmFault::offset64
virtual FaultOffset offset64(ThreadContext *tc)=0
gem5::ArmISA::ArmFault::DebugEvent
@ DebugEvent
Definition: faults.hh:105
gem5::ArmISA::Watchpoint::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1716
gem5::ArmISA::AbortFault::debugType
ArmFault::DebugType debugType
Definition: faults.hh:458
gem5::ArmISA::ArmFault::FaultVals
Definition: faults.hh:166
gem5::ArmISA::Watchpoint
Definition: faults.hh:642
gem5::ArmISA::ArmFault::FaultVals::hypTrappable
const bool hypTrappable
Definition: faults.hh:188
gem5::ArmISA::PrefetchAbort::FarIndex
static const MiscRegIndex FarIndex
Definition: faults.hh:490
gem5::ArmISA::ArmFault::getToMode
OperatingMode getToMode() const
Definition: faults.hh:257
gem5::ArmISA::SupervisorTrap::iss
uint32_t iss() const override
Definition: faults.cc:1053
gem5::ArmISA::UndefinedInstruction::vectorCatchFlag
uint32_t vectorCatchFlag() const override
Definition: faults.hh:333
gem5::ArmISA::HardwareBreakpoint::vAddr
Addr vAddr
Definition: faults.hh:633
gem5::ArmISA::VirtualDataAbort::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst) override
Definition: faults.cc:1472
gem5::ArmISA::SoftwareStepFault::isldx
bool isldx
Definition: faults.hh:662
gem5::ArmISA::UndefinedInstruction::UndefinedInstruction
UndefinedInstruction(ExtMachInst _machInst, uint32_t _iss, ExceptionClass _overrideEc, const char *_mnemonic=NULL)
Definition: faults.hh:321
gem5::ArmISA::ArmFault::setSyndrome
virtual void setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg)
Definition: faults.cc:398
gem5::ArmISA::ArmFault::to64
bool to64
Definition: faults.hh:73
gem5::ArmISA::getFaultVAddr
bool getFaultVAddr(Fault fault, Addr &va)
Returns true if the fault passed as a first argument was triggered by a memory access,...
Definition: faults.cc:1847
faults.hh
types.hh
gem5::ArmISA::ArmFault::FaultVals::currELTOffset
const uint16_t currELTOffset
Definition: faults.hh:173
gem5::ArmISA::ArmFault::FaultVals::thumbPcOffset
const uint8_t thumbPcOffset
Definition: faults.hh:181
gem5::ArmISA::SoftwareBreakpoint::ec
ExceptionClass ec(ThreadContext *tc) const override
Definition: faults.cc:1631
gem5::ArmISA::SystemError::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1605
gem5::ArmISA::ArmFault::getVector64
Addr getVector64(ThreadContext *tc)
Definition: faults.cc:343
gem5::ArmISA::SystemError::routeToMonitor
bool routeToMonitor(ThreadContext *tc) const override
Definition: faults.cc:1596
gem5::ArmISA::TlbEntry
Definition: pagetable.hh:165
gem5::ArmISA::ArmFault::PermissionLL
@ PermissionLL
Definition: faults.hh:104
gem5::ArmISA::TlbEntry::DomainType
DomainType
Definition: pagetable.hh:177
gem5::ArmISA::SecureMonitorTrap
Definition: faults.hh:391
gem5::ArmISA::ArmSev::ArmSev
ArmSev()
Definition: faults.hh:676
gem5::ArmISA::ArmFault::AsynchronousExternalAbort
@ AsynchronousExternalAbort
Definition: faults.hh:109
gem5::ArmISA::PCAlignmentFault::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:1559
gem5::RefCountingPtr< StaticInst >
gem5::ArmISA::ArmFault::VmsaTran
@ VmsaTran
Definition: faults.hh:153
gem5::ArmISA::DataAbort
Definition: faults.hh:507
gem5::ArmISA::AbortFault::getFsr
FSR getFsr(ThreadContext *tc) const override
Definition: faults.cc:1199
gem5::ArmISA::SupervisorCall::iss
uint32_t iss() const override
Definition: faults.cc:911
gem5::ArmISA::MISCREG_IFSR
@ MISCREG_IFSR
Definition: misc.hh:271
gem5::ArmISA::ArmFaultVals::nextMode
OperatingMode nextMode() override
Definition: faults.hh:274
gem5::ArmISA::ArmFault::OFA
@ OFA
Definition: faults.hh:140
gem5::ArmISA::ArmFault::iss
virtual uint32_t iss() const =0
gem5::ArmISA::FastInterrupt::abortDisable
bool abortDisable(ThreadContext *tc) override
Definition: faults.cc:1534
gem5::ArmISA::Watchpoint::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:1707
gem5::ArmISA::ArmFault::instrAnnotate
ArmStaticInst * instrAnnotate(const StaticInstPtr &inst)
Definition: faults.cc:759
gem5::ArmISA::DataAbort::FarIndex
static const MiscRegIndex FarIndex
Definition: faults.hh:511
gem5::ArmISA::HypervisorTrap::HypervisorTrap
HypervisorTrap(ExtMachInst _machInst, uint32_t _iss, ExceptionClass _overrideEc=EC_INVALID)
Definition: faults.hh:425
gem5::nullStaticInstPtr
const StaticInstPtr nullStaticInstPtr
Statically allocated null StaticInstPtr.
Definition: null_static_inst.cc:36
gem5::ArmISA::ArmFault::thumbPcElrOffset
virtual uint8_t thumbPcElrOffset()=0
gem5::ArmISA::ArmFaultVals
Definition: faults.hh:261
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::ArmISA::ArmFault::offset
virtual FaultOffset offset(ThreadContext *tc)=0
gem5::ArmISA::Reset
Definition: faults.hh:294
gem5::ArmISA::SoftwareStepFault
Definition: faults.hh:659
gem5::ArmISA::HardwareBreakpoint
Definition: faults.hh:630
gem5::ArmISA::ArmFault::thumbPcOffset
virtual uint8_t thumbPcOffset(bool isHyp)=0
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::ArmISA::ArmFault::FaultSource
FaultSource
Generic fault source enums used to index into {short/long/aarch64}DescFaultSources[] to get the actua...
Definition: faults.hh:95
gem5::ArmISA::ArmFault::getSyndromeReg64
MiscRegIndex getSyndromeReg64() const
Definition: faults.cc:366
gem5::ArmISA::SecureMonitorCall::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:1031
gem5::ArmISA::AbortFault::domain
TlbEntry::DomainType domain
Definition: faults.hh:452
gem5::ArmISA::DataAbort::DataAbort
DataAbort(Addr _addr, TlbEntry::DomainType _domain, bool _write, uint8_t _source, bool _stage2=false, ArmFault::TranMethod _tranMethod=ArmFault::UnknownTran, ArmFault::DebugType _debug_type=ArmFault::NODEBUG)
Definition: faults.hh:523
gem5::ArmISA::ArmFaultVals::armPcElrOffset
uint8_t armPcElrOffset() override
Definition: faults.hh:286
gem5::ArmISA::ArmFault::toEL
ExceptionLevel toEL
Definition: faults.hh:75
gem5::ArmISA::SecureMonitorCall
Definition: faults.hh:357
gem5::ArmISA::DataAbort::ec
ExceptionClass ec(ThreadContext *tc) const override
Definition: faults.cc:1342
gem5::ArmISA::DataAbort::vectorCatchFlag
uint32_t vectorCatchFlag() const override
Definition: faults.hh:538
gem5::ArmISA::SecureMonitorTrap::ec
ExceptionClass ec(ThreadContext *tc) const override
Definition: faults.cc:1072
gem5::ArmISA::FastInterrupt::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1526
gem5::ArmISA::ArmFault::hypRouted
bool hypRouted
Definition: faults.hh:84
gem5::ArmISA::SupervisorTrap::machInst
ExtMachInst machInst
Definition: faults.hh:376
gem5::ArmISA::ArmFault::vectorCatchFlag
virtual uint32_t vectorCatchFlag() const
Definition: faults.hh:251
gem5::ArmISA::SupervisorCall::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:877
gem5::ArmISA::ArmFault::SynchPtyErrOnTranslTableWalkLL
@ SynchPtyErrOnTranslTableWalkLL
Definition: faults.hh:100
gem5::ArmISA::ArmFault::shortDescFaultSources
static uint8_t shortDescFaultSources[NumFaultSources]
Encodings of the fault sources when the short-desc.
Definition: faults.hh:125
gem5::ArmISA::DataAbort::sas
uint8_t sas
Definition: faults.hh:514
gem5::ArmISA::ArmFault::FaultVals::name
const FaultName name
Definition: faults.hh:168
gem5::ArmISA::SupervisorTrap
Definition: faults.hh:373
gem5::ArmISA::ArmFault::update
void update(ThreadContext *tc)
Definition: faults.cc:439
gem5::ArmISA::ArmFault::FaultVals::FaultVals
FaultVals(const FaultName &name_, const FaultOffset &offset_, const uint16_t &currELTOffset_, const uint16_t &currELHOffset_, const uint16_t &lowerEL64Offset_, const uint16_t &lowerEL32Offset_, const OperatingMode &nextMode_, const uint8_t &armPcOffset_, const uint8_t &thumbPcOffset_, const uint8_t &armPcElrOffset_, const uint8_t &thumbPcElrOffset_, const bool &hypTrappable_, const bool &abortDisable_, const bool &fiqDisable_, const ExceptionClass &ec_)
Definition: faults.hh:196
gem5::ArmISA::VirtualFastInterrupt
Definition: faults.hh:581
gem5::ArmISA::HypervisorTrap::machInst
ExtMachInst machInst
Definition: faults.hh:421
gem5::ArmISA::ArmFaultVals::offset64
FaultOffset offset64(ThreadContext *tc) override
Definition: faults.cc:990
gem5::ArmISA::ArmFault::getFaultVAddr
virtual bool getFaultVAddr(Addr &va) const
Definition: faults.hh:256
gem5::ArmISA::Watchpoint::cm
bool cm
Definition: faults.hh:647
gem5::ArmISA::SecureMonitorCall::iss
uint32_t iss() const override
Definition: faults.cc:919
gem5::ArmISA::UndefinedInstruction::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:840
gem5::ArmISA::AbortFault::iss
uint32_t iss() const override
Definition: faults.cc:1254
gem5::ArmISA::AbortFault::abortDisable
bool abortDisable(ThreadContext *tc) override
Definition: faults.cc:1224
gem5::ArmISA::UndefinedInstruction::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:817
gem5::ArmISA::ArmFault::FaultVals::offset
const FaultOffset offset
Definition: faults.hh:170
gem5::ArmISA::SupervisorTrap::overrideEc
ExceptionClass overrideEc
Definition: faults.hh:377
gem5::ArmISA::ArmFault::WPOINT_NOCM
@ WPOINT_NOCM
Definition: faults.hh:163
gem5::PowerISA::AlignmentFault
Definition: faults.hh:82
gem5::ArmISA::SupervisorCall::SupervisorCall
SupervisorCall(ExtMachInst _machInst, uint32_t _iss, ExceptionClass _overrideEc=EC_INVALID)
Definition: faults.hh:341
gem5::ArmISA::ArmFault::FaultVals::armPcOffset
const uint8_t armPcOffset
Definition: faults.hh:180
gem5::ArmISA::MISCREG_IFAR
@ MISCREG_IFAR
Definition: misc.hh:286
gem5::ArmISA::DataAbort::srt
uint8_t srt
Definition: faults.hh:516
gem5::ArmISA::ArmFault::FaultVals::lowerEL64Offset
const uint16_t lowerEL64Offset
Definition: faults.hh:175
gem5::ArmISA::VirtualInterrupt::VirtualInterrupt
VirtualInterrupt()
Definition: faults.cc:1510
gem5::ArmISA::ArmFault::ArmFault
ArmFault(ExtMachInst _machInst=0, uint32_t _iss=0)
Definition: faults.hh:214
gem5::ArmISA::DataAbort::annotate
void annotate(AnnotationIDs id, uint64_t val) override
Definition: faults.cc:1434
gem5::ArmISA::ArmFault::SF
@ SF
Definition: faults.hh:146
gem5::ArmISA::ArmFault::nextMode
virtual OperatingMode nextMode()=0
gem5::ArmISA::FastInterrupt::fiqDisable
bool fiqDisable(ThreadContext *tc) override
Definition: faults.cc:1544
gem5::ArmISA::SupervisorTrap::SupervisorTrap
SupervisorTrap(ExtMachInst _machInst, uint32_t _iss, ExceptionClass _overrideEc=EC_INVALID)
Definition: faults.hh:380
gem5::ArmISA::ArmFault::FaultVals::abortDisable
const bool abortDisable
Definition: faults.hh:189
gem5::ArmISA::DataAbort::cm
uint8_t cm
Definition: faults.hh:517
gem5::ArmISA::SecureMonitorTrap::SecureMonitorTrap
SecureMonitorTrap(ExtMachInst _machInst, uint32_t _iss, ExceptionClass _overrideEc=EC_INVALID)
Definition: faults.hh:398
gem5::ArmISA::MISCREG_HDFAR
@ MISCREG_HDFAR
Definition: misc.hh:289
null_static_inst.hh
gem5::ArmISA::AbortFault::isStage2
bool isStage2() const override
Definition: faults.hh:480
gem5::ArmISA::VirtualDataAbort::HFarIndex
static const MiscRegIndex HFarIndex
Definition: faults.hh:546
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::SoftwareBreakpoint::SoftwareBreakpoint
SoftwareBreakpoint(ExtMachInst _mach_inst, uint32_t _iss)
Definition: faults.cc:1616
gem5::ArmISA::PrefetchAbort::PrefetchAbort
PrefetchAbort(Addr _addr, uint8_t _source, bool _stage2=false, ArmFault::TranMethod _tranMethod=ArmFault::UnknownTran, ArmFault::DebugType _debug=ArmFault::NODEBUG)
Definition: faults.hh:493
gem5::ArmISA::SoftwareBreakpoint
System error (AArch64 only)
Definition: faults.hh:621
gem5::ArmISA::ArmFaultVals::offset
FaultOffset offset(ThreadContext *tc) override
Definition: faults.cc:970
gem5::ArmISA::ArmFault::AsynchPtyErrOnMemoryAccess
@ AsynchPtyErrOnMemoryAccess
Definition: faults.hh:110
gem5::ArmISA::PrefetchAbort
Definition: faults.hh:486
gem5::ArmISA::SoftwareStepFault::iss
uint32_t iss() const override
Definition: faults.cc:1779
gem5::ArmISA::PCAlignmentFault::PCAlignmentFault
PCAlignmentFault(Addr _faultPC)
Definition: faults.hh:594
gem5::ArmISA::MISCREG_DFSR
@ MISCREG_DFSR
Definition: misc.hh:268
gem5::ArmISA::HypervisorCall::ec
ExceptionClass ec(ThreadContext *tc) const override
Definition: faults.cc:957
gem5::ArmISA::MiscRegIndex
MiscRegIndex
Definition: misc.hh:59
gem5::ArmISA::HardwareBreakpoint::ec
ExceptionClass ec(ThreadContext *tc) const override
Definition: faults.cc:1650
gem5::ArmISA::ArmFaultVals::routeToMonitor
virtual bool routeToMonitor(ThreadContext *tc) const override
Definition: faults.hh:275
gem5::ArmISA::DataAbort::FsrIndex
static const MiscRegIndex FsrIndex
Definition: faults.hh:510
gem5::ArmISA::va
Bitfield< 8 > va
Definition: misc_types.hh:276
gem5::ArmISA::ArmFault::getFsr
virtual FSR getFsr(ThreadContext *tc) const
Definition: faults.hh:254
gem5::ArmISA::ArmFault::InstructionCacheMaintenance
@ InstructionCacheMaintenance
Definition: faults.hh:98
gem5::ArmISA::AbortFault::getFaultVAddr
bool getFaultVAddr(Addr &va) const override
Definition: faults.cc:1283
gem5::ArmISA::AbortFault::OVAddr
Addr OVAddr
Original virtual address.
Definition: faults.hh:450
gem5::ArmISA::ExceptionClass
ExceptionClass
Definition: types.hh:293
gem5::ArmISA::SoftwareStepFault::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1759
full_system.hh
gem5::FaultName
const typedef char * FaultName
Definition: faults.hh:53
gem5::ArmISA::ArmFault::getFaultAddrReg64
MiscRegIndex getFaultAddrReg64() const
Definition: faults.cc:382
gem5::ArmISA::HardwareBreakpoint::HardwareBreakpoint
HardwareBreakpoint(Addr _vaddr, uint32_t _iss)
Definition: faults.cc:1636
gem5::ArmISA::Reset::getVector
Addr getVector(ThreadContext *tc) override
Definition: faults.cc:771
gem5::ArmISA::AbortFault::srcEncoded
uint8_t srcEncoded
Definition: faults.hh:454
gem5::ArmISA::ArmFault
Definition: faults.hh:64
gem5::ArmISA::ArmFault::FaultVals::currELHOffset
const uint16_t currELHOffset
Definition: faults.hh:174
gem5::ArmISA::AbortFault::faultAddr
Addr faultAddr
The virtual address the fault occured at.
Definition: faults.hh:444
gem5::ArmISA::FaultOffset
Addr FaultOffset
Definition: faults.hh:60
gem5::ArmISA::ArmFault::FaultVals::fiqDisable
const bool fiqDisable
Definition: faults.hh:190
gem5::X86ISA::ExtMachInst
Definition: types.hh:206
gem5::ArmISA::ArmFault::aarch64FaultSources
static uint8_t aarch64FaultSources[NumFaultSources]
Encodings of the fault sources in AArch64 state.
Definition: faults.hh:130
gem5::ArmISA::SupervisorCall::overrideEc
ExceptionClass overrideEc
Definition: faults.hh:339
gem5::ArmISA::PrefetchAbort::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1327
gem5::ArmISA::EL0
@ EL0
Definition: types.hh:266
gem5::ArmISA::ArmFault::TranMethod
TranMethod
Definition: faults.hh:150
gem5::ArmISA::SupervisorCall::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:896
gem5::ArmISA::ArmFault::invoke64
void invoke64(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)
Definition: faults.cc:649
gem5::ArmISA::ArmFault::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:489
gem5::ArmISA::SupervisorTrap::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1046
gem5::ArmISA::DataAbort::isv
bool isv
Definition: faults.hh:513
gem5::ArmISA::Watchpoint::annotate
void annotate(AnnotationIDs id, uint64_t val) override
Definition: faults.cc:1726
gem5::ArmISA::SystemError
System error (AArch64 only)
Definition: faults.hh:610
gem5::ArmISA::AbortFault::isMMUFault
bool isMMUFault() const
Definition: faults.cc:1266
gem5::ArmISA::ArmFault::getVector
virtual Addr getVector(ThreadContext *tc)
Definition: faults.cc:311
gem5::ArmISA::ArmFault::isResetSPSR
bool isResetSPSR()
Definition: faults.hh:233
gem5::ArmISA::ArmFaultVals::name
FaultName name() const override
Definition: faults.hh:269
gem5::ArmISA::ArmFault::CM
@ CM
Definition: faults.hh:139
gem5::FaultBase
Definition: translation_gen.test.cc:48
gem5::ArmISA::Watchpoint::iss
uint32_t iss() const override
Definition: faults.cc:1693
gem5::ArmISA::FastInterrupt
Definition: faults.hh:571
gem5::ArmISA::SPAlignmentFault
Stack pointer alignment fault (AArch64 only)
Definition: faults.hh:602
gem5::ArmISA::AbortFault::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:1080
gem5::ArmISA::ArmFault::span
bool span
Definition: faults.hh:85
gem5::ArmISA::ArmFault::TranslationLL
@ TranslationLL
Definition: faults.hh:101
gem5::ArmISA::AbortFault::stage2
bool stage2
Definition: faults.hh:455
gem5::ArmISA::SecureMonitorCall::SecureMonitorCall
SecureMonitorCall(ExtMachInst _machInst)
Definition: faults.hh:360
gem5::ArmISA::SoftwareStepFault::SoftwareStepFault
SoftwareStepFault(ExtMachInst _mach_inst, bool is_ldx, bool stepped)
Definition: faults.cc:1750
misc.hh
gem5::ArmISA::ArmFault::WPOINT_CM
@ WPOINT_CM
Definition: faults.hh:162
gem5::ArmISA::ArmFaultVals::ec
ExceptionClass ec(ThreadContext *tc) const override
Definition: faults.hh:290
gem5::ArmISA::ArmFault::ec
virtual ExceptionClass ec(ThreadContext *tc) const =0
gem5::ArmISA::ArmFault::AnnotationIDs
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Definition: faults.hh:132
gem5::ArmISA::ArmFault::DebugType
DebugType
Definition: faults.hh:157
gem5::ArmISA::ArmFault::annotate
virtual void annotate(AnnotationIDs id, uint64_t val)
Definition: faults.hh:238
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gem5::ArmISA::ArmFault::TLBConflictAbort
@ TLBConflictAbort
Definition: faults.hh:107
gem5::ArmISA::ArmFault::AccessFlagLL
@ AccessFlagLL
Definition: faults.hh:102
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ExceptionClass ec(ThreadContext *tc) const override
Definition: faults.cc:1769
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uint32_t iss() const override
Definition: faults.cc:848
gem5::ArmISA::EC_INVALID
@ EC_INVALID
Definition: types.hh:295
gem5::ArmISA::FastInterrupt::routeToMonitor
bool routeToMonitor(ThreadContext *tc) const override
Definition: faults.cc:1514
gem5::ArmISA::ArmFault::S1PTW
@ S1PTW
Definition: faults.hh:134
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Definition: faults.hh:548
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Definition: faults.cc:789
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const OperatingMode nextMode
Definition: faults.hh:178
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Definition: faults.cc:938
gem5::ArmISA::ArmSev::invoke
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Definition: faults.cc:1795
gem5::ArmISA::ArmFault::toMode
OperatingMode toMode
Definition: faults.hh:77
gem5::ArmISA::ArmFault::routeToHyp
virtual bool routeToHyp(ThreadContext *tc) const
Definition: faults.hh:243
gem5::ArmISA::ArmFault::SRT
@ SRT
Definition: faults.hh:138
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Definition: faults.cc:1660
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Definition: faults.hh:515
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Definition: faults.cc:745
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Definition: faults.cc:1493
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Definition: faults.hh:451
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ExceptionClass ec(ThreadContext *tc) const override
Definition: faults.cc:1290
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bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1383
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Definition: faults.cc:945
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Definition: faults.hh:521
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bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1840
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Definition: faults.cc:1589
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Definition: faults.hh:67
gem5::ArmISA::ArmFault::armPcOffset
virtual uint8_t armPcOffset(bool isHyp)=0
gem5::ArmISA::SPAlignmentFault::routeToHyp
bool routeToHyp(ThreadContext *tc) const override
Definition: faults.cc:1578
gem5::ArmISA::ArmFault::fromMode
OperatingMode fromMode
Definition: faults.hh:76
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Definition: faults.hh:394
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ExceptionClass ec(ThreadContext *tc) const override
Definition: faults.cc:904
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::ArmISA::ArmFault::invoke32
void invoke32(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)
Definition: faults.cc:516
gem5::ArmISA::ArmFault::routeToMonitor
virtual bool routeToMonitor(ThreadContext *tc) const =0
gem5::ArmISA::IllegalInstSetStateFault::IllegalInstSetStateFault
IllegalInstSetStateFault()
Definition: faults.cc:1836
gem5::ArmISA::AbortFault::source
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Definition: faults.hh:453
gem5::ArmISA::ArmFault::isStage2
virtual bool isStage2() const
Definition: faults.hh:253
gem5::ArmISA::VirtualInterrupt
Definition: faults.hh:565
gem5::ArmISA::Interrupt
Definition: faults.hh:556
gem5::ArmISA::ArmFault::longDescFaultSources
static uint8_t longDescFaultSources[NumFaultSources]
Encodings of the fault sources when the long-desc.
Definition: faults.hh:128
gem5::ArmISA::AbortFault
Definition: faults.hh:435
gem5::ArmISA::ArmFault::SAS
@ SAS
Definition: faults.hh:136
gem5::ArmISA::DataAbort::HFarIndex
static const MiscRegIndex HFarIndex
Definition: faults.hh:512
gem5::ArmISA::SecureMonitorCall::vectorCatchFlag
uint32_t vectorCatchFlag() const override
Definition: faults.hh:370
gem5::ArmISA::ArmFault::UnknownTran
@ UnknownTran
Definition: faults.hh:154
gem5::ArmISA::OperatingMode
OperatingMode
Definition: types.hh:272
gem5::ArmISA::ArmFault::OVA
@ OVA
Definition: faults.hh:135
gem5::ArmISA::SoftwareStepFault::stepped
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Definition: faults.hh:663
gem5::ArmISA::AbortFault::s1ptw
bool s1ptw
Definition: faults.hh:456
gem5::ArmISA::VirtualFastInterrupt::VirtualFastInterrupt
VirtualFastInterrupt()
Definition: faults.cc:1555
gem5::ArmISA::SecureMonitorTrap::overrideEc
ExceptionClass overrideEc
Definition: faults.hh:395
gem5::ArmISA::ArmFaultVals::fiqDisable
bool fiqDisable(ThreadContext *tc) override
Definition: faults.hh:289
gem5::ArmISA::VirtualDataAbort::FsrIndex
static const MiscRegIndex FsrIndex
Definition: faults.hh:544
gem5::ArmISA::ArmFaultVals::iss
uint32_t iss() const override
Definition: faults.hh:291
gem5::ArmISA::Interrupt::abortDisable
bool abortDisable(ThreadContext *tc) override
Definition: faults.cc:1501
gem5::ArmISA::VirtualDataAbort::FarIndex
static const MiscRegIndex FarIndex
Definition: faults.hh:545
gem5::ArmISA::ExceptionLevel
ExceptionLevel
Definition: types.hh:264
gem5::ArmISA::Watchpoint::ec
ExceptionClass ec(ThreadContext *tc) const override
Definition: faults.cc:1741
gem5::ArmISA::AbortFault::tranMethod
ArmFault::TranMethod tranMethod
Definition: faults.hh:457
gem5::ArmISA::ArmFault::fiqDisable
virtual bool fiqDisable(ThreadContext *tc)=0
gem5::ArmISA::Watchpoint::write
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Definition: faults.hh:646
gem5::ArmISA::IllegalInstSetStateFault
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Definition: faults.hh:682
gem5::ArmISA::ArmFault::FaultVals::armPcElrOffset
const uint8_t armPcElrOffset
Definition: faults.hh:185

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