gem5  v22.0.0.1
static_register_manager_policy.cc
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31 
33 
34 #include "config/the_gpu_isa.hh"
35 #include "debug/GPURename.hh"
39 #include "gpu-compute/shader.hh"
41 #include "gpu-compute/wavefront.hh"
42 
43 namespace gem5
44 {
45 
47 {
48 }
49 
50 void
52 {
53 }
54 
55 int
57 {
58  panic_if((vgprIndex >= w->reservedVectorRegs)
59  || (w->reservedVectorRegs < 0),
60  "VGPR index %d is out of range: VGPR range=[0,%d]",
61  vgprIndex, w->reservedVectorRegs);
62 
63  // add the offset from where the VGPRs of the wavefront have been assigned
64  int physicalVgprIndex = w->startVgprIndex + vgprIndex;
65 
66  panic_if(!((w->startVgprIndex <= physicalVgprIndex) &&
67  (w->startVgprIndex + w->reservedVectorRegs - 1)
68  >= physicalVgprIndex),
69  "Invalid VGPR index %d\n", physicalVgprIndex);
70 
71  // calculate physical VGPR index
72  return physicalVgprIndex % w->computeUnit->vrf[w->simdId]->numRegs();
73 }
74 
75 int
77 {
78  panic_if(!((sgprIndex < w->reservedScalarRegs)
79  && (w->reservedScalarRegs > 0)),
80  "SGPR index %d is out of range: SGPR range=[0,%d]\n",
81  sgprIndex, w->reservedScalarRegs);
82 
83  // add the offset from where the SGPRs of the wavefront have been assigned
84  int physicalSgprIndex = w->startSgprIndex + sgprIndex;
85 
86  panic_if(!((w->startSgprIndex <= physicalSgprIndex) &&
87  (w->startSgprIndex + w->reservedScalarRegs - 1)
88  >= physicalSgprIndex),
89  "Invalid SGPR index %d\n", physicalSgprIndex);
90 
91  // calculate physical SGPR index
92  return physicalSgprIndex % w->computeUnit->srf[w->simdId]->numRegs();
93 }
94 
95 bool
97  int demandPerWf)
98 {
99  return cu->registerManager->vrfPoolMgrs[simdId]->
100  canAllocate(nWfs, demandPerWf);
101 }
102 
103 bool
105  int demandPerWf)
106 {
107  return cu->registerManager->srfPoolMgrs[simdId]->
108  canAllocate(nWfs, demandPerWf);
109 }
110 
111 void
113  int scalarDemand)
114 {
115  uint32_t allocatedSize = 0;
116  w->startVgprIndex = cu->registerManager->vrfPoolMgrs[w->simdId]->
117  allocateRegion(vectorDemand, &allocatedSize);
118  w->reservedVectorRegs = allocatedSize;
119  cu->vectorRegsReserved[w->simdId] += w->reservedVectorRegs;
121  "VRF[%d] has been overallocated %d > %d\n",
122  w->simdId, cu->vectorRegsReserved[w->simdId],
124 
125  if (scalarDemand) {
126  w->startSgprIndex = cu->registerManager->srfPoolMgrs[w->simdId]->
127  allocateRegion(scalarDemand, &allocatedSize);
128  w->reservedScalarRegs = allocatedSize;
129  cu->scalarRegsReserved[w->simdId] += w->reservedScalarRegs;
131  "SRF[%d] has been overallocated %d > %d\n",
132  w->simdId, cu->scalarRegsReserved[w->simdId],
134  }
135 }
136 
137 void
139 {
140  // free the vector registers of the completed wavefront
141  w->computeUnit->vectorRegsReserved[w->simdId] -= w->reservedVectorRegs;
142  // free the scalar registers of the completed wavefront
143  w->computeUnit->scalarRegsReserved[w->simdId] -= w->reservedScalarRegs;
144 
145  panic_if(w->computeUnit->vectorRegsReserved[w->simdId] < 0,
146  "Freeing VRF[%d] registers left %d registers reserved\n",
147  w->simdId,
148  w->computeUnit->vectorRegsReserved[w->simdId]);
149  panic_if(w->computeUnit->scalarRegsReserved[w->simdId] < 0,
150  "Freeing SRF[%d] registers left %d registers reserved\n",
151  w->simdId,
152  w->computeUnit->scalarRegsReserved[w->simdId]);
153 
154  // Current dynamic register allocation does not handle wraparound
155  int endIndex = w->startVgprIndex + w->reservedVectorRegs;
156 
157  w->computeUnit->registerManager->vrfPoolMgrs[w->simdId]->
158  freeRegion(w->startVgprIndex, endIndex);
159 
160  // mark/pre-mark all registers are not busy
161  for (int i = 0; i < w->reservedVectorRegs; i++) {
162  uint32_t physVgprIdx = mapVgpr(w, i);
163  w->computeUnit->vrf[w->simdId]->markReg(physVgprIdx, false);
164  }
165 
166  w->reservedVectorRegs = 0;
167  w->startVgprIndex = 0;
168 
169  endIndex = w->startSgprIndex + w->reservedScalarRegs;
170  w->computeUnit->registerManager->srfPoolMgrs[w->simdId]->
171  freeRegion(w->startSgprIndex, endIndex);
172 
173  // mark/pre-mark all registers are not busy
174  for (int i = 0; i < w->reservedScalarRegs; i++) {
175  uint32_t physSgprIdx = mapSgpr(w, i);
176  w->computeUnit->srf[w->simdId]->markReg(physSgprIdx, false);
177  }
178 
179  w->reservedScalarRegs = 0;
180  w->startSgprIndex = 0;
181 }
182 
183 } // namespace gem5
static_register_manager_policy.hh
shader.hh
gem5::ComputeUnit::numVecRegsPerSimd
int numVecRegsPerSimd
Definition: compute_unit.hh:371
gem5::StaticRegisterManagerPolicy::StaticRegisterManagerPolicy
StaticRegisterManagerPolicy()
Definition: static_register_manager_policy.cc:46
gem5::Wavefront
Definition: wavefront.hh:60
compute_unit.hh
gem5::StaticRegisterManagerPolicy::canAllocateVgprs
bool canAllocateVgprs(int simdId, int nWfs, int demandPerWf) override
Definition: static_register_manager_policy.cc:96
gem5::StaticRegisterManagerPolicy::mapVgpr
int mapVgpr(Wavefront *w, int vgprIndex) override
Definition: static_register_manager_policy.cc:56
gem5::VegaISA::w
Bitfield< 6 > w
Definition: pagetable.hh:59
gem5::StaticRegisterManagerPolicy::allocateRegisters
void allocateRegisters(Wavefront *w, int vectorDemand, int scalarDemand) override
Definition: static_register_manager_policy.cc:112
gem5::RegisterManager::vrfPoolMgrs
std::vector< PoolManager * > vrfPoolMgrs
Definition: register_manager.hh:80
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
wavefront.hh
gem5::StaticRegisterManagerPolicy::canAllocateSgprs
bool canAllocateSgprs(int simdId, int nWfs, int demandPerWf) override
Definition: static_register_manager_policy.cc:104
vector_register_file.hh
gem5::ComputeUnit::registerManager
RegisterManager * registerManager
Definition: compute_unit.hh:278
scalar_register_file.hh
gem5::RegisterManager::srfPoolMgrs
std::vector< PoolManager * > srfPoolMgrs
Definition: register_manager.hh:79
gem5::StaticRegisterManagerPolicy::freeRegisters
void freeRegisters(Wavefront *w) override
Definition: static_register_manager_policy.cc:138
gem5::RegisterManagerPolicy::cu
ComputeUnit * cu
Definition: register_manager_policy.hh:79
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:204
gem5::ComputeUnit::vectorRegsReserved
std::vector< int > vectorRegsReserved
Definition: compute_unit.hh:367
gem5::StaticRegisterManagerPolicy::exec
void exec() override
Definition: static_register_manager_policy.cc:51
gem5::ComputeUnit::scalarRegsReserved
std::vector< int > scalarRegsReserved
Definition: compute_unit.hh:369
gem5::ComputeUnit::numScalarRegsPerSimd
int numScalarRegsPerSimd
Definition: compute_unit.hh:373
pool_manager.hh
gem5::StaticRegisterManagerPolicy::mapSgpr
int mapSgpr(Wavefront *w, int sgprIndex) override
Definition: static_register_manager_policy.cc:76
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37

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