gem5  v21.1.0.2
static_register_manager_policy.cc
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2016 Advanced Micro Devices, Inc.
3  * All rights reserved.
4  *
5  * For use for simulation and test purposes only
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions are met:
9  *
10  * 1. Redistributions of source code must retain the above copyright notice,
11  * this list of conditions and the following disclaimer.
12  *
13  * 2. Redistributions in binary form must reproduce the above copyright notice,
14  * this list of conditions and the following disclaimer in the documentation
15  * and/or other materials provided with the distribution.
16  *
17  * 3. Neither the name of the copyright holder nor the names of its
18  * contributors may be used to endorse or promote products derived from this
19  * software without specific prior written permission.
20  *
21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31  * POSSIBILITY OF SUCH DAMAGE.
32  */
33 
35 
36 #include "config/the_gpu_isa.hh"
37 #include "debug/GPURename.hh"
41 #include "gpu-compute/shader.hh"
43 #include "gpu-compute/wavefront.hh"
44 
45 namespace gem5
46 {
47 
49 {
50 }
51 
52 void
54 {
55 }
56 
57 int
59 {
60  panic_if((vgprIndex >= w->reservedVectorRegs)
61  || (w->reservedVectorRegs < 0),
62  "VGPR index %d is out of range: VGPR range=[0,%d]",
63  vgprIndex, w->reservedVectorRegs);
64 
65  // add the offset from where the VGPRs of the wavefront have been assigned
66  int physicalVgprIndex = w->startVgprIndex + vgprIndex;
67 
68  panic_if(!((w->startVgprIndex <= physicalVgprIndex) &&
69  (w->startVgprIndex + w->reservedVectorRegs - 1)
70  >= physicalVgprIndex),
71  "Invalid VGPR index %d\n", physicalVgprIndex);
72 
73  // calculate physical VGPR index
74  return physicalVgprIndex % w->computeUnit->vrf[w->simdId]->numRegs();
75 }
76 
77 int
79 {
80  panic_if(!((sgprIndex < w->reservedScalarRegs)
81  && (w->reservedScalarRegs > 0)),
82  "SGPR index %d is out of range: SGPR range=[0,%d]\n",
83  sgprIndex, w->reservedScalarRegs);
84 
85  // add the offset from where the SGPRs of the wavefront have been assigned
86  int physicalSgprIndex = w->startSgprIndex + sgprIndex;
87 
88  panic_if(!((w->startSgprIndex <= physicalSgprIndex) &&
89  (w->startSgprIndex + w->reservedScalarRegs - 1)
90  >= physicalSgprIndex),
91  "Invalid SGPR index %d\n", physicalSgprIndex);
92 
93  // calculate physical SGPR index
94  return physicalSgprIndex % w->computeUnit->srf[w->simdId]->numRegs();
95 }
96 
97 bool
99  int demandPerWf)
100 {
101  return cu->registerManager->vrfPoolMgrs[simdId]->
102  canAllocate(nWfs, demandPerWf);
103 }
104 
105 bool
107  int demandPerWf)
108 {
109  return cu->registerManager->srfPoolMgrs[simdId]->
110  canAllocate(nWfs, demandPerWf);
111 }
112 
113 void
115  int scalarDemand)
116 {
117  uint32_t allocatedSize = 0;
118  w->startVgprIndex = cu->registerManager->vrfPoolMgrs[w->simdId]->
119  allocateRegion(vectorDemand, &allocatedSize);
120  w->reservedVectorRegs = allocatedSize;
121  cu->vectorRegsReserved[w->simdId] += w->reservedVectorRegs;
123  "VRF[%d] has been overallocated %d > %d\n",
124  w->simdId, cu->vectorRegsReserved[w->simdId],
126 
127  if (scalarDemand) {
128  w->startSgprIndex = cu->registerManager->srfPoolMgrs[w->simdId]->
129  allocateRegion(scalarDemand, &allocatedSize);
130  w->reservedScalarRegs = allocatedSize;
131  cu->scalarRegsReserved[w->simdId] += w->reservedScalarRegs;
133  "SRF[%d] has been overallocated %d > %d\n",
134  w->simdId, cu->scalarRegsReserved[w->simdId],
136  }
137 }
138 
139 void
141 {
142  // free the vector registers of the completed wavefront
143  w->computeUnit->vectorRegsReserved[w->simdId] -= w->reservedVectorRegs;
144  // free the scalar registers of the completed wavefront
145  w->computeUnit->scalarRegsReserved[w->simdId] -= w->reservedScalarRegs;
146 
147  panic_if(w->computeUnit->vectorRegsReserved[w->simdId] < 0,
148  "Freeing VRF[%d] registers left %d registers reserved\n",
149  w->simdId,
150  w->computeUnit->vectorRegsReserved[w->simdId]);
151  panic_if(w->computeUnit->scalarRegsReserved[w->simdId] < 0,
152  "Freeing SRF[%d] registers left %d registers reserved\n",
153  w->simdId,
154  w->computeUnit->scalarRegsReserved[w->simdId]);
155 
156  // Current dynamic register allocation does not handle wraparound
157  int endIndex = w->startVgprIndex + w->reservedVectorRegs;
158 
159  w->computeUnit->registerManager->vrfPoolMgrs[w->simdId]->
160  freeRegion(w->startVgprIndex, endIndex);
161 
162  // mark/pre-mark all registers are not busy
163  for (int i = 0; i < w->reservedVectorRegs; i++) {
164  uint32_t physVgprIdx = mapVgpr(w, i);
165  w->computeUnit->vrf[w->simdId]->markReg(physVgprIdx, false);
166  }
167 
168  w->reservedVectorRegs = 0;
169  w->startVgprIndex = 0;
170 
171  endIndex = w->startSgprIndex + w->reservedScalarRegs;
172  w->computeUnit->registerManager->srfPoolMgrs[w->simdId]->
173  freeRegion(w->startSgprIndex, endIndex);
174 
175  // mark/pre-mark all registers are not busy
176  for (int i = 0; i < w->reservedScalarRegs; i++) {
177  uint32_t physSgprIdx = mapSgpr(w, i);
178  w->computeUnit->srf[w->simdId]->markReg(physSgprIdx, false);
179  }
180 
181  w->reservedScalarRegs = 0;
182  w->startSgprIndex = 0;
183 }
184 
185 } // namespace gem5
static_register_manager_policy.hh
gem5::MipsISA::w
Bitfield< 0 > w
Definition: pra_constants.hh:281
shader.hh
gem5::ComputeUnit::numVecRegsPerSimd
int numVecRegsPerSimd
Definition: compute_unit.hh:373
gem5::StaticRegisterManagerPolicy::StaticRegisterManagerPolicy
StaticRegisterManagerPolicy()
Definition: static_register_manager_policy.cc:48
gem5::Wavefront
Definition: wavefront.hh:62
compute_unit.hh
gem5::StaticRegisterManagerPolicy::canAllocateVgprs
bool canAllocateVgprs(int simdId, int nWfs, int demandPerWf) override
Definition: static_register_manager_policy.cc:98
gem5::StaticRegisterManagerPolicy::mapVgpr
int mapVgpr(Wavefront *w, int vgprIndex) override
Definition: static_register_manager_policy.cc:58
gem5::StaticRegisterManagerPolicy::allocateRegisters
void allocateRegisters(Wavefront *w, int vectorDemand, int scalarDemand) override
Definition: static_register_manager_policy.cc:114
gem5::RegisterManager::vrfPoolMgrs
std::vector< PoolManager * > vrfPoolMgrs
Definition: register_manager.hh:82
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
wavefront.hh
gem5::StaticRegisterManagerPolicy::canAllocateSgprs
bool canAllocateSgprs(int simdId, int nWfs, int demandPerWf) override
Definition: static_register_manager_policy.cc:106
vector_register_file.hh
gem5::ComputeUnit::registerManager
RegisterManager * registerManager
Definition: compute_unit.hh:280
scalar_register_file.hh
gem5::RegisterManager::srfPoolMgrs
std::vector< PoolManager * > srfPoolMgrs
Definition: register_manager.hh:81
gem5::StaticRegisterManagerPolicy::freeRegisters
void freeRegisters(Wavefront *w) override
Definition: static_register_manager_policy.cc:140
gem5::RegisterManagerPolicy::cu
ComputeUnit * cu
Definition: register_manager_policy.hh:81
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:203
gem5::ComputeUnit::vectorRegsReserved
std::vector< int > vectorRegsReserved
Definition: compute_unit.hh:369
gem5::StaticRegisterManagerPolicy::exec
void exec() override
Definition: static_register_manager_policy.cc:53
gem5::ComputeUnit::scalarRegsReserved
std::vector< int > scalarRegsReserved
Definition: compute_unit.hh:371
gem5::ComputeUnit::numScalarRegsPerSimd
int numScalarRegsPerSimd
Definition: compute_unit.hh:375
pool_manager.hh
gem5::StaticRegisterManagerPolicy::mapSgpr
int mapSgpr(Wavefront *w, int sgprIndex) override
Definition: static_register_manager_policy.cc:78
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40

Generated on Tue Sep 21 2021 12:25:25 for gem5 by doxygen 1.8.17