gem5  v21.2.1.1
register_manager.hh
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31 
32 #ifndef __REGISTER_MANAGER_HH__
33 #define __REGISTER_MANAGER_HH__
34 
35 #include <cstdint>
36 #include <map>
37 #include <string>
38 #include <utility>
39 #include <vector>
40 
43 #include "sim/sim_object.hh"
44 #include "sim/stats.hh"
45 
46 namespace gem5
47 {
48 
49 class ComputeUnit;
50 class Wavefront;
51 
52 struct RegisterManagerParams;
53 
54 /*
55  * Rename stage.
56  */
57 class RegisterManager : public SimObject
58 {
59  public:
60  RegisterManager(const RegisterManagerParams &params);
62  void setParent(ComputeUnit *cu);
63  void exec();
64 
65  // lookup virtual to physical register translation
66  int mapVgpr(Wavefront* w, int vgprIndex);
67  int mapSgpr(Wavefront* w, int sgprIndex);
68 
69  // check if we can allocate registers
70  bool canAllocateVgprs(int simdId, int nWfs, int demandPerWf);
71  bool canAllocateSgprs(int simdId, int nWfs, int demandPerWf);
72 
73  // allocate registers
74  void allocateRegisters(Wavefront *w, int vectorDemand, int scalarDemand);
75 
76  // free all registers used by the WF
77  void freeRegisters(Wavefront *w);
78 
81 
82  private:
84 
86 
87  std::string _name;
88 };
89 
90 } // namespace gem5
91 
92 #endif // __REGISTER_MANAGER_HH__
gem5::MipsISA::w
Bitfield< 0 > w
Definition: pra_constants.hh:281
gem5::Wavefront
Definition: wavefront.hh:60
gem5::RegisterManager::setParent
void setParent(ComputeUnit *cu)
Definition: register_manager.cc:77
std::vector
STL vector class.
Definition: stl.hh:37
gem5::RegisterManager::vrfPoolMgrs
std::vector< PoolManager * > vrfPoolMgrs
Definition: register_manager.hh:80
gem5::RegisterManagerPolicy
Register Manager Policy abstract class.
Definition: register_manager_policy.hh:53
stats.hh
gem5::RegisterManager::mapSgpr
int mapSgpr(Wavefront *w, int sgprIndex)
Definition: register_manager.cc:102
gem5::ComputeUnit
Definition: compute_unit.hh:201
gem5::RegisterManager::freeRegisters
void freeRegisters(Wavefront *w)
Definition: register_manager.cc:129
gem5::SimObject::params
const Params & params() const
Definition: sim_object.hh:176
sim_object.hh
gem5::RegisterManager::srfPoolMgrs
std::vector< PoolManager * > srfPoolMgrs
Definition: register_manager.hh:79
gem5::SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:146
gem5::RegisterManager::policy
RegisterManagerPolicy * policy
Definition: register_manager.hh:83
gem5::RegisterManager::mapVgpr
int mapVgpr(Wavefront *w, int vgprIndex)
Definition: register_manager.cc:95
gem5::RegisterManager::exec
void exec()
Definition: register_manager.cc:71
gem5::RegisterManager::allocateRegisters
void allocateRegisters(Wavefront *w, int vectorDemand, int scalarDemand)
Definition: register_manager.cc:122
pool_manager.hh
gem5::RegisterManager::RegisterManager
RegisterManager(const RegisterManagerParams &params)
Definition: register_manager.cc:48
gem5::RegisterManager::canAllocateSgprs
bool canAllocateSgprs(int simdId, int nWfs, int demandPerWf)
Definition: register_manager.cc:115
gem5::RegisterManager
Definition: register_manager.hh:57
gem5::RegisterManager::_name
std::string _name
Definition: register_manager.hh:87
gem5::RegisterManager::~RegisterManager
~RegisterManager()
Definition: register_manager.cc:60
gem5::RegisterManager::canAllocateVgprs
bool canAllocateVgprs(int simdId, int nWfs, int demandPerWf)
Definition: register_manager.cc:109
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
register_manager_policy.hh
gem5::RegisterManager::computeUnit
ComputeUnit * computeUnit
Definition: register_manager.hh:85

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