gem5 v24.0.0.0
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register_manager.hh
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1/*
2 * Copyright (c) 2016, 2017 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright notice,
12 * this list of conditions and the following disclaimer in the documentation
13 * and/or other materials provided with the distribution.
14 *
15 * 3. Neither the name of the copyright holder nor the names of its
16 * contributors may be used to endorse or promote products derived from this
17 * software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32#ifndef __REGISTER_MANAGER_HH__
33#define __REGISTER_MANAGER_HH__
34
35#include <cstdint>
36#include <map>
37#include <string>
38#include <utility>
39#include <vector>
40
43#include "sim/sim_object.hh"
44#include "sim/stats.hh"
45
46namespace gem5
47{
48
49class ComputeUnit;
50class Wavefront;
51
52struct RegisterManagerParams;
53
54/*
55 * Rename stage.
56 */
58{
59 public:
60 RegisterManager(const RegisterManagerParams &params);
62 void setParent(ComputeUnit *cu);
63 void exec();
64
65 // lookup virtual to physical register translation
66 int mapVgpr(Wavefront* w, int vgprIndex);
67 int mapSgpr(Wavefront* w, int sgprIndex);
68
69 // check if we can allocate registers
70 bool canAllocateVgprs(int simdId, int nWfs, int demandPerWf);
71 bool canAllocateSgprs(int simdId, int nWfs, int demandPerWf);
72
73 // allocate registers
74 void allocateRegisters(Wavefront *w, int vectorDemand, int scalarDemand);
75
76 // free all registers used by the WF
78
81
82 private:
84
86
87 std::string _name;
88};
89
90} // namespace gem5
91
92#endif // __REGISTER_MANAGER_HH__
Register Manager Policy abstract class.
int mapVgpr(Wavefront *w, int vgprIndex)
RegisterManager(const RegisterManagerParams &params)
void allocateRegisters(Wavefront *w, int vectorDemand, int scalarDemand)
void freeRegisters(Wavefront *w)
std::vector< PoolManager * > vrfPoolMgrs
RegisterManagerPolicy * policy
int mapSgpr(Wavefront *w, int sgprIndex)
bool canAllocateSgprs(int simdId, int nWfs, int demandPerWf)
std::vector< PoolManager * > srfPoolMgrs
bool canAllocateVgprs(int simdId, int nWfs, int demandPerWf)
void setParent(ComputeUnit *cu)
Abstract superclass for simulation objects.
STL vector class.
Definition stl.hh:37
const Params & params() const
Bitfield< 0 > w
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36

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