gem5  v21.1.0.2
register_manager.hh
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33 
34 #ifndef __REGISTER_MANAGER_HH__
35 #define __REGISTER_MANAGER_HH__
36 
37 #include <cstdint>
38 #include <map>
39 #include <string>
40 #include <utility>
41 #include <vector>
42 
45 #include "sim/sim_object.hh"
46 #include "sim/stats.hh"
47 
48 namespace gem5
49 {
50 
51 class ComputeUnit;
52 class Wavefront;
53 
54 struct RegisterManagerParams;
55 
56 /*
57  * Rename stage.
58  */
59 class RegisterManager : public SimObject
60 {
61  public:
62  RegisterManager(const RegisterManagerParams &params);
64  void setParent(ComputeUnit *cu);
65  void exec();
66 
67  // lookup virtual to physical register translation
68  int mapVgpr(Wavefront* w, int vgprIndex);
69  int mapSgpr(Wavefront* w, int sgprIndex);
70 
71  // check if we can allocate registers
72  bool canAllocateVgprs(int simdId, int nWfs, int demandPerWf);
73  bool canAllocateSgprs(int simdId, int nWfs, int demandPerWf);
74 
75  // allocate registers
76  void allocateRegisters(Wavefront *w, int vectorDemand, int scalarDemand);
77 
78  // free all registers used by the WF
79  void freeRegisters(Wavefront *w);
80 
83 
84  private:
86 
88 
89  std::string _name;
90 };
91 
92 } // namespace gem5
93 
94 #endif // __REGISTER_MANAGER_HH__
gem5::MipsISA::w
Bitfield< 0 > w
Definition: pra_constants.hh:281
gem5::Wavefront
Definition: wavefront.hh:62
gem5::RegisterManager::setParent
void setParent(ComputeUnit *cu)
Definition: register_manager.cc:79
std::vector
STL vector class.
Definition: stl.hh:37
gem5::RegisterManager::vrfPoolMgrs
std::vector< PoolManager * > vrfPoolMgrs
Definition: register_manager.hh:82
gem5::RegisterManagerPolicy
Register Manager Policy abstract class.
Definition: register_manager_policy.hh:55
stats.hh
gem5::RegisterManager::mapSgpr
int mapSgpr(Wavefront *w, int sgprIndex)
Definition: register_manager.cc:104
gem5::ComputeUnit
Definition: compute_unit.hh:203
gem5::RegisterManager::freeRegisters
void freeRegisters(Wavefront *w)
Definition: register_manager.cc:131
gem5::SimObject::params
const Params & params() const
Definition: sim_object.hh:176
sim_object.hh
gem5::RegisterManager::srfPoolMgrs
std::vector< PoolManager * > srfPoolMgrs
Definition: register_manager.hh:81
gem5::SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:146
gem5::RegisterManager::policy
RegisterManagerPolicy * policy
Definition: register_manager.hh:85
gem5::RegisterManager::mapVgpr
int mapVgpr(Wavefront *w, int vgprIndex)
Definition: register_manager.cc:97
gem5::RegisterManager::exec
void exec()
Definition: register_manager.cc:73
gem5::RegisterManager::allocateRegisters
void allocateRegisters(Wavefront *w, int vectorDemand, int scalarDemand)
Definition: register_manager.cc:124
pool_manager.hh
gem5::RegisterManager::RegisterManager
RegisterManager(const RegisterManagerParams &params)
Definition: register_manager.cc:50
gem5::RegisterManager::canAllocateSgprs
bool canAllocateSgprs(int simdId, int nWfs, int demandPerWf)
Definition: register_manager.cc:117
gem5::RegisterManager
Definition: register_manager.hh:59
gem5::RegisterManager::_name
std::string _name
Definition: register_manager.hh:89
gem5::RegisterManager::~RegisterManager
~RegisterManager()
Definition: register_manager.cc:62
gem5::RegisterManager::canAllocateVgprs
bool canAllocateVgprs(int simdId, int nWfs, int demandPerWf)
Definition: register_manager.cc:111
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
register_manager_policy.hh
gem5::RegisterManager::computeUnit
ComputeUnit * computeUnit
Definition: register_manager.hh:87

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