locked_mem.hh

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/*
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 * Copyright (c) 2006 The Regents of The University of Michigan
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 * Authors: Steve Reinhardt
 */

#ifndef __ARCH_ALPHA_LOCKED_MEM_HH__
#define __ARCH_ALPHA_LOCKED_MEM_HH__

#include "arch/alpha/registers.hh"
#include "base/logging.hh"
#include "mem/packet.hh"
#include "mem/request.hh"

namespace AlphaISA {

template <class XC>
inline void
handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
{
    // If we see a snoop come into the CPU and we currently have an LLSC
    // operation pending we need to clear the lock flag if it is to the same
    // cache line.

    if (!xc->readMiscReg(MISCREG_LOCKFLAG))
        return;

    Addr locked_addr = xc->readMiscReg(MISCREG_LOCKADDR) & cacheBlockMask;
    Addr snoop_addr = pkt->getAddr() & cacheBlockMask;

    if (locked_addr == snoop_addr)
        xc->setMiscReg(MISCREG_LOCKFLAG, false);
}


template <class XC>
inline void
handleLockedRead(XC *xc, const RequestPtr &req)
{
    xc->setMiscReg(MISCREG_LOCKADDR, req->getPaddr() & ~0xf);
    xc->setMiscReg(MISCREG_LOCKFLAG, true);
}

template <class XC>
inline void
handleLockedSnoopHit(XC *xc)
{
}

template <class XC>
inline bool
handleLockedWrite(XC *xc, const RequestPtr &req, Addr cacheBlockMask)
{
    if (req->isUncacheable()) {
        // Funky Turbolaser mailbox access...don't update
        // result register (see stq_c in decoder.isa)
        req->setExtraData(2);
    } else {
        // standard store conditional
        bool lock_flag = xc->readMiscReg(MISCREG_LOCKFLAG);
        Addr lock_addr = xc->readMiscReg(MISCREG_LOCKADDR);
        if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) {
            // Lock flag not set or addr mismatch in CPU;
            // don't even bother sending to memory system
            req->setExtraData(0);
            xc->setMiscReg(MISCREG_LOCKFLAG, false);
            // the rest of this code is not architectural;
            // it's just a debugging aid to help detect
            // livelock by warning on long sequences of failed
            // store conditionals
            int stCondFailures = xc->readStCondFailures();
            stCondFailures++;
            xc->setStCondFailures(stCondFailures);
            if (stCondFailures % 100000 == 0) {
                warn("context %d: %d consecutive "
                     "store conditional failures\n",
                     xc->contextId(), stCondFailures);
            }

            // store conditional failed already, so don't issue it to mem
            return false;
        }
    }

    return true;
}

template <class XC>
inline void
globalClearExclusive(XC *xc)
{
    xc->getCpuPtr()->wakeup(xc->threadId());
}

} // namespace AlphaISA

#endif // __ARCH_ALPHA_LOCKED_MEM_HH__