rename_map.hh

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 * Copyright (c) 2004-2005 The Regents of The University of Michigan
 * Copyright (c) 2013 Advanced Micro Devices, Inc.
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 * Authors: Kevin Lim
 *          Steve Reinhardt
 */

#ifndef __CPU_O3_RENAME_MAP_HH__
#define __CPU_O3_RENAME_MAP_HH__

#include <iostream>
#include <utility>
#include <vector>

#include "arch/types.hh"
#include "config/the_isa.hh"
#include "cpu/o3/free_list.hh"
#include "cpu/o3/regfile.hh"
#include "cpu/reg_class.hh"
#include "enums/VecRegRenameMode.hh"

class SimpleRenameMap
{
  private:
    using Arch2PhysMap = std::vector<PhysRegIdPtr>;
    Arch2PhysMap map;
  public:
    using iterator = Arch2PhysMap::iterator;
    using const_iterator = Arch2PhysMap::const_iterator;
  private:

    SimpleFreeList *freeList;

    RegId zeroReg;

  public:

    SimpleRenameMap();

    ~SimpleRenameMap() {};

    void init(unsigned size, SimpleFreeList *_freeList, RegIndex _zeroReg);

    typedef std::pair<PhysRegIdPtr, PhysRegIdPtr> RenameInfo;

    RenameInfo rename(const RegId& arch_reg);

    PhysRegIdPtr lookup(const RegId& arch_reg) const
    {
        assert(arch_reg.flatIndex() <= map.size());
        return map[arch_reg.flatIndex()];
    }

    void setEntry(const RegId& arch_reg, PhysRegIdPtr phys_reg)
    {
        assert(arch_reg.flatIndex() <= map.size());
        map[arch_reg.flatIndex()] = phys_reg;
    }

    unsigned numFreeEntries() const { return freeList->numFreeRegs(); }

    iterator begin() { return map.begin(); }
    const_iterator begin() const { return map.begin(); }
    const_iterator cbegin() const { return map.cbegin(); }
    iterator end() { return map.end(); }
    const_iterator end() const { return map.end(); }
    const_iterator cend() const { return map.cend(); }
};

class UnifiedRenameMap
{
  private:
    static constexpr uint32_t NVecElems = TheISA::NumVecElemPerVecReg;
    using VecReg = TheISA::VecReg;
    using VecPredReg = TheISA::VecPredReg;

    SimpleRenameMap intMap;

    SimpleRenameMap floatMap;

    SimpleRenameMap ccMap;

    SimpleRenameMap vecMap;

    SimpleRenameMap vecElemMap;

    SimpleRenameMap predMap;

    using VecMode = Enums::VecRegRenameMode;
    VecMode vecMode;

    PhysRegFile *regFile;

  public:

    typedef SimpleRenameMap::RenameInfo RenameInfo;

    UnifiedRenameMap() : regFile(nullptr) {};

    ~UnifiedRenameMap() {};

    void init(PhysRegFile *_regFile,
              RegIndex _intZeroReg,
              RegIndex _floatZeroReg,
              UnifiedFreeList *freeList,
              VecMode _mode);

    RenameInfo rename(const RegId& arch_reg)
    {
        switch (arch_reg.classValue()) {
          case IntRegClass:
            return intMap.rename(arch_reg);
          case FloatRegClass:
            return floatMap.rename(arch_reg);
          case VecRegClass:
            assert(vecMode == Enums::Full);
            return vecMap.rename(arch_reg);
          case VecElemClass:
            assert(vecMode == Enums::Elem);
            return vecElemMap.rename(arch_reg);
          case VecPredRegClass:
            return predMap.rename(arch_reg);
          case CCRegClass:
            return ccMap.rename(arch_reg);
          case MiscRegClass:
            {
            // misc regs aren't really renamed, just remapped
            PhysRegIdPtr phys_reg = lookup(arch_reg);
            // Set the new register to the previous one to keep the same
            // mapping throughout the execution.
            return RenameInfo(phys_reg, phys_reg);
            }

          default:
            panic("rename rename(): unknown reg class %s\n",
                  arch_reg.className());
        }
    }

    PhysRegIdPtr lookup(const RegId& arch_reg) const
    {
        switch (arch_reg.classValue()) {
          case IntRegClass:
            return intMap.lookup(arch_reg);

          case FloatRegClass:
            return  floatMap.lookup(arch_reg);

          case VecRegClass:
            assert(vecMode == Enums::Full);
            return  vecMap.lookup(arch_reg);

          case VecElemClass:
            assert(vecMode == Enums::Elem);
            return  vecElemMap.lookup(arch_reg);

          case VecPredRegClass:
            return predMap.lookup(arch_reg);

          case CCRegClass:
            return ccMap.lookup(arch_reg);

          case MiscRegClass:
            // misc regs aren't really renamed, they keep the same
            // mapping throughout the execution.
            return regFile->getMiscRegId(arch_reg.flatIndex());

          default:
            panic("rename lookup(): unknown reg class %s\n",
                  arch_reg.className());
        }
    }

    void setEntry(const RegId& arch_reg, PhysRegIdPtr phys_reg)
    {
        switch (arch_reg.classValue()) {
          case IntRegClass:
            assert(phys_reg->isIntPhysReg());
            return intMap.setEntry(arch_reg, phys_reg);

          case FloatRegClass:
            assert(phys_reg->isFloatPhysReg());
            return floatMap.setEntry(arch_reg, phys_reg);

          case VecRegClass:
            assert(phys_reg->isVectorPhysReg());
            assert(vecMode == Enums::Full);
            return vecMap.setEntry(arch_reg, phys_reg);

          case VecElemClass:
            assert(phys_reg->isVectorPhysElem());
            assert(vecMode == Enums::Elem);
            return vecElemMap.setEntry(arch_reg, phys_reg);

          case VecPredRegClass:
            assert(phys_reg->isVecPredPhysReg());
            return predMap.setEntry(arch_reg, phys_reg);

          case CCRegClass:
            assert(phys_reg->isCCPhysReg());
            return ccMap.setEntry(arch_reg, phys_reg);

          case MiscRegClass:
            // Misc registers do not actually rename, so don't change
            // their mappings.  We end up here when a commit or squash
            // tries to update or undo a hardwired misc reg nmapping,
            // which should always be setting it to what it already is.
            assert(phys_reg == lookup(arch_reg));
            return;

          default:
            panic("rename setEntry(): unknown reg class %s\n",
                  arch_reg.className());
        }
    }

    unsigned numFreeEntries() const
    {
        return std::min(std::min(
                std::min(intMap.numFreeEntries(), floatMap.numFreeEntries()),
                vecMode == Enums::Full ? vecMap.numFreeEntries()
                                    : vecElemMap.numFreeEntries()),
                predMap.numFreeEntries());
    }

    unsigned numFreeIntEntries() const { return intMap.numFreeEntries(); }
    unsigned numFreeFloatEntries() const { return floatMap.numFreeEntries(); }
    unsigned numFreeVecEntries() const
    {
        return vecMode == Enums::Full
                ? vecMap.numFreeEntries()
                : vecElemMap.numFreeEntries();
    }
    unsigned numFreePredEntries() const { return predMap.numFreeEntries(); }
    unsigned numFreeCCEntries() const { return ccMap.numFreeEntries(); }

    bool canRename(uint32_t intRegs, uint32_t floatRegs, uint32_t vectorRegs,
                   uint32_t vecElemRegs, uint32_t vecPredRegs,
                   uint32_t ccRegs) const
    {
        return intRegs <= intMap.numFreeEntries() &&
            floatRegs <= floatMap.numFreeEntries() &&
            vectorRegs <= vecMap.numFreeEntries() &&
            vecElemRegs <= vecElemMap.numFreeEntries() &&
            vecPredRegs <= predMap.numFreeEntries() &&
            ccRegs <= ccMap.numFreeEntries();
    }
    void switchMode(VecMode newVecMode);

    void switchFreeList(UnifiedFreeList* freeList);

};

#endif //__CPU_O3_RENAME_MAP_HH__