Member ArmISA::TableWalker::doL1Descriptor ()

: check sctlr.ha (bit[17]) if Hardware Access Flag is enabled if set, do l1.Desc.setAp0() instead of generating AccessFlag0

Member ArmISA::TableWalker::doL2Descriptor ()

: check sctlr.ha (bit[17]) if Hardware Access Flag is enabled if set, do l2.Desc.setAp0() instead of generating AccessFlag0

Member ArmISA::TableWalker::walk (const RequestPtr &req, ThreadContext *tc, uint16_t asid, uint8_t _vmid, bool _isHyp, TLB::Mode mode, TLB::Translation *_trans, bool timing, bool functional, bool secure, TLB::ArmTranslationType tranType, bool _stage2Req)

These should be cached or grabbed from cached copies in the TLB, all these miscreg reads are expensive

Member BaseCPU::instCnt

unify this with the counters that cpus individually keep

Member BaseDynInst< Impl >::_readySrcRegIdx

: Not sure this should be here vs the derived class.

Member BaseDynInst< Impl >::doneTargCalc ()

: Actually use this instruction.

Member BaseDynInst< Impl >::renameSrcReg (int idx, PhysRegIdPtr renamed_src)

: add in whether or not the source register is ready.

Member BaseO3DynInst< Impl >::setIntRegOperand (const StaticInst *si, int idx, RegVal val) override

: Make results into arrays so they can handle multiple dest registers.

Member BaseTags::BaseTagStats::avgRefs

This should change to an average stat once we have them.

Member BPredUnit::update (ThreadID tid, Addr instPC, bool taken, void *bp_history, bool squashed, const StaticInstPtr &inst=StaticInst::nullStaticInstPtr, Addr corrTarget=MaxAddr)=0

Make this update flexible enough to handle a global predictor.

Member EventQueue::serviceEvents (Tick when)

this assert is a good bug catcher. I need to make it true again.

Member FullO3CPU< Impl >::syscall (ThreadID tid, Fault *fault)

: Determine if this needs to be virtual.

Member GicV2::readDistributor (ContextID ctx, Addr daddr, size_t resp_sz)

software generated interrupts and PPIs can't be configured in some ways

Member IdeDisk::doDmaDataRead ()

we need to figure out what the delay actually will be

Member IdeDisk::doDmaDataWrite ()

we need to figure out what the delay actually will be

Member IdeDisk::serialize (CheckpointOut &cp) const override

need to serialized chunk generator stuff!!

Member IdeDisk::startCommand ()

make this a scheduled event to simulate disk delay

Member IdeDisk::unserialize (CheckpointIn &cp) override

need to serialized chunk generator stuff!!

Member IdeDisk::updateState (DevAction_t action)

change this to a scheduled event to simulate disk delay

File inifile.hh

Change comments to match documentation style.

Class InstructionQueue< Impl >

: Make IQ able to handle multiple FU pools.

Member InstructionQueue< Impl >::commitToIEWDelay

: Make there be a distinction between the delays within IEW.

Member InstructionQueue< Impl >::listOrder

: Might be better to just move these entries around instead of creating new ones every time the position changes due to an instruction issuing. Not sure std::list supports this.

Member InstructionQueue< Impl >::numIssuedDist

: Need to create struct to track the entry time for each instruction.

Member InstructionQueue< Impl >::statFuBusy

: Need to create struct to track the ready time for each instruction.

Member LinuxAlphaSystem::initState ()

At some point we should change ev5.hh and the palcode to support 255 ASNs.

Member LSQUnit< Impl >::checkViolations (typename LoadQueue::iterator &loadIt, const DynInstPtr &inst)

in theory you only need to check an instruction that has executed however, there isn't a good way in the pipeline at the moment to check all instructions that will execute before the store writes back. Thus, like the implementation that came before it, we're overly conservative.

Member NSGigE::cpuIntrPost (Tick when)

this warning should be removed and the intrTick code should be fixed.

Member NSGigE::rxKick ()

in reality, we should be able to start processing the packet as it arrives, and not have to wait for the full packet ot be in the receive fifo.

do we want to schedule a future kick?

Member NSGigE::txKick ()

do we want to schedule a future kick?

Member O3ThreadContext< Impl >::dumpFuncProfile () override

: Implement.

Member ObjectMatch::domatch (const std::string &name) const

this should probably be changed to just use regular expression code

Member RefCounted::~RefCounted ()

Even if this were true, does it matter? Shouldn't the derived class indicate this? This only matters if we would ever choose to delete a "RefCounted *" which I doubt we'd ever do. We don't ever delete a "void *".

Member Sinic::Base::cpuIntrPost (Tick when)

this warning should be removed and the intrTick code should be fixed.

Member Sinic::Device::rxKick ()

do we want to schedule a future kick?

Member Sinic::Device::txKick ()

do we want to schedule a future kick?

Class SystemCounter

: implement memory-mapped controls

Member Trace::InstPBTrace::traceInst (ThreadContext *tc, StaticInstPtr si, TheISA::PCState pc)

if we are running multi-threaded I assume we'd need a lock here

Member TsunamiPChip::dmaAddr (const PciBusAddr &addr, Addr pci_addr) const override

Andrew says this needs to be fixed. What's wrong with it?

This currently is faked by just doing a direct read from memory, however, to be realistic, this needs to actually do a bus transaction. The process is explained in the tsunami documentation on page 10-12 and basically munges the address to look up a PTE from a table in memory and then uses that mapping to create an address for the SG page

Class UnifiedFreeList

: Give a better name to the base FP dependency.

Member VncServer::sendFrameBufferUpdate ()

this doesn't do anything smart and just sends the entire image

Member X86ISA::convX87XTagsToTags (uint8_t ftwx)

Reconstruct the correct state of stack positions instead of just valid/invalid.