|
gem5
v19.0.0.0
|
•All Classes Namespaces Files Functions Variables Typedefs Enumerations Enumerator Friends Macros Modules Pages
|
gem5
v19.0.0.0
|
This is exposed globally, independent of the ISA. More...
Namespaces | |
| ACPI | |
| ConditionTests | |
| IntelMP | |
| Kernel | |
| SMBios | |
Classes | |
| class | AlignmentCheck |
| class | BoundRange |
| class | Breakpoint |
| class | Cmos |
| struct | CpuidResult |
| class | DebugException |
| class | Decoder |
| class | DeviceNotAvailable |
| class | DivideError |
| class | DoubleFault |
| class | E820Entry |
| class | E820Table |
| struct | EmulEnv |
| class | ExternalInterrupt |
| struct | ExtMachInst |
| class | FpOp |
| Base classes for FpOps which provides a generateDisassembly method. More... | |
| class | GeneralProtection |
| class | GpuTLB |
| class | I386LinuxProcess |
| class | I386Process |
| class | I8042 |
| class | I82094AA |
| class | I8237 |
| class | I8254 |
| class | I8259 |
| class | InitInterrupt |
| struct | InstRegIndex |
| Class for register indices passed to instruction constructors. More... | |
| class | Interrupts |
| class | IntMasterPort |
| class | IntSlavePort |
| class | InvalidOpcode |
| class | InvalidTSS |
| class | ISA |
| class | LdStOp |
| Base class for load and store ops using one register. More... | |
| class | LdStSplitOp |
| Base class for load and store ops using two registers, we will call them split ops for this reason. More... | |
| class | LongModePTE |
| class | MachineCheck |
| class | MacroopBase |
| class | MediaOpBase |
| class | MediaOpImm |
| class | MediaOpReg |
| class | MemOp |
| Base class for memory ops. More... | |
| class | NonMaskableInterrupt |
| class | OverflowTrap |
| class | PageFault |
| class | PCState |
| class | ProcessInfo |
| class | RegOp |
| class | RegOpBase |
| Base classes for RegOps which provides a generateDisassembly method. More... | |
| class | RegOpImm |
| class | RemoteGDB |
| class | SecurityException |
| class | SegDescriptorLimit |
| class | SegmentNotPresent |
| class | SIMDFloatingPointFault |
| class | SoftwareInterrupt |
| class | Speaker |
| class | StackFault |
| class | StackTrace |
| class | StartupInterrupt |
| class | SystemManagementInterrupt |
| class | TLB |
| struct | TlbEntry |
| class | UnimpInstFault |
| class | Walker |
| class | X86_64LinuxProcess |
| class | X86_64Process |
| class | X86Abort |
| class | X86Fault |
| class | X86FaultBase |
| class | X86Interrupt |
| class | X86MicroopBase |
| class | X86Process |
| class | X86StaticInst |
| Base class for all X86 static instructions. More... | |
| class | X86Trap |
| class | X87FpExceptionPending |
Typedefs | |
| using | VecElem = ::DummyVecElem |
| using | VecReg = ::DummyVecReg |
| using | ConstVecReg = ::DummyConstVecReg |
| using | VecRegContainer = ::DummyVecRegContainer |
| using | VecPredReg = ::DummyVecPredReg |
| using | ConstVecPredReg = ::DummyConstVecPredReg |
| using | VecPredRegContainer = ::DummyVecPredRegContainer |
| typedef MsrMap::value_type | MsrVal |
| typedef std::unordered_map< Addr, MiscRegIndex > | MsrMap |
| typedef uint64_t | MachInst |
Functions | |
| uint64_t | stringToRegister (const char *str) |
| bool | doCpuid (ThreadContext *tc, uint32_t function, uint32_t index, CpuidResult &result) |
| ApicRegIndex | decodeAddr (Addr paddr) |
| BitUnion32 (TriggerIntMessage) Bitfield< 7 | |
| EndBitUnion (TriggerIntMessage) namespace DeliveryMode | |
| static PacketPtr | buildIntTriggerPacket (int id, TriggerIntMessage message) |
| static Fault | initiateMemRead (ExecContext *xc, Trace::InstRecord *traceData, Addr addr, unsigned dataSize, Request::Flags flags) |
| Initiate a read from memory in timing mode. More... | |
| static void | getMem (PacketPtr pkt, uint64_t &mem, unsigned dataSize, Trace::InstRecord *traceData) |
| template<typename T , size_t N> | |
| static void | getPackedMem (PacketPtr pkt, std::array< uint64_t, N > &mem, unsigned dataSize) |
| template<size_t N> | |
| static void | getMem (PacketPtr pkt, std::array< uint64_t, N > &mem, unsigned dataSize, Trace::InstRecord *traceData) |
| static Fault | readMemAtomic (ExecContext *xc, Trace::InstRecord *traceData, Addr addr, uint64_t &mem, unsigned dataSize, Request::Flags flags) |
| template<typename T , size_t N> | |
| static Fault | readPackedMemAtomic (ExecContext *xc, Addr addr, std::array< uint64_t, N > &mem, unsigned flags) |
| template<size_t N> | |
| static Fault | readMemAtomic (ExecContext *xc, Trace::InstRecord *traceData, Addr addr, std::array< uint64_t, N > &mem, unsigned dataSize, unsigned flags) |
| template<typename T , size_t N> | |
| static Fault | writePackedMem (ExecContext *xc, std::array< uint64_t, N > &mem, Addr addr, unsigned flags, uint64_t *res) |
| static Fault | writeMemTiming (ExecContext *xc, Trace::InstRecord *traceData, uint64_t mem, unsigned dataSize, Addr addr, Request::Flags flags, uint64_t *res) |
| template<size_t N> | |
| static Fault | writeMemTiming (ExecContext *xc, Trace::InstRecord *traceData, std::array< uint64_t, N > &mem, unsigned dataSize, Addr addr, unsigned flags, uint64_t *res) |
| static Fault | writeMemAtomic (ExecContext *xc, Trace::InstRecord *traceData, uint64_t mem, unsigned dataSize, Addr addr, Request::Flags flags, uint64_t *res) |
| template<size_t N> | |
| static Fault | writeMemAtomic (ExecContext *xc, Trace::InstRecord *traceData, std::array< uint64_t, N > &mem, unsigned dataSize, Addr addr, unsigned flags, uint64_t *res) |
| Cycles | handleIprRead (ThreadContext *tc, Packet *pkt) |
| Cycles | handleIprWrite (ThreadContext *tc, Packet *pkt) |
| BitUnion64 (VAddr) Bitfield< 20 | |
| EndBitUnion (VAddr) BitUnion64(PageTableEntry) Bitfield< 63 > nx | |
| EndBitUnion (PageTableEntry) template< int first | |
| void | m5PageFault (ThreadContext *tc) |
| static ApicRegIndex | APIC_IN_SERVICE (int index) |
| static ApicRegIndex | APIC_TRIGGER_MODE (int index) |
| static ApicRegIndex | APIC_INTERRUPT_REQUEST (int index) |
| BitUnion32 (InterruptCommandRegLow) Bitfield< 7 | |
| EndBitUnion (InterruptCommandRegLow) BitUnion32(InterruptCommandRegHigh) Bitfield< 31 | |
| static FloatRegIndex | FLOATREG_MMX (int index) |
| static FloatRegIndex | FLOATREG_FPR (int index) |
| static FloatRegIndex | FLOATREG_XMM_LOW (int index) |
| static FloatRegIndex | FLOATREG_XMM_HIGH (int index) |
| static FloatRegIndex | FLOATREG_MICROFP (int index) |
| static FloatRegIndex | FLOATREG_STACK (int index, int top) |
| BitUnion64 (X86IntReg) Bitfield< 63 | |
| EndBitUnion (X86IntReg) enum IntRegIndex | |
| static IntRegIndex | INTREG_MICRO (int index) |
| static IntRegIndex | INTREG_IMPLICIT (int index) |
| static IntRegIndex | INTREG_FOLDED (int index, int foldBit) |
| static bool | isValidMiscReg (int index) |
| static MiscRegIndex | MISCREG_CR (int index) |
| static MiscRegIndex | MISCREG_DR (int index) |
| static MiscRegIndex | MISCREG_MTRR_PHYS_BASE (int index) |
| static MiscRegIndex | MISCREG_MTRR_PHYS_MASK (int index) |
| static MiscRegIndex | MISCREG_MC_CTL (int index) |
| static MiscRegIndex | MISCREG_MC_STATUS (int index) |
| static MiscRegIndex | MISCREG_MC_ADDR (int index) |
| static MiscRegIndex | MISCREG_MC_MISC (int index) |
| static MiscRegIndex | MISCREG_PERF_EVT_SEL (int index) |
| static MiscRegIndex | MISCREG_PERF_EVT_CTR (int index) |
| static MiscRegIndex | MISCREG_IORR_BASE (int index) |
| static MiscRegIndex | MISCREG_IORR_MASK (int index) |
| static MiscRegIndex | MISCREG_SEG_SEL (int index) |
| static MiscRegIndex | MISCREG_SEG_BASE (int index) |
| static MiscRegIndex | MISCREG_SEG_EFF_BASE (int index) |
| static MiscRegIndex | MISCREG_SEG_LIMIT (int index) |
| static MiscRegIndex | MISCREG_SEG_ATTR (int index) |
| BitUnion64 (CCFlagBits) Bitfield< 11 > of | |
| A type to describe the condition code bits of the RFLAGS register, plus two flags, EZF and ECF, which are only visible to microcode. More... | |
| EndBitUnion (CCFlagBits) BitUnion64(RFLAGS) Bitfield< 21 > id | |
| RFLAGS. More... | |
| EndBitUnion (RFLAGS) BitUnion64(HandyM5Reg) Bitfield< 0 > mode | |
| EndBitUnion (HandyM5Reg) BitUnion64(CR0) Bitfield< 31 > pg | |
| Control registers. More... | |
| EndBitUnion (CR0) BitUnion64(CR2) Bitfield< 31 | |
| EndBitUnion (CR2) BitUnion64(CR3) Bitfield< 51 | |
| EndBitUnion (CR3) BitUnion64(CR4) Bitfield< 18 > osxsave | |
| EndBitUnion (CR4) BitUnion64(CR8) Bitfield< 3 | |
| EndBitUnion (CR8) BitUnion64(DR6) Bitfield< 0 > b0 | |
| EndBitUnion (DR6) BitUnion64(DR7) Bitfield< 0 > l0 | |
| EndBitUnion (DR7) BitUnion64(MTRRcap) Bitfield< 7 | |
| EndBitUnion (MTRRcap) BitUnion64(SysenterCS) Bitfield< 15 | |
| SYSENTER configuration registers. More... | |
| EndBitUnion (SysenterCS) BitUnion64(SysenterESP) Bitfield< 31 | |
| EndBitUnion (SysenterESP) BitUnion64(SysenterEIP) Bitfield< 31 | |
| EndBitUnion (SysenterEIP) BitUnion64(McgCap) Bitfield< 7 | |
| Global machine check registers. More... | |
| EndBitUnion (McgCap) BitUnion64(McgStatus) Bitfield< 0 > ripv | |
| EndBitUnion (McgStatus) BitUnion64(DebugCtlMsr) Bitfield< 0 > lbr | |
| EndBitUnion (DebugCtlMsr) BitUnion64(MtrrPhysBase) Bitfield< 7 | |
| EndBitUnion (MtrrPhysBase) BitUnion64(MtrrPhysMask) Bitfield< 11 > valid | |
| EndBitUnion (MtrrPhysMask) BitUnion64(MtrrFixed) EndBitUnion(MtrrFixed) BitUnion64(Pat) EndBitUnion(Pat) BitUnion64(MtrrDefType) Bitfield< 7 | |
| EndBitUnion (MtrrDefType) BitUnion64(McStatus) Bitfield< 15 | |
| Machine check. More... | |
| EndBitUnion (McStatus) BitUnion64(McCtl) EndBitUnion(McCtl) BitUnion64(Efer) Bitfield< 0 > sce | |
| EndBitUnion (Efer) BitUnion64(Star) Bitfield< 31 | |
| EndBitUnion (Star) BitUnion64(SfMask) Bitfield< 31 | |
| EndBitUnion (SfMask) BitUnion64(PerfEvtSel) Bitfield< 7 | |
| EndBitUnion (PerfEvtSel) BitUnion32(Syscfg) Bitfield< 18 > mfde | |
| EndBitUnion (Syscfg) BitUnion64(IorrBase) Bitfield< 3 > wr | |
| EndBitUnion (IorrBase) BitUnion64(IorrMask) Bitfield< 11 > v | |
| EndBitUnion (IorrMask) BitUnion64(Tom) Bitfield< 51 | |
| EndBitUnion (Tom) BitUnion64(VmCrMsr) Bitfield< 0 > dpd | |
| EndBitUnion (VmCrMsr) BitUnion64(IgnneMsr) Bitfield< 0 > ignne | |
| EndBitUnion (IgnneMsr) BitUnion64(SmmCtlMsr) Bitfield< 0 > dismiss | |
| EndBitUnion (SmmCtlMsr) BitUnion64(SegSelector) Bitfield< 63 | |
| Segment Selector. More... | |
| EndBitUnion (SegSelector) class SegDescriptorBase | |
| Segment Descriptors. More... | |
| BitUnion64 (SegDescriptor) Bitfield< 63 | |
| SubBitUnion (type, 43, 40) Bitfield< 43 > codeOrData | |
| EndSubBitUnion (type) EndBitUnion(SegDescriptor) BitUnion64(TSSlow) Bitfield< 63 | |
| TSS Descriptor (long mode - 128 bits) the lower 64 bits. More... | |
| EndBitUnion (TSShigh) BitUnion64(SegAttr) Bitfield< 1 | |
| EndBitUnion (SegAttr) BitUnion64(GateDescriptor) Bitfield< 63 | |
| EndBitUnion (GateDescriptor) BitUnion64(GateDescriptorLow) Bitfield< 63 | |
| Long Mode Gate Descriptor. More... | |
| EndBitUnion (GateDescriptorLow) BitUnion64(GateDescriptorHigh) Bitfield< 31 | |
| EndBitUnion (GateDescriptorHigh) BitUnion64(GDTR) EndBitUnion(GDTR) BitUnion64(IDTR) EndBitUnion(IDTR) BitUnion64(LDTR) EndBitUnion(LDTR) BitUnion64(TR) EndBitUnion(TR) BitUnion64(LocalApicBase) Bitfield< 51 | |
| Descriptor-Table Registers. More... | |
| const MsrMap | msrMap (msrMapData, msrMapData+msrMapSize) |
| bool | msrAddrToIndex (MiscRegIndex ®Num, Addr addr) |
| Find and return the misc reg corresponding to an MSR address. More... | |
| static int32_t | readSymbol (ThreadContext *tc, const std::string name) |
| void | installSegDesc (ThreadContext *tc, SegmentRegIndex seg, SegDescriptor desc, bool longmode) |
| BitUnion8 (LegacyPrefixVector) Bitfield< 7 | |
| EndBitUnion (LegacyPrefixVector) BitUnion8(ModRM) Bitfield< 7 | |
| EndBitUnion (ModRM) BitUnion8(Sib) Bitfield< 7 | |
| EndBitUnion (Sib) BitUnion8(Rex) Bitfield< 6 > present | |
| EndBitUnion (Rex) BitUnion8(Vex2Of3) Bitfield< 7 > r | |
| EndBitUnion (Vex2Of3) BitUnion8(Vex3Of3) Bitfield< 7 > w | |
| EndBitUnion (Vex3Of3) BitUnion8(Vex2Of2) Bitfield< 7 > r | |
| EndBitUnion (Vex2Of2) BitUnion8(VexInfo) Bitfield< 6 | |
| EndBitUnion (VexInfo) enum OpcodeType | |
| static const char * | opcodeTypeToStr (OpcodeType type) |
| BitUnion8 (Opcode) Bitfield< 7 | |
| EndBitUnion (Opcode) BitUnion8(OperatingMode) Bitfield< 3 > mode | |
| EndBitUnion (OperatingMode) enum X86Mode | |
| static std::ostream & | operator<< (std::ostream &os, const ExtMachInst &emi) |
| static bool | operator== (const ExtMachInst &emi1, const ExtMachInst &emi2) |
| uint64_t | getArgument (ThreadContext *tc, int &number, uint16_t size, bool fp) |
| void | copyMiscRegs (ThreadContext *src, ThreadContext *dest) |
| void | copyRegs (ThreadContext *src, ThreadContext *dest) |
| void | skipFunction (ThreadContext *tc) |
| uint64_t | getRFlags (ThreadContext *tc) |
| Reconstruct the rflags register from the internal gem5 register state. More... | |
| void | setRFlags (ThreadContext *tc, uint64_t val) |
| Set update the rflags register and internal gem5 state. More... | |
| uint8_t | convX87TagsToXTags (uint16_t ftw) |
| Convert an x87 tag word to abridged tag format. More... | |
| uint16_t | convX87XTagsToTags (uint8_t ftwx) |
| Convert an x87 xtag word to normal tags format. More... | |
| uint16_t | genX87Tags (uint16_t ftw, uint8_t top, int8_t spm) |
| Generate and updated x87 tag register after a push/pop operation. More... | |
| double | loadFloat80 (const void *mem) |
| Load an 80-bit float from memory and convert it to double. More... | |
| void | storeFloat80 (void *mem, double value) |
| Convert and store a double as an 80-bit float. More... | |
| PCState | buildRetPC (const PCState &curPC, const PCState &callPC) |
| static bool | inUserMode (ThreadContext *tc) |
| void | advancePC (PCState &pc, const StaticInstPtr &inst) |
| uint64_t | getExecutingAsid (ThreadContext *tc) |
| uint64_t | getDoubleBits (double val) |
| Extract the bit string representing a double value. More... | |
| Addr | vtophys (Addr vaddr) |
| Addr | vtophys (ThreadContext *tc, Addr vaddr) |
| static Addr | x86IOAddress (const uint32_t port) |
| static Addr | x86PciConfigAddress (const uint32_t addr) |
| static Addr | x86LocalAPICAddress (const uint8_t id, const uint16_t addr) |
| static Addr | x86InterruptAddress (const uint8_t id, const uint16_t addr) |
| template<class T > | |
| PacketPtr | buildIntPacket (Addr addr, T payload) |
Variables | |
| static const int | vendorStringSize = 13 |
| static const char | vendorString [vendorStringSize] = "M5 Simulator" |
| static const int | nameStringSize = 48 |
| static const char | nameString [nameStringSize] = "Fake M5 x86_64 CPU" |
| const uint8_t | CS = CSOverride |
| const uint8_t | DS = DSOverride |
| const uint8_t | ES = ESOverride |
| const uint8_t | FS = FSOverride |
| const uint8_t | GS = GSOverride |
| const uint8_t | SS = SSOverride |
| const uint8_t | OO = OperandSizeOverride |
| const uint8_t | AO = AddressSizeOverride |
| const uint8_t | LO = Lock |
| const uint8_t | RE = Rep |
| const uint8_t | RN = Repne |
| const uint8_t | RX = RexPrefix |
| const uint8_t | V2 = Vex2Prefix |
| const uint8_t | V3 = Vex3Prefix |
| const StaticInstPtr | badMicroop |
| destination | |
| Bitfield< 15, 8 > | vector |
| Bitfield< 18, 16 > | deliveryMode |
| Bitfield< 19 > | destMode |
| Bitfield< 20 > | level |
| Bitfield< 21 > | trigger |
| static const Addr | TriggerIntOffset = 0 |
| const ByteOrder | GuestByteOrder = LittleEndianByteOrder |
| const Addr | PageShift = 12 |
| const Addr | PageBytes = ULL(1) << PageShift |
| const bool | HasUnalignedMemAcc = true |
| const bool | CurThreadInfoImplemented = false |
| const int | CurThreadInfoReg = -1 |
| const Request::FlagsType M5_VAR_USED | SegmentFlagMask = mask(4) |
| const int | FlagShift = 4 |
| longl1 | |
| Bitfield< 29, 21 > | longl2 |
| Bitfield< 38, 30 > | longl3 |
| Bitfield< 47, 39 > | longl4 |
| Bitfield< 20, 12 > | pael1 |
| Bitfield< 29, 21 > | pael2 |
| Bitfield< 31, 30 > | pael3 |
| Bitfield< 21, 12 > | norml1 |
| Bitfield< 31, 22 > | norml2 |
| Bitfield< 51, 12 > | base |
| Bitfield< 11, 9 > | avl |
| Bitfield< 8 > | g |
| Bitfield< 7 > | ps |
| Bitfield< 6 > | d |
| Bitfield< 5 > | a |
| Bitfield< 4 > | pcd |
| Bitfield< 3 > | pwt |
| Bitfield< 2 > | u |
| Bitfield< 1 > | w |
| Bitfield< 0 > | p |
| const int | NumMiscRegs = NUM_MISCREGS |
| const int | NumIntArchRegs = NUM_INTREGS |
| const int | NumIntRegs = NumIntArchRegs + NumMicroIntRegs + NumImplicitIntRegs |
| const int | NumCCRegs = NUM_CCREGS |
| const int | NumFloatRegs |
| const int | NumVecRegs = 1 |
| const int | NumVecPredRegs = 1 |
| const int | ZeroReg = NUM_INTREGS |
| const int | StackPointerReg = INTREG_RSP |
| const int | ReturnAddressReg = 0 |
| const int | ReturnValueReg = INTREG_RAX |
| const int | FramePointerReg = INTREG_RBP |
| const int | SyscallPseudoReturnReg = INTREG_RDX |
| constexpr unsigned | NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg |
| constexpr size_t | VecRegSizeBytes = ::DummyVecRegSizeBytes |
| constexpr size_t | VecPredRegSizeBits = ::DummyVecPredRegSizeBits |
| constexpr bool | VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr |
| Bitfield< 12 > | deliveryStatus |
| Bitfield< 19, 18 > | destShorthand |
| R | |
| SignedBitfield< 63, 0 > | SR |
| Bitfield< 31, 0 > | E |
| SignedBitfield< 31, 0 > | SE |
| Bitfield< 15, 0 > | X |
| SignedBitfield< 15, 0 > | SX |
| Bitfield< 15, 8 > | H |
| SignedBitfield< 15, 8 > | SH |
| Bitfield< 7, 0 > | L |
| SignedBitfield< 7, 0 > | SL |
| static const IntRegIndex | IntFoldBit = (IntRegIndex)(1 << 6) |
| const uint32_t | cfofMask = CFBit | OFBit |
| const uint32_t | ccFlagMask = PFBit | AFBit | ZFBit | SFBit |
| Bitfield< 7 > | sf |
| Bitfield< 6 > | zf |
| Bitfield< 5 > | ezf |
| Bitfield< 4 > | af |
| Bitfield< 3 > | ecf |
| Bitfield< 2 > | pf |
| Bitfield< 0 > | cf |
| Bitfield< 20 > | vip |
| Bitfield< 19 > | vif |
| Bitfield< 18 > | ac |
| Bitfield< 17 > | vm |
| Bitfield< 16 > | rf |
| Bitfield< 14 > | nt |
| Bitfield< 13, 12 > | iopl |
| Bitfield< 11 > | of |
| Bitfield< 10 > | df |
| Bitfield< 9 > | intf |
| Bitfield< 8 > | tf |
| Bitfield< 3, 1 > | submode |
| Bitfield< 5, 4 > | cpl |
| Bitfield< 6 > | paging |
| Bitfield< 7 > | prot |
| Bitfield< 9, 8 > | defOp |
| Bitfield< 11, 10 > | altOp |
| Bitfield< 13, 12 > | defAddr |
| Bitfield< 15, 14 > | altAddr |
| Bitfield< 17, 16 > | stack |
| Bitfield< 30 > | cd |
| Bitfield< 29 > | nw |
| Bitfield< 18 > | am |
| Bitfield< 16 > | wp |
| Bitfield< 5 > | ne |
| Bitfield< 4 > | et |
| Bitfield< 3 > | ts |
| Bitfield< 2 > | em |
| Bitfield< 1 > | mp |
| Bitfield< 0 > | pe |
| legacy | |
| longPdtb | |
| Bitfield< 31, 12 > | pdtb |
| Bitfield< 31, 5 > | paePdtb |
| Bitfield< 16 > | fsgsbase |
| Bitfield< 10 > | osxmmexcpt |
| Bitfield< 9 > | osfxsr |
| Bitfield< 8 > | pce |
| Bitfield< 7 > | pge |
| Bitfield< 6 > | mce |
| Bitfield< 5 > | pae |
| Bitfield< 4 > | pse |
| Bitfield< 3 > | de |
| Bitfield< 2 > | tsd |
| Bitfield< 1 > | pvi |
| Bitfield< 0 > | vme |
| tpr | |
| Bitfield< 1 > | b1 |
| Bitfield< 2 > | b2 |
| Bitfield< 3 > | b3 |
| Bitfield< 13 > | bd |
| Bitfield< 14 > | bs |
| Bitfield< 15 > | bt |
| Bitfield< 1 > | g0 |
| Bitfield< 2 > | l1 |
| Bitfield< 3 > | g1 |
| Bitfield< 4 > | l2 |
| Bitfield< 5 > | g2 |
| Bitfield< 6 > | l3 |
| Bitfield< 7 > | g3 |
| Bitfield< 8 > | le |
| Bitfield< 9 > | ge |
| Bitfield< 13 > | gd |
| Bitfield< 17, 16 > | rw0 |
| Bitfield< 19, 18 > | len0 |
| Bitfield< 21, 20 > | rw1 |
| Bitfield< 23, 22 > | len1 |
| Bitfield< 25, 24 > | rw2 |
| Bitfield< 27, 26 > | len2 |
| Bitfield< 29, 28 > | rw3 |
| Bitfield< 31, 30 > | len3 |
| vcnt | |
| Bitfield< 8 > | fix |
| Bitfield< 10 > | wc |
| targetCS | |
| targetESP | |
| targetEIP | |
| count | |
| Bitfield< 8 > | MCGCP |
| Bitfield< 1 > | eipv |
| Bitfield< 2 > | mcip |
| Bitfield< 1 > | btf |
| Bitfield< 2 > | pb0 |
| Bitfield< 3 > | pb1 |
| Bitfield< 4 > | pb2 |
| Bitfield< 5 > | pb3 |
| type | |
| Bitfield< 51, 12 > | physbase |
| Bitfield< 51, 12 > | physmask |
| Bitfield< 10 > | fe |
| Bitfield< 11 > | e |
| mcaErrorCode | |
| Bitfield< 31, 16 > | modelSpecificCode |
| Bitfield< 56, 32 > | otherInfo |
| Bitfield< 57 > | pcc |
| Bitfield< 58 > | addrv |
| Bitfield< 59 > | miscv |
| Bitfield< 60 > | en |
| Bitfield< 61 > | uc |
| Bitfield< 62 > | over |
| Bitfield< 63 > | val |
| Bitfield< 8 > | lme |
| Bitfield< 10 > | lma |
| Bitfield< 11 > | nxe |
| Bitfield< 12 > | svme |
| Bitfield< 14 > | ffxsr |
| targetEip | |
| Bitfield< 47, 32 > | syscallCsAndSs |
| Bitfield< 63, 48 > | sysretCsAndSs |
| mask | |
| eventMask | |
| Bitfield< 15, 8 > | unitMask |
| Bitfield< 16 > | usr |
| Bitfield< 17 > | os |
| Bitfield< 19 > | pc |
| Bitfield< 20 > | intEn |
| Bitfield< 23 > | inv |
| Bitfield< 31, 24 > | counterMask |
| Bitfield< 19 > | mfdm |
| Bitfield< 20 > | mvdm |
| Bitfield< 21 > | tom2 |
| Bitfield< 4 > | rd |
| physAddr | |
| Bitfield< 1 > | rInit |
| Bitfield< 2 > | disA20M |
| Bitfield< 1 > | enter |
| Bitfield< 2 > | smiCycle |
| Bitfield< 3 > | exit |
| Bitfield< 4 > | rsmCycle |
| esi | |
| Bitfield< 15, 3 > | si |
| Bitfield< 2 > | ti |
| Bitfield< 1, 0 > | rpl |
| baseHigh | |
| Bitfield< 39, 16 > | baseLow |
| Bitfield< 54 > | b |
| Bitfield< 53 > | l |
| Bitfield< 51, 48 > | limitHigh |
| Bitfield< 15, 0 > | limitLow |
| BitfieldType< SegDescriptorLimit > | limit |
| Bitfield< 46, 45 > | dpl |
| Bitfield< 44 > | s |
| Bitfield< 42 > | c |
| Bitfield< 41 > | r |
| Bitfield< 2 > | unusable |
| Bitfield< 3 > | defaultSize |
| Bitfield< 4 > | longMode |
| Bitfield< 6 > | granularity |
| Bitfield< 7 > | present |
| Bitfield< 12 > | writable |
| Bitfield< 13 > | readable |
| Bitfield< 14 > | expandDown |
| Bitfield< 15 > | system |
| offsetHigh | |
| Bitfield< 15, 0 > | offsetLow |
| Bitfield< 31, 16 > | selector |
| Bitfield< 35, 32 > | IST |
| offset | |
| Bitfield< 11 > | enable |
| Bitfield< 8 > | bsp |
| const MsrMap::value_type | msrMapData [] |
| static const unsigned | msrMapSize = sizeof(msrMapData) / sizeof(msrMapData[0]) |
| const MsrMap | msrMap |
| Map between MSR addresses and their corresponding misc registers. More... | |
| const uint64_t | syscallCodeVirtAddr = 0xffff800000000000 |
| const uint64_t | GDTVirtAddr = 0xffff800000001000 |
| const uint64_t | IDTVirtAddr = 0xffff800000002000 |
| const uint64_t | TSSVirtAddr = 0xffff800000003000 |
| const uint64_t | TSSPhysAddr = 0x63000 |
| const uint64_t | ISTVirtAddr = 0xffff800000004000 |
| const uint64_t | PFHandlerVirtAddr = 0xffff800000005000 |
| const uint64_t | MMIORegionVirtAddr = 0xffffc90000000000 |
| const uint64_t | MMIORegionPhysAddr = 0xffff0000 |
| decodeVal | |
| Bitfield< 7 > | repne |
| Bitfield< 6 > | rep |
| Bitfield< 5 > | lock |
| Bitfield< 4 > | op |
| Bitfield< 3 > | addr |
| Bitfield< 2, 0 > | seg |
| mod | |
| Bitfield< 5, 3 > | reg |
| Bitfield< 2, 0 > | rm |
| scale | |
| Bitfield< 5, 3 > | index |
| Bitfield< 1 > | x |
| Bitfield< 4, 0 > | m |
| Bitfield< 6, 3 > | v |
| top5 | |
| Bitfield< 2, 0 > | bottom3 |
| const int | NumMicroIntRegs = 16 |
| const int | NumImplicitIntRegs = 6 |
| const int | NumMMXRegs = 8 |
| const int | NumXMMRegs = 16 |
| const int | NumMicroFpRegs = 8 |
| const int | NumCRegs = 16 |
| const int | NumDRegs = 8 |
| const int | NumSegments = 6 |
| const int | NumSysSegments = 4 |
| const Addr | IntAddrPrefixMask = ULL(0xffffffff00000000) |
| const Addr | IntAddrPrefixCPUID = ULL(0x100000000) |
| const Addr | IntAddrPrefixMSR = ULL(0x200000000) |
| const Addr | IntAddrPrefixIO = ULL(0x300000000) |
| const Addr | PhysAddrPrefixIO = ULL(0x8000000000000000) |
| const Addr | PhysAddrPrefixPciConfig = ULL(0xC000000000000000) |
| const Addr | PhysAddrPrefixLocalAPIC = ULL(0x2000000000000000) |
| const Addr | PhysAddrPrefixInterrupts = ULL(0xA000000000000000) |
| const Addr | PhysAddrAPICRangeSize = 1 << 12 |
This is exposed globally, independent of the ISA.
| using X86ISA::ConstVecPredReg = typedef ::DummyConstVecPredReg |
Definition at line 107 of file registers.hh.
| using X86ISA::ConstVecReg = typedef ::DummyConstVecReg |
Definition at line 100 of file registers.hh.
| typedef uint64_t X86ISA::MachInst |
| typedef std::unordered_map<Addr, MiscRegIndex> X86ISA::MsrMap |
| typedef MsrMap::value_type X86ISA::MsrVal |
| using X86ISA::VecElem = typedef ::DummyVecElem |
Definition at line 98 of file registers.hh.
| using X86ISA::VecPredReg = typedef ::DummyVecPredReg |
Definition at line 106 of file registers.hh.
| using X86ISA::VecPredRegContainer = typedef ::DummyVecPredRegContainer |
Definition at line 108 of file registers.hh.
| using X86ISA::VecReg = typedef ::DummyVecReg |
Definition at line 99 of file registers.hh.
| using X86ISA::VecRegContainer = typedef ::DummyVecRegContainer |
Definition at line 101 of file registers.hh.
| enum X86ISA::ApicRegIndex |
| enum X86ISA::CCRegIndex |
| enum X86ISA::CondFlagBit |
| Enumerator | |
|---|---|
| FP_Reg_Base | |
| CC_Reg_Base | |
| Misc_Reg_Base | |
| Max_Reg_Index | |
Definition at line 69 of file registers.hh.
| enum X86ISA::FlagBit |
| Enumerator | |
|---|---|
| CPL0FlagBit | |
| AddrSizeFlagBit | |
| StoreCheck | |
Definition at line 53 of file ldstflags.hh.
| enum X86ISA::MediaFlag |
| Enumerator | |
|---|---|
| MediaMultHiOp | |
| MediaSignedOp | |
| MediaScalarOp | |
Definition at line 38 of file micromediaop.hh.
| enum X86ISA::MiscRegIndex |
| enum X86ISA::Prefixes |
| enum X86ISA::RFLAGBit |
Definition at line 45 of file segment.hh.
| enum X86ISA::SizeType |
| Enumerator | |
|---|---|
| NoImm | |
| NI | |
| ByteImm | |
| BY | |
| WordImm | |
| WO | |
| DWordImm | |
| DW | |
| QWordImm | |
| QW | |
| OWordImm | |
| OW | |
| VWordImm | |
| VW | |
| ZWordImm | |
| ZW | |
| Enter | |
| EN | |
| Pointer | |
| PO | |
Definition at line 169 of file decoder_tables.cc.
| Enumerator | |
|---|---|
| M5_AT_SYSINFO | |
| M5_AT_SYSINFO_EHDR | |
Definition at line 55 of file process.hh.
| enum X86ISA::X86SubMode |
| enum X86ISA::X87StatusBit |
|
inline |
Definition at line 79 of file utility.hh.
References StaticInst::advancePC().
|
inlinestatic |
Definition at line 75 of file apic.hh.
References APIC_IN_SERVICE_BASE, and index.
Referenced by decodeAddr(), and X86ISA::Interrupts::setReg().
|
inlinestatic |
Definition at line 87 of file apic.hh.
References APIC_INTERRUPT_REQUEST_BASE, BitUnion32(), deliveryMode, destMode, index, and vector.
Referenced by decodeAddr(), and X86ISA::Interrupts::setReg().
|
inlinestatic |
Definition at line 81 of file apic.hh.
References APIC_TRIGGER_MODE_BASE, and index.
Referenced by decodeAddr(), X86ISA::Interrupts::readReg(), and X86ISA::Interrupts::setReg().
| X86ISA::BitUnion32 | ( | TriggerIntMessage | ) |
Referenced by APIC_INTERRUPT_REQUEST().
| X86ISA::BitUnion32 | ( | InterruptCommandRegLow | ) |
| X86ISA::BitUnion64 | ( | X86IntReg | ) |
| X86ISA::BitUnion64 | ( | VAddr | ) |
Referenced by MISCREG_SEG_ATTR(), X86ISA::SegDescriptorLimit::setter(), and X86ISA::TlbEntry::size().
| X86ISA::BitUnion64 | ( | CCFlagBits | ) |
A type to describe the condition code bits of the RFLAGS register, plus two flags, EZF and ECF, which are only visible to microcode.
| X86ISA::BitUnion64 | ( | SegDescriptor | ) |
| X86ISA::BitUnion8 | ( | LegacyPrefixVector | ) |
Referenced by opcodeTypeToStr().
| X86ISA::BitUnion8 | ( | Opcode | ) |
Definition at line 87 of file intdev.hh.
References addr, Packet::allocate(), Request::intMasterId, Packet::setRaw(), Request::UNCACHEABLE, and MemCmd::WriteReq.
Referenced by buildIntTriggerPacket().
|
inlinestatic |
Definition at line 81 of file intmessage.hh.
References addr, buildIntPacket(), and x86InterruptAddress().
Referenced by X86ISA::Interrupts::setReg(), and X86ISA::I82094AA::signalInterrupt().
Definition at line 51 of file utility.hh.
References ArmISA::fp, getArgument(), and X86ISA::PCState::uEnd().
| uint8_t X86ISA::convX87TagsToXTags | ( | uint16_t | ftw | ) |
Convert an x87 tag word to abridged tag format.
Convert from the x87 tag representation to the tag abridged representation used in the FXSAVE area. The classic format uses 2 bits per stack position to indicate if a position is valid, zero, special, or empty. The abridged format only stores whether a position is empty or not.
| ftw | Tag word in classic x87 format. |
Definition at line 150 of file utility.cc.
References ArmISA::i.
Referenced by getDoubleBits(), and updateKvmStateFPUCommon().
| uint16_t X86ISA::convX87XTagsToTags | ( | uint8_t | ftwx | ) |
Convert an x87 xtag word to normal tags format.
Convert from the abridged x87 tag representation used in the FXSAVE area to a full x87 tag. The classic format uses 2 bits per stack position to indicate if a position is valid, zero, special, or empty. The abridged format only stores whether a position is empty or not.
| ftwx | Tag word in the abridged format. |
Definition at line 175 of file utility.cc.
References ArmISA::i.
Referenced by getDoubleBits(), and updateThreadContextFPUCommon().
| void X86ISA::copyMiscRegs | ( | ThreadContext * | src, |
| ThreadContext * | dest | ||
| ) |
Definition at line 75 of file utility.cc.
References BaseTLB::flushAll(), ThreadContext::getDTBPtr(), ThreadContext::getITBPtr(), ArmISA::i, isValidMiscReg(), MISCREG_TSC, NUM_MISCREGS, ThreadContext::readMiscReg(), ThreadContext::readMiscRegNoEffect(), ThreadContext::setMiscReg(), and ThreadContext::setMiscRegNoEffect().
Referenced by copyRegs(), and inUserMode().
| void X86ISA::copyRegs | ( | ThreadContext * | src, |
| ThreadContext * | dest | ||
| ) |
Definition at line 96 of file utility.cc.
References copyMiscRegs(), ArmISA::i, NumCCRegs, NumFloatRegs, NumIntRegs, ThreadContext::pcState(), ThreadContext::readCCRegFlat(), ThreadContext::readFloatRegFlat(), ThreadContext::readIntRegFlat(), ThreadContext::setCCRegFlat(), ThreadContext::setFloatRegFlat(), and ThreadContext::setIntRegFlat().
Referenced by X86Linux::archClone(), and inUserMode().
| ApicRegIndex X86ISA::decodeAddr | ( | Addr | paddr | ) |
Definition at line 83 of file interrupts.cc.
References APIC_ARBITRATION_PRIORITY, APIC_CURRENT_COUNT, APIC_DESTINATION_FORMAT, APIC_DIVIDE_CONFIGURATION, APIC_EOI, APIC_ERROR_STATUS, APIC_ID, APIC_IN_SERVICE(), APIC_INITIAL_COUNT, APIC_INTERRUPT_COMMAND_HIGH, APIC_INTERRUPT_COMMAND_LOW, APIC_INTERRUPT_REQUEST(), APIC_LOGICAL_DESTINATION, APIC_LVT_ERROR, APIC_LVT_LINT0, APIC_LVT_LINT1, APIC_LVT_PERFORMANCE_MONITORING_COUNTERS, APIC_LVT_THERMAL_SENSOR, APIC_LVT_TIMER, APIC_PROCESSOR_PRIORITY, APIC_SPURIOUS_INTERRUPT_VECTOR, APIC_TASK_PRIORITY, APIC_TRIGGER_MODE(), APIC_VERSION, mask, and panic.
Referenced by X86ISA::Interrupts::read(), and X86ISA::Interrupts::write().
| bool X86ISA::doCpuid | ( | ThreadContext * | tc, |
| uint32_t | function, | ||
| uint32_t | index, | ||
| CpuidResult & | result | ||
| ) |
Definition at line 89 of file cpuid.cc.
References APMInfo, bits(), ExtendedFeatures, FamilyModelStepping, FamilyModelSteppingBrandFeatures, L1CacheAndTLB, L2L3CacheAndL2TLB, LongModeAddressSize, NameString1, NameString2, NameString3, nameStringSize, NumExtendedCpuidFuncs, NumStandardCpuidFuncs, offset, stringToRegister(), VendorAndLargestExtFunc, VendorAndLargestStdFunc, and warn.
Referenced by X86ISA::CpuidResult::CpuidResult(), and X86KvmCPU::updateCPUID().
| X86ISA::EndBitUnion | ( | TriggerIntMessage | ) |
Definition at line 51 of file intmessage.hh.
References ArmISA::mode.
| X86ISA::EndBitUnion | ( | X86IntReg | ) |
Definition at line 61 of file int.hh.
References ArmISA::INTREG_R10, ArmISA::INTREG_R11, ArmISA::INTREG_R12, ArmISA::INTREG_R13, ArmISA::INTREG_R14, ArmISA::INTREG_R15, ArmISA::INTREG_R8, ArmISA::INTREG_R9, ArmISA::INTREG_SP, and ArmISA::NUM_INTREGS.
| X86ISA::EndBitUnion | ( | LegacyPrefixVector | ) |
| X86ISA::EndBitUnion | ( | ModRM | ) |
| X86ISA::EndBitUnion | ( | Sib | ) |
| X86ISA::EndBitUnion | ( | InterruptCommandRegLow | ) |
| X86ISA::EndBitUnion | ( | Rex | ) |
| X86ISA::EndBitUnion | ( | Vex2Of3 | ) |
| X86ISA::EndBitUnion | ( | Vex3Of3 | ) |
| X86ISA::EndBitUnion | ( | VAddr | ) |
| X86ISA::EndBitUnion | ( | Vex2Of2 | ) |
| X86ISA::EndBitUnion | ( | PageTableEntry | ) |
| X86ISA::EndBitUnion | ( | Opcode | ) |
| X86ISA::EndBitUnion | ( | CCFlagBits | ) |
RFLAGS.
| X86ISA::EndBitUnion | ( | RFLAGS | ) |
| X86ISA::EndBitUnion | ( | HandyM5Reg | ) |
Control registers.
| X86ISA::EndBitUnion | ( | CR0 | ) |
| X86ISA::EndBitUnion | ( | CR2 | ) |
| X86ISA::EndBitUnion | ( | CR3 | ) |
| X86ISA::EndBitUnion | ( | CR4 | ) |
| X86ISA::EndBitUnion | ( | CR8 | ) |
| X86ISA::EndBitUnion | ( | DR6 | ) |
| X86ISA::EndBitUnion | ( | DR7 | ) |
| X86ISA::EndBitUnion | ( | MTRRcap | ) |
SYSENTER configuration registers.
| X86ISA::EndBitUnion | ( | SysenterCS | ) |
| X86ISA::EndBitUnion | ( | SysenterESP | ) |
| X86ISA::EndBitUnion | ( | SysenterEIP | ) |
Global machine check registers.
| X86ISA::EndBitUnion | ( | McgCap | ) |
| X86ISA::EndBitUnion | ( | McgStatus | ) |
| X86ISA::EndBitUnion | ( | DebugCtlMsr | ) |
| X86ISA::EndBitUnion | ( | MtrrPhysBase | ) |
| X86ISA::EndBitUnion | ( | MtrrPhysMask | ) |
| X86ISA::EndBitUnion | ( | MtrrDefType | ) |
Machine check.
| X86ISA::EndBitUnion | ( | McStatus | ) |
| X86ISA::EndBitUnion | ( | Efer | ) |
| X86ISA::EndBitUnion | ( | Star | ) |
| X86ISA::EndBitUnion | ( | SfMask | ) |
| X86ISA::EndBitUnion | ( | PerfEvtSel | ) |
| X86ISA::EndBitUnion | ( | Syscfg | ) |
| X86ISA::EndBitUnion | ( | IorrBase | ) |
| X86ISA::EndBitUnion | ( | IorrMask | ) |
| X86ISA::EndBitUnion | ( | Tom | ) |
| X86ISA::EndBitUnion | ( | VmCrMsr | ) |
| X86ISA::EndBitUnion | ( | IgnneMsr | ) |
| X86ISA::EndBitUnion | ( | SmmCtlMsr | ) |
Segment Selector.
| X86ISA::EndBitUnion | ( | SegSelector | ) |
Segment Descriptors.
Definition at line 865 of file misc.hh.
References base, bits(), and replaceBits().
| X86ISA::EndBitUnion | ( | TSShigh | ) |
| X86ISA::EndBitUnion | ( | SegAttr | ) |
| X86ISA::EndBitUnion | ( | GateDescriptor | ) |
Long Mode Gate Descriptor.
| X86ISA::EndBitUnion | ( | GateDescriptorLow | ) |
| X86ISA::EndBitUnion | ( | GateDescriptorHigh | ) |
Descriptor-Table Registers.
Task Register Local APIC Base Register
| X86ISA::EndSubBitUnion | ( | type | ) |
TSS Descriptor (long mode - 128 bits) the lower 64 bits.
TSS Descriptor (long mode - 128 bits) the upper 64 bits.
|
inlinestatic |
Definition at line 125 of file float.hh.
References FLOATREG_FPR_BASE, and index.
Referenced by FLOATREG_STACK(), updateKvmStateFPUCommon(), and updateThreadContextFPUCommon().
|
inlinestatic |
Definition at line 143 of file float.hh.
References FLOATREG_MICROFP_BASE, and index.
|
inlinestatic |
Definition at line 119 of file float.hh.
References FLOATREG_MMX_BASE, and index.
Referenced by Trace::X86NativeTrace::ThreadState::update().
|
inlinestatic |
Definition at line 149 of file float.hh.
References FLOATREG_FPR().
Referenced by X86ISA::ISA::flattenFloatIndex().
|
inlinestatic |
Definition at line 137 of file float.hh.
References FLOATREG_XMM_BASE.
Referenced by updateKvmStateFPUCommon(), and updateThreadContextFPUCommon().
|
inlinestatic |
Definition at line 131 of file float.hh.
References FLOATREG_XMM_BASE, and index.
Referenced by updateKvmStateFPUCommon(), and updateThreadContextFPUCommon().
| uint16_t X86ISA::genX87Tags | ( | uint16_t | ftw, |
| uint8_t | top, | ||
| int8_t | spm | ||
| ) |
Generate and updated x87 tag register after a push/pop operation.
| ftw | Current value of the FTW register. |
| top | Current x87 TOP value. |
| spm | Stack displacement. |
Definition at line 196 of file utility.cc.
References ArmISA::i.
Referenced by getDoubleBits().
| uint64_t X86ISA::getArgument | ( | ThreadContext * | tc, |
| int & | number, | ||
| uint16_t | size, | ||
| bool | fp | ||
| ) |
Definition at line 53 of file utility.cc.
References ArmISA::INTREG_R8, ArmISA::INTREG_R9, panic, and ThreadContext::readIntReg().
Referenced by buildRetPC().
|
inline |
Extract the bit string representing a double value.
Definition at line 123 of file utility.hh.
References convX87TagsToXTags(), convX87XTagsToTags(), genX87Tags(), loadFloat80(), mem, and storeFloat80().
|
inline |
Definition at line 85 of file utility.hh.
References getRFlags(), setRFlags(), and val.
|
static |
Definition at line 54 of file memhelpers.hh.
References Packet::getLE(), panic, and Trace::InstRecord::setData().
|
static |
Definition at line 88 of file memhelpers.hh.
References mem, panic, and Trace::InstRecord::setData().
|
static |
Definition at line 79 of file memhelpers.hh.
References Packet::getLE(), and ArmISA::i.
| uint64_t X86ISA::getRFlags | ( | ThreadContext * | tc | ) |
Reconstruct the rflags register from the internal gem5 register state.
gem5 stores rflags in several different registers to avoid pipeline dependencies. In order to get the true rflags value, we can't simply read the value of MISCREG_RFLAGS. Instead, we need to read out various state from microcode registers and merge that with MISCREG_RFLAGS.
| tc | Thread context to read rflags from. |
Definition at line 118 of file utility.cc.
References CCREG_CFOF, CCREG_DF, CCREG_ZAPS, MISCREG_RFLAGS, ThreadContext::readCCReg(), and ThreadContext::readMiscRegNoEffect().
Referenced by getExecutingAsid(), and X86KvmCPU::updateKvmStateRegs().
|
inline |
Definition at line 60 of file mmapped_ipr.hh.
References addr, data, PseudoInst::decodeAddrOffset(), Packet::getAddr(), Packet::getSize(), ThreadContext::getSystemPtr(), htole(), index, System::m5opRange(), mask, offset, ThreadContext::readMiscReg(), Packet::setData(), and Packet::setLE().
|
inline |
Definition at line 81 of file mmapped_ipr.hh.
References addr, data, PseudoInst::decodeAddrOffset(), Packet::getAddr(), Packet::getSize(), ThreadContext::getSystemPtr(), htole(), index, letoh(), System::m5opRange(), mask, offset, ThreadContext::readMiscRegNoEffect(), ThreadContext::setMiscReg(), and Packet::writeData().
|
static |
Initiate a read from memory in timing mode.
Definition at line 47 of file memhelpers.hh.
References ExecContext::initiateMemRead().
| void X86ISA::installSegDesc | ( | ThreadContext * | tc, |
| SegmentRegIndex | seg, | ||
| SegDescriptor | desc, | ||
| bool | longmode | ||
| ) |
Definition at line 63 of file system.cc.
References ArmISA::attr, MISCREG_SEG_ATTR(), MISCREG_SEG_BASE(), MISCREG_SEG_EFF_BASE(), MISCREG_SEG_LIMIT(), SEGMENT_REG_FS, SEGMENT_REG_GS, SEGMENT_REG_TSL, ThreadContext::setMiscReg(), and SYS_SEGMENT_REG_TR.
Referenced by X86System::initState(), and X86ISA::X86_64Process::initState().
|
inlinestatic |
|
inlinestatic |
Definition at line 162 of file int.hh.
References index, and NumMicroIntRegs.
|
inlinestatic |
Definition at line 156 of file int.hh.
References index.
Referenced by X86ISA::X86FaultBase::invoke().
|
inlinestatic |
Definition at line 62 of file utility.hh.
References copyMiscRegs(), copyRegs(), FullSystem, MISCREG_M5_REG, ThreadContext::readMiscRegNoEffect(), and skipFunction().
|
inlinestatic |
Definition at line 404 of file misc.hh.
References MISCREG_CR0, MISCREG_CR1, MISCREG_CR15, MISCREG_CR4, MISCREG_CR8, and NUM_MISCREGS.
Referenced by copyMiscRegs(), X86ISA::ISA::readMiscRegNoEffect(), and X86ISA::ISA::setMiscRegNoEffect().
| double X86ISA::loadFloat80 | ( | const void * | mem | ) |
Load an 80-bit float from memory and convert it to double.
| mem | Pointer to an 80-bit float. |
Definition at line 216 of file utility.cc.
Referenced by dumpFpuCommon(), getDoubleBits(), and updateThreadContextFPUCommon().
| void X86ISA::m5PageFault | ( | ThreadContext * | tc | ) |
Definition at line 48 of file pseudo_inst.cc.
References DPRINTF, Process::fixupStackFault(), ThreadContext::getProcessPtr(), ThreadContext::getVirtProxy(), MipsISA::is, ISTVirtAddr, MISCREG_CR2, p, PageBytes, panic, PortProxy::readBlob(), and ThreadContext::readMiscReg().
Referenced by PseudoInst::pseudoInst().
|
inlinestatic |
Definition at line 413 of file misc.hh.
References index, MISCREG_CR_BASE, and NumCRegs.
|
inlinestatic |
Definition at line 420 of file misc.hh.
References index, MISCREG_DR_BASE, and NumDRegs.
|
inlinestatic |
Definition at line 491 of file misc.hh.
References index, MISCREG_IORR_BASE_BASE, and MISCREG_IORR_BASE_END.
|
inlinestatic |
Definition at line 499 of file misc.hh.
References index, MISCREG_IORR_MASK_BASE, and MISCREG_IORR_MASK_END.
|
inlinestatic |
Definition at line 459 of file misc.hh.
References index, MISCREG_MC_ADDR_BASE, and MISCREG_MC_ADDR_END.
|
inlinestatic |
Definition at line 443 of file misc.hh.
References index, MISCREG_MC_CTL_BASE, and MISCREG_MC_CTL_END.
|
inlinestatic |
Definition at line 467 of file misc.hh.
References index, MISCREG_MC_MISC_BASE, and MISCREG_MC_MISC_END.
|
inlinestatic |
Definition at line 451 of file misc.hh.
References index, MISCREG_MC_STATUS_BASE, and MISCREG_MC_STATUS_END.
|
inlinestatic |
Definition at line 427 of file misc.hh.
References index, MISCREG_MTRR_PHYS_BASE_BASE, and MISCREG_MTRR_PHYS_BASE_END.
|
inlinestatic |
Definition at line 435 of file misc.hh.
References index, MISCREG_MTRR_PHYS_MASK_BASE, and MISCREG_MTRR_PHYS_MASK_END.
|
inlinestatic |
Definition at line 483 of file misc.hh.
References index, MISCREG_PERF_EVT_CTR_BASE, and MISCREG_PERF_EVT_CTR_END.
|
inlinestatic |
Definition at line 475 of file misc.hh.
References index, MISCREG_PERF_EVT_SEL_BASE, and MISCREG_PERF_EVT_SEL_END.
|
inlinestatic |
Definition at line 535 of file misc.hh.
References BitUnion64(), index, MISCREG_SEG_ATTR_BASE, NUM_SEGMENTREGS, and of.
Referenced by X86ISA::X86_64Process::initState(), X86ISA::I386Process::initState(), installSegDesc(), X86ISA::InitInterrupt::invoke(), setContextSegment(), setKvmSegmentReg(), X86ISA::TLB::translate(), and X86ISA::GpuTLB::translate().
|
inlinestatic |
Definition at line 514 of file misc.hh.
References index, MISCREG_SEG_BASE_BASE, and NUM_SEGMENTREGS.
Referenced by X86ISA::X86_64Process::initState(), X86ISA::I386Process::initState(), installSegDesc(), X86ISA::InitInterrupt::invoke(), setContextSegment(), setKvmDTableReg(), setKvmSegmentReg(), X86ISA::TLB::translate(), and X86ISA::GpuTLB::translate().
|
inlinestatic |
Definition at line 521 of file misc.hh.
References index, MISCREG_SEG_EFF_BASE_BASE, and NUM_SEGMENTREGS.
Referenced by X86ISA::X86_64Process::initState(), X86ISA::I386Process::initState(), installSegDesc(), X86ISA::InitInterrupt::invoke(), and X86ISA::ISA::setMiscReg().
|
inlinestatic |
Definition at line 528 of file misc.hh.
References index, MISCREG_SEG_LIMIT_BASE, and NUM_SEGMENTREGS.
Referenced by X86ISA::I386Process::initState(), installSegDesc(), X86ISA::InitInterrupt::invoke(), setContextSegment(), setKvmDTableReg(), setKvmSegmentReg(), X86ISA::TLB::translate(), and X86ISA::GpuTLB::translate().
|
inlinestatic |
Definition at line 507 of file misc.hh.
References index, MISCREG_SEG_SEL_BASE, and NUM_SEGMENTREGS.
Referenced by X86ISA::I386Process::initState(), X86ISA::InitInterrupt::invoke(), setContextSegment(), setKvmSegmentReg(), X86ISA::TLB::translate(), and X86ISA::GpuTLB::translate().
| bool X86ISA::msrAddrToIndex | ( | MiscRegIndex & | regNum, |
| Addr | addr | ||
| ) |
Find and return the misc reg corresponding to an MSR address.
Look for an MSR (addr) in msrMap and return the corresponding misc reg in regNum. The value of regNum is undefined if the MSR was not found.
| regNum | misc reg index (out). |
| addr | MSR address |
Definition at line 149 of file msr.cc.
References msrMap.
Referenced by X86ISA::TLB::translateInt().
| const MsrMap X86ISA::msrMap | ( | msrMapData | , |
| msrMapData+ | msrMapSize | ||
| ) |
|
inlinestatic |
Definition at line 158 of file types.hh.
References BitUnion8(), and AlphaISA::Opcode().
Referenced by operator<<().
|
inlinestatic |
Definition at line 239 of file types.hh.
References ccprintf(), X86ISA::ExtMachInst::displacement, X86ISA::ExtMachInst::dispSize, X86ISA::ExtMachInst::immediate, X86ISA::ExtMachInst::legacy, X86ISA::ExtMachInst::modRM, X86ISA::ExtMachInst::op, X86ISA::ExtMachInst::opcode, opcodeTypeToStr(), os, X86ISA::ExtMachInst::rex, X86ISA::ExtMachInst::sib, X86ISA::ExtMachInst::type, and X86ISA::ExtMachInst::vex.
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inlinestatic |
Definition at line 256 of file types.hh.
References X86ISA::ExtMachInst::addrSize, X86ISA::ExtMachInst::displacement, X86ISA::ExtMachInst::dispSize, X86ISA::ExtMachInst::immediate, X86ISA::ExtMachInst::legacy, X86ISA::ExtMachInst::mode, X86ISA::ExtMachInst::modRM, X86ISA::ExtMachInst::op, X86ISA::ExtMachInst::opcode, X86ISA::ExtMachInst::opSize, X86ISA::ExtMachInst::rex, X86ISA::ExtMachInst::sib, X86ISA::ExtMachInst::stackSize, X86ISA::ExtMachInst::type, and X86ISA::ExtMachInst::vex.
Referenced by ArmISA::EndBitUnion(), and sc_core::sc_process_handle::operator=().
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Definition at line 107 of file memhelpers.hh.
References letoh(), NoFault, ExecContext::readMem(), and Trace::InstRecord::setData().
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Definition at line 141 of file memhelpers.hh.
References addr, mem, NoFault, panic, and Trace::InstRecord::setData().
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Definition at line 125 of file memhelpers.hh.
References ArmISA::i, letoh(), NoFault, and ExecContext::readMem().
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Definition at line 48 of file stacktrace.cc.
References addr, SymbolTable::findAddress(), ThreadContext::getSystemPtr(), ThreadContext::getVirtProxy(), GuestByteOrder, System::kernelSymtab, panic, and PortProxy::read().
Referenced by X86ISA::ProcessInfo::ProcessInfo().
| void X86ISA::setRFlags | ( | ThreadContext * | tc, |
| uint64_t | val | ||
| ) |
Set update the rflags register and internal gem5 state.
| tc | Thread context to update |
| val | New rflags value to store in TC |
Definition at line 134 of file utility.cc.
References ccFlagMask, CCREG_CFOF, CCREG_DF, CCREG_ECF, CCREG_EZF, CCREG_ZAPS, cfofMask, DFBit, MISCREG_RFLAGS, ThreadContext::setCCReg(), and ThreadContext::setMiscReg().
Referenced by getExecutingAsid(), and X86KvmCPU::updateThreadContextRegs().
| void X86ISA::skipFunction | ( | ThreadContext * | tc | ) |
| void X86ISA::storeFloat80 | ( | void * | mem, |
| double | value | ||
| ) |
Convert and store a double as an 80-bit float.
| mem | Pointer to destination for the 80-bit float. |
| value | Double precision float to store. |
Definition at line 225 of file utility.cc.
Referenced by getDoubleBits(), and updateKvmStateFPUCommon().
| uint64_t X86ISA::stringToRegister | ( | const char * | str | ) |
Definition at line 78 of file cpuid.cc.
References reg.
Referenced by X86ISA::CpuidResult::CpuidResult(), and doCpuid().
| X86ISA::SubBitUnion | ( | type | , |
| 43 | , | ||
| 40 | |||
| ) |
Definition at line 55 of file vtophys.cc.
Referenced by ArmISA::PteAddr().
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inline |
Definition at line 61 of file vtophys.cc.
References addr, DPRINTF, fatal, ThreadContext::getDTBPtr(), ArmISA::mask, NoFault, panic, BaseTLB::Read, X86ISA::Walker::startFunctional(), try_translate(), and MipsISA::vaddr.
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Definition at line 206 of file memhelpers.hh.
References htole(), letoh(), NoFault, Trace::InstRecord::setData(), and ExecContext::writeMem().
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Definition at line 222 of file memhelpers.hh.
References addr, letoh(), mem, NoFault, panic, and Trace::InstRecord::setData().
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Definition at line 176 of file memhelpers.hh.
References htole(), Trace::InstRecord::setData(), and ExecContext::writeMem().
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Definition at line 188 of file memhelpers.hh.
References addr, mem, panic, and Trace::InstRecord::setData().
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Definition at line 164 of file memhelpers.hh.
References htole(), ArmISA::i, and ExecContext::writeMem().
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inlinestatic |
Definition at line 100 of file x86_traits.hh.
References PhysAddrAPICRangeSize.
Referenced by buildIntTriggerPacket(), X86ISA::Interrupts::getIntAddrRange(), and X86ISA::Interrupts::recvMessage().
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inlinestatic |
Definition at line 81 of file x86_traits.hh.
Referenced by X86KvmCPU::handleKvmExitIO().
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inlinestatic |
Definition at line 93 of file x86_traits.hh.
References addr.
Referenced by X86ISA::TLB::finalizePhysical(), X86ISA::Interrupts::setCPU(), and X86ISA::GpuTLB::translate().
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inlinestatic |
Definition at line 87 of file x86_traits.hh.
References addr.
Referenced by X86KvmCPU::handleKvmExitIO().
| Bitfield< 40 > X86ISA::a |
Definition at line 147 of file pagetable.hh.
Referenced by AlphaISA::VAddr::operator=(), and PowerISA::VAddr::operator=().
| Bitfield<18> X86ISA::ac |
Definition at line 563 of file misc.hh.
Referenced by LinuxArmSystem::initState().
| Bitfield<3> X86ISA::addr |
Definition at line 81 of file types.hh.
Referenced by buildIntPacket(), buildIntTriggerPacket(), X86ISA::StackTrace::decodePrologue(), X86ISA::PageFault::describe(), X86System::fixFuncEventAddr(), X86ISA::SMBios::SMBiosStructure::getLength(), X86ISA::SMBios::BiosInformation::getLength(), handleIprRead(), handleIprWrite(), X86ISA::PageFault::invoke(), X86ISA::I8042::read(), readMemAtomic(), readSymbol(), X86ISA::TLB::setConfigAddress(), X86ISA::GpuTLB::setConfigAddress(), X86ISA::IntelMP::FloatingPointer::setTableAddr(), X86ISA::SMBios::SMBiosTable::setTableAddr(), X86ISA::Walker::WalkerState::setupWalk(), X86ISA::TLB::takeOverFrom(), X86ISA::Decoder::updateNPC(), X86ISA::Walker::WalkerSenderState::WalkerSenderState(), X86ISA::Walker::WalkerState::WalkerState(), X86ISA::I8042::write(), writeMemAtomic(), writeMemTiming(), x86LocalAPICAddress(), x86PciConfigAddress(), and X86ISA::GpuTLB::Translation::~Translation().
| const uint8_t X86ISA::AO = AddressSizeOverride |
Definition at line 53 of file decoder_tables.cc.
| Bitfield< 5 > X86ISA::avl |
Definition at line 143 of file pagetable.hh.
| const StaticInstPtr X86ISA::badMicroop |
Definition at line 59 of file badmicroop.cc.
Referenced by X86ISAInst::MicrocodeRom::fetchMicroop(), and X86ISA::MacroopBase::fetchMicroop().
| Bitfield< 2, 0 > X86ISA::base |
Definition at line 142 of file pagetable.hh.
Referenced by Iris::BaseCPU::BaseCPU(), Stats::Hdf5::beginGroup(), ElfObject::buildImage(), PacketFifo::check(), PacketFifoEntry::clear(), FastModel::CortexA76Cluster::CortexA76Cluster(), EmbeddedPyBind::depsReady(), SMMUTranslationProcess::doReadPTE(), dumpDmesgEntry(), IdeController::EndBitUnion(), EndBitUnion(), sc_dt::scfx_rep::from_string(), sc_dt::sc_fxval_fast::from_string(), ArmISA::SysDC64::generateDisassembly(), ArmISA::RfeOp::generateDisassembly(), ArmISA::MemoryDImm64::generateDisassembly(), ArmISA::MemoryDImmEx64::generateDisassembly(), ArmISA::MemoryEx64::generateDisassembly(), ArmFreebsdProcessBits::SyscallTable::getDesc(), ArmLinuxProcessBits::SyscallTable::getDesc(), ArmISA::RemoteGDB::AArch64GdbRegCache::getRegs(), SymbolTable::getSymbolTable(), ArmISA::ArmFault::getVector(), ArmISA::Reset::getVector(), EmbeddedPython::initAll(), AlphaSystem::initState(), X86System::initState(), Packet::isMaskedWrite(), DictionaryCompressor< T >::DeltaPattern< DeltaSizeBits >::isValidDelta(), Stats::VectorPrint::operator()(), Stats::DistPrint::operator()(), Stats::SparseHistPrint::operator()(), Time::operator-=(), sc_dt::operator<<(), Intel8254Timer::outputHigh(), Gicv3Its::pageAddress(), sc_gem5::Object::pickUniqueName(), sc_gem5::pickUniqueName(), ArmISA::Memory::printInst(), ItsProcess::readDeviceTable(), ItsProcess::readIrqCollectionTable(), X86ISA::ISA::readMiscReg(), ArmSemihosting::readString(), sc_dt::scfx_parse_base(), IdeController::serialize(), ArmISA::RemoteGDB::AArch64GdbRegCache::setRegs(), EtherLink::Link::setRxInt(), ArmISA::ArmStaticInst::shift_rm_rs(), ArmISA::ArmStaticInst::shiftReg64(), ArmISA::Memory64::startDisassembly(), MipsISA::ProcessInfo::task(), X86ISA::ProcessInfo::task(), AlphaISA::ProcessInfo::task(), ArmISA::ProcessInfo::task(), MemTest::tick(), X86ISA::TLB::translate(), X86ISA::GpuTLB::translate(), IdeController::unserialize(), sc_dt::vec_from_str(), Packet::writeData(), ItsProcess::writeDeviceTable(), ItsProcess::writeIrqCollectionTable(), X86ISA::SMBios::SMBiosTable::writeOut(), X86ISA::X86StaticInst::X86StaticInst(), and EthPacketData::~EthPacketData().
| Bitfield<8> X86ISA::bsp |
Definition at line 1054 of file misc.hh.
Referenced by sc_gem5::Gem5ToTlmBridge< BITWIDTH >::pec(), and sc_gem5::Gem5ToTlmBridge< BITWIDTH >::recvRespRetry().
Definition at line 69 of file misc.hh.
Referenced by setRFlags().
Definition at line 68 of file misc.hh.
Referenced by setRFlags().
| Bitfield< 36, 32 > X86ISA::count |
Definition at line 705 of file misc.hh.
Referenced by FlashDevice::accessDevice(), sc_gem5::VcdTraceFile::addTraceVal(), DefaultCommit< Impl >::commitInsts(), countBoolVec(), FastModel::SCGIC::Terminator::countUnbound(), DmaCallback::drain(), IGbE::drain(), FunctionProfile::dump(), UFSHostDevice::finalUTP(), DmaCallback::getChunkEvent(), BloomFilter::MultiBitSel::getCount(), BloomFilter::Multi::getCount(), Iris::ThreadContext::getCurrentInstCount(), MultiperspectivePerceptron::BLURRYPATH::getHash(), BloomFilter::Multi::getTotalCount(), BloomFilter::Base::getTotalCount(), X86KvmCPU::handleKvmExitIO(), CPA::hwWe(), FlashDevice::initializeFlash(), BloomFilter::Multi::isSet(), ElfObject::loadSomeSymbols(), UFSHostDevice::manageReadTransfer(), UFSHostDevice::manageWriteTransfer(), System::markWorkItem(), Iris::ThreadContext::noThrow(), MipsISA::Interrupts::onCpuTimerInterrupt(), StackDistCalc::printStack(), AnnotateDumpCallback::process(), QueuedPrefetcher::processMissingTranslations(), SimpleDisk::read(), Intel8254Timer::Counter::read(), UFSHostDevice::UFSSCSIDevice::readFlash(), readvFunc(), FlashDevice::remap(), UFSHostDevice::requestHandler(), FutexMap::requeue(), rmdirFunc(), SC_MODULE(), UFSHostDevice::UFSSCSIDevice::SCSICMDHandle(), UFSHostDevice::SCSIResume(), FlashDevice::serialize(), EmulationPageTable::serialize(), Sinic::Device::serialize(), ActivityRecorder::setActivityCount(), LocalBP::squash(), UFSHostDevice::UFSSCSIDevice::statusCheck(), Iris::BaseCPU::totalInsts(), UFSHostDevice::UFSHostDevice(), FlashDevice::unserialize(), EmulationPageTable::unserialize(), ActivityRecorder::validate(), Checker< O3CPUImpl >::verify(), sc_gem5::Process::waitCount(), FutexMap::wakeup(), UFSHostDevice::UFSSCSIDevice::writeFlash(), writevFunc(), and ThreadContext::~ThreadContext().
| const uint8_t X86ISA::CS = CSOverride |
Definition at line 45 of file decoder_tables.cc.
Referenced by SC_MODULE().
| const bool X86ISA::CurThreadInfoImplemented = false |
Definition at line 58 of file isa_traits.hh.
| const int X86ISA::CurThreadInfoReg = -1 |
Definition at line 59 of file isa_traits.hh.
| Bitfield< 54 > X86ISA::d |
Definition at line 146 of file pagetable.hh.
| Bitfield<3> X86ISA::de |
Definition at line 637 of file misc.hh.
Referenced by dumpDmesgEntry(), and OutputDirectory::remove().
| Bitfield< 10, 8 > X86ISA::deliveryMode |
Definition at line 47 of file intmessage.hh.
Referenced by APIC_INTERRUPT_REQUEST().
| X86ISA::destination |
Definition at line 45 of file intmessage.hh.
Referenced by GarnetSyntheticTraffic::generatePkt(), UFSHostDevice::readDevice(), and UFSHostDevice::transferDone().
| Bitfield< 11 > X86ISA::destMode |
Definition at line 48 of file intmessage.hh.
Referenced by APIC_INTERRUPT_REQUEST().
| const uint8_t X86ISA::DS = DSOverride |
Definition at line 46 of file decoder_tables.cc.
| Bitfield<31,0> X86ISA::E |
Definition at line 53 of file int.hh.
Referenced by ArmISA::ArmStaticInst::cSwap().
| Bitfield<2> X86ISA::em |
Definition at line 604 of file misc.hh.
Referenced by TCPIface::anyislistening(), Consumer::scheduleEvent(), Consumer::scheduleEventAbsolute(), and Intel8254Timer::~Intel8254Timer().
| Bitfield<11> X86ISA::enable |
Definition at line 1053 of file misc.hh.
Referenced by ArmISA::addPACDA(), ArmISA::addPACDB(), ArmISA::addPACIA(), ArmISA::addPACIB(), ArmISA::PMU::PMUEvent::attachEvent(), ArmISA::authDA(), ArmISA::authDB(), ArmISA::authIA(), ArmISA::authIB(), sc_gem5::Process::disabled(), sc_core::sc_process_handle::operator=(), Gicv3CPUInterface::setMiscReg(), ArmISA::PMU::updateAllCounters(), and Gicv3Distributor::write().
| const uint8_t X86ISA::ES = ESOverride |
Definition at line 47 of file decoder_tables.cc.
| Bitfield<3> X86ISA::exit |
Definition at line 850 of file misc.hh.
Referenced by SimpleATTarget1::beginResponse(), MultiSocketSimpleSwitchAT::bwPEQcb(), MultiSocketSimpleSwitchAT::initiatorNBTransport(), SimpleBusAT< NR_OF_INITIATORS, NR_OF_TARGETS >::initiatorNBTransport(), MultiSocketSimpleSwitchAT::initiatorNBTransport_core(), RoutingUnit::lookupRoutingTable(), main(), ExplicitATTarget::myNBTransport(), SimpleATTarget2::myNBTransport(), SimpleATTarget1::myNBTransport(), SimpleLTInitiator_ext::myNBTransport(), SimpleATInitiator2::myNBTransport(), SimpleATInitiator1::myNBTransport(), TraceCPU::FixedRetryGen::name(), TraceCPU::ElasticDataGen::name(), SimpleBusAT< NR_OF_INITIATORS, NR_OF_TARGETS >::RequestThread(), SimpleBusAT< NR_OF_INITIATORS, NR_OF_TARGETS >::ResponseThread(), SimpleLTInitiator_ext::run(), SimpleATInitiator2::run(), SimpleATInitiator1::run(), Sinic::Device::rxKick(), NSGigE::rxKick(), ArmISA::ArmStaticInst::shift_carry_imm(), ArmISA::ArmStaticInst::shift_carry_rs(), ArmISA::ArmStaticInst::shift_rm_imm(), ArmISA::ArmStaticInst::shift_rm_rs(), ArmISA::ArmStaticInst::shiftReg64(), MultiSocketSimpleSwitchAT::targetNBTransport(), SimpleBusAT< NR_OF_INITIATORS, NR_OF_TARGETS >::targetNBTransport(), Sinic::Device::txKick(), NSGigE::txKick(), and usage().
| Bitfield<14> X86ISA::expandDown |
Definition at line 998 of file misc.hh.
Referenced by X86ISA::TLB::translate(), and X86ISA::GpuTLB::translate().
| const int X86ISA::FlagShift = 4 |
Definition at line 52 of file ldstflags.hh.
Referenced by Sequencer::makeRequest(), GPUCoalescer::makeRequest(), X86ISA::GpuTLB::pagingProtectionChecks(), X86ISA::TLB::translate(), and X86ISA::GpuTLB::translate().
| const int X86ISA::FramePointerReg = INTREG_RBP |
Definition at line 91 of file registers.hh.
| const uint8_t X86ISA::FS = FSOverride |
Definition at line 48 of file decoder_tables.cc.
| Bitfield< 55 > X86ISA::g |
Definition at line 144 of file pagetable.hh.
Referenced by X86ISA::SegDescriptorLimit::setter().
| const uint64_t X86ISA::GDTVirtAddr = 0xffff800000001000 |
Definition at line 67 of file system.hh.
Referenced by X86ISA::X86_64Process::initState().
| const uint8_t X86ISA::GS = GSOverride |
Definition at line 49 of file decoder_tables.cc.
| const ByteOrder X86ISA::GuestByteOrder = LittleEndianByteOrder |
Definition at line 50 of file isa_traits.hh.
Referenced by X86ISA::X86Process::argsInit(), X86ISA::ProcessInfo::pid(), readSymbol(), and X86ISA::ProcessInfo::task().
| const bool X86ISA::HasUnalignedMemAcc = true |
Definition at line 56 of file isa_traits.hh.
| const uint64_t X86ISA::IDTVirtAddr = 0xffff800000002000 |
Definition at line 68 of file system.hh.
Referenced by X86ISA::X86_64Process::initState().
| Bitfield<5,3> X86ISA::index |
Definition at line 95 of file types.hh.
Referenced by APIC_IN_SERVICE(), APIC_INTERRUPT_REQUEST(), APIC_TRIGGER_MODE(), X86ISA::CpuidResult::CpuidResult(), FLOATREG_FPR(), FLOATREG_MICROFP(), FLOATREG_MMX(), FLOATREG_XMM_LOW(), handleIprRead(), handleIprWrite(), INTREG_FOLDED(), INTREG_IMPLICIT(), INTREG_MICRO(), X86ISA::InitInterrupt::invoke(), MISCREG_CR(), MISCREG_DR(), MISCREG_IORR_BASE(), MISCREG_IORR_MASK(), MISCREG_MC_ADDR(), MISCREG_MC_CTL(), MISCREG_MC_MISC(), MISCREG_MC_STATUS(), MISCREG_MTRR_PHYS_BASE(), MISCREG_MTRR_PHYS_MASK(), MISCREG_PERF_EVT_CTR(), MISCREG_PERF_EVT_SEL(), MISCREG_SEG_ATTR(), MISCREG_SEG_BASE(), MISCREG_SEG_EFF_BASE(), MISCREG_SEG_LIMIT(), MISCREG_SEG_SEL(), X86ISA::I82094AA::readReg(), and X86ISA::I82094AA::writeReg().
Definition at line 68 of file x86_traits.hh.
Referenced by X86ISA::TLB::translateInt(), and X86ISA::GpuTLB::translateInt().
Definition at line 70 of file x86_traits.hh.
Referenced by X86ISA::TLB::translateInt(), and X86ISA::GpuTLB::translateInt().
Definition at line 67 of file x86_traits.hh.
Referenced by X86ISA::TLB::translateInt(), and X86ISA::GpuTLB::translateInt().
Definition at line 69 of file x86_traits.hh.
Referenced by X86ISA::TLB::translateInt(), and X86ISA::GpuTLB::translateInt().
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static |
Definition at line 153 of file int.hh.
Referenced by X86ISA::ISA::flattenIntIndex(), X86ISA::X86StaticInst::merge(), X86ISA::X86StaticInst::pick(), X86ISA::X86StaticInst::printReg(), and X86ISA::X86StaticInst::signedPick().
| Bitfield<23> X86ISA::inv |
Definition at line 810 of file misc.hh.
Referenced by BasePrefetcher::observeAccess().
| const uint64_t X86ISA::ISTVirtAddr = 0xffff800000004000 |
Definition at line 71 of file system.hh.
Referenced by X86ISA::X86_64Process::initState(), and m5PageFault().
| Bitfield<7, 0> X86ISA::L |
Definition at line 59 of file int.hh.
Referenced by ArmProcess32::ArmProcess32(), ArmProcess64::ArmProcess64(), ArmISA::TableWalker::doLongDescriptor(), KvmDevice::ioctl(), Kvm::ioctl(), PerfKvmCounter::ioctl(), KvmVM::ioctl(), BaseKvmCPU::ioctl(), MipsProcess::MipsProcess(), PowerProcess::PowerProcess(), ArmISA::TableWalker::processWalkAArch64(), RiscvProcess32::RiscvProcess32(), RiscvProcess64::RiscvProcess64(), and SparcISA::TlbEntry::unserialize().
| Bitfield<8> X86ISA::le |
Definition at line 666 of file misc.hh.
Referenced by sc_gem5::DynamicSensitivityEventOrList::notifyWork().
| Bitfield<19, 18> X86ISA::len0 |
Definition at line 670 of file misc.hh.
Referenced by tlm::loop_word1(), tlm::tlm_from_hostendian_word(), and tlm::tlm_to_hostendian_word().
| Bitfield< 14 > X86ISA::level |
Definition at line 49 of file intmessage.hh.
Referenced by X86ISA::Interrupts::clockPeriod(), Trie< Key, Value >::Node::dump(), SparcISA::Interrupts::getInterrupt(), StackDistCalc::getSum(), SparcISA::Interrupts::InterruptLevel(), SparcISA::SparcFaultBase::invoke(), WalkCache::lookup(), WalkCache::pickEntryIdxToReplace(), WalkCache::pickSetIdx(), StackDistCalc::sanityCheckTree(), SMMUTranslationProcess::translateStage1And2(), SMMUTranslationProcess::translateStage2(), StackDistCalc::updateSum(), StackDistCalc::updateSumsLeavesToRoot(), SMMUTranslationProcess::walkCacheLookup(), SMMUTranslationProcess::walkCacheUpdate(), SMMUTranslationProcess::walkStage1And2(), SMMUTranslationProcess::walkStage2(), and WalkCache::~WalkCache().
| BitfieldType< SegDescriptorLimit > X86ISA::limit |
Definition at line 926 of file misc.hh.
Referenced by sc_dt::sc_uint_base::check_value(), sc_dt::sc_int_base::check_value(), EndBitUnion(), X86ISA::SegDescriptorLimit::getter(), MemFootprintProbe::insertAddr(), DictionaryCompressor< T >::DeltaPattern< DeltaSizeBits >::isValidDelta(), ProtoInputStream::read(), sc_core::sc_report_handler::stop_after(), X86ISA::TLB::translate(), and X86ISA::GpuTLB::translate().
| const uint8_t X86ISA::LO = Lock |
Definition at line 54 of file decoder_tables.cc.
| Bitfield<5> X86ISA::lock |
Definition at line 79 of file types.hh.
Referenced by DistIface::Sync::abort(), sc_gem5::Scheduler::asyncRequestUpdate(), doSimLoop(), BaseKvmCPU::drain(), DrainManager::drainableCount(), DistIface::SyncNode::progress(), DistIface::SyncSwitch::progress(), DrainManager::registerDrainable(), DistIface::SyncNode::requestCkpt(), DistIface::SyncNode::requestExit(), DistIface::SyncNode::requestStopSync(), DistIface::SyncNode::run(), DistIface::SyncSwitch::run(), sc_gem5::Scheduler::runUpdate(), EventQueue::serviceOne(), DrainManager::unregisterDrainable(), and Barrier::wait().
| X86ISA::longl1 |
Definition at line 124 of file pagetable.hh.
| Bitfield<29, 21> X86ISA::longl2 |
Definition at line 125 of file pagetable.hh.
| Bitfield<38, 30> X86ISA::longl3 |
Definition at line 126 of file pagetable.hh.
| Bitfield<47, 39> X86ISA::longl4 |
Definition at line 127 of file pagetable.hh.
| X86ISA::mask |
Definition at line 798 of file misc.hh.
Referenced by X86ISA::RemoteGDB::acc(), X86ISA::ISA::clear(), X86ISA::Decoder::decode(), decodeAddr(), X86ISA::Decoder::getImmediate(), X86ISA::I386Process::getSyscallArg(), X86ISA::SegDescriptorLimit::getter(), handleIprRead(), handleIprWrite(), X86ISA::Interrupts::read(), X86ISA::ISA::setMiscRegNoEffect(), X86ISA::SegDescriptorLimit::setter(), X86ISA::Walker::WalkerState::stepWalk(), X86ISA::TLB::translate(), X86ISA::TLB::translateInt(), X86ISA::GpuTLB::translateInt(), X86ISA::I8259::write(), and X86ISA::Interrupts::write().
| const uint64_t X86ISA::MMIORegionPhysAddr = 0xffff0000 |
Definition at line 74 of file system.hh.
Referenced by X86ISA::X86_64Process::initState().
| const uint64_t X86ISA::MMIORegionVirtAddr = 0xffffc90000000000 |
Definition at line 73 of file system.hh.
Referenced by X86ISA::X86_64Process::initState().
| X86ISA::mod |
Definition at line 88 of file types.hh.
Referenced by X86ISA::IntelMP::CompatAddrSpaceMod::writeOut().
| Bitfield<1> X86ISA::mp |
Definition at line 605 of file misc.hh.
Referenced by GlobalMemPipeline::exec().
| const MsrMap X86ISA::msrMap |
Map between MSR addresses and their corresponding misc registers.
Referenced by X86KvmCPU::getMsrIntersection(), msrAddrToIndex(), X86KvmCPU::updateKvmStateMSRs(), and X86KvmCPU::updateThreadContextMSRs().
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| Bitfield<21, 12> X86ISA::norml1 |
Definition at line 133 of file pagetable.hh.
| Bitfield<31, 22> X86ISA::norml2 |
Definition at line 134 of file pagetable.hh.
| const int X86ISA::NumCCRegs = NUM_CCREGS |
Definition at line 61 of file registers.hh.
Referenced by copyRegs().
| const int X86ISA::NumCRegs = 16 |
Definition at line 61 of file x86_traits.hh.
Referenced by MISCREG_CR().
| const int X86ISA::NumDRegs = 8 |
Definition at line 62 of file x86_traits.hh.
Referenced by MISCREG_DR().
| const int X86ISA::NumFloatRegs |
| const int X86ISA::NumImplicitIntRegs = 6 |
Definition at line 49 of file x86_traits.hh.
| const int X86ISA::NumIntArchRegs = NUM_INTREGS |
Definition at line 59 of file registers.hh.
| const int X86ISA::NumIntRegs = NumIntArchRegs + NumMicroIntRegs + NumImplicitIntRegs |
Definition at line 60 of file registers.hh.
Referenced by copyRegs().
| const int X86ISA::NumMicroFpRegs = 8 |
Definition at line 59 of file x86_traits.hh.
Referenced by X86ISA::X86StaticInst::printReg().
| const int X86ISA::NumMicroIntRegs = 16 |
Definition at line 47 of file x86_traits.hh.
Referenced by INTREG_IMPLICIT().
| const int X86ISA::NumMiscRegs = NUM_MISCREGS |
Definition at line 57 of file registers.hh.
Referenced by X86ISA::ISA::clear(), X86ISA::ISA::serialize(), and X86ISA::ISA::unserialize().
| const int X86ISA::NumMMXRegs = 8 |
Definition at line 57 of file x86_traits.hh.
Referenced by X86ISA::X86StaticInst::printReg().
| const int X86ISA::NumSegments = 6 |
Definition at line 64 of file x86_traits.hh.
| const int X86ISA::NumSysSegments = 4 |
Definition at line 65 of file x86_traits.hh.
| constexpr unsigned X86ISA::NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg |
Definition at line 102 of file registers.hh.
| const int X86ISA::NumVecPredRegs = 1 |
Definition at line 81 of file registers.hh.
| const int X86ISA::NumVecRegs = 1 |
Definition at line 79 of file registers.hh.
| const int X86ISA::NumXMMRegs = 16 |
Definition at line 58 of file x86_traits.hh.
Referenced by X86ISA::X86StaticInst::printReg().
| Bitfield<11> X86ISA::of |
Definition at line 568 of file misc.hh.
Referenced by MISCREG_SEG_ATTR(), and AnnotateDumpCallback::process().
| X86ISA::offset |
Definition at line 1026 of file misc.hh.
Referenced by doCpuid(), X86ISA::Interrupts::findRegArrayMSB(), handleIprRead(), handleIprWrite(), X86ISA::I82094AA::params(), X86ISA::I8237::read(), X86ISA::I8254::read(), X86ISA::I82094AA::read(), X86ISA::Interrupts::read(), X86ISA::Interrupts::recvMessage(), X86ISA::Interrupts::setReg(), X86ISA::TLB::translate(), X86ISA::GpuTLB::translate(), X86ISA::I8237::write(), X86ISA::I8254::write(), X86ISA::I82094AA::write(), X86ISA::Interrupts::write(), X86ISA::IntelMP::ConfigTable::writeOut(), X86ISA::SMBios::SMBiosTable::writeOut(), and X86ISA::SMBios::SMBiosStructure::writeOutStrings().
| const uint8_t X86ISA::OO = OperandSizeOverride |
Definition at line 52 of file decoder_tables.cc.
| Bitfield<4> X86ISA::op |
Definition at line 80 of file types.hh.
Referenced by TimingExprUn::eval(), TimingExprBin::eval(), HsailISA::Call::execPseudoInst(), AtomicGeneric2Op< T >::execute(), AtomicGeneric3Op< T >::execute(), AtomicGenericPair3Op< T >::execute(), RiscvISA::AtomicGenericOp< T >::execute(), findRegDataType(), ArmISA::FPCRRounding(), ArmISA::fplibRoundInt(), ArmSystem::haveSemihosting(), CPA::hwWe(), RegAddrOperand< RegOperandType >::init(), LabelOperand::init(), osf_getsysinfoFunc(), osf_setsysinfoFunc(), AnnotateDumpCallback::process(), Stats::UnaryNode< Op >::result(), Stats::BinaryNode< Op >::result(), Stats::SumNode< Op >::result(), ArmISA::ArmStaticInst::satInt(), SC_MODULE(), ArmISA::Crypto::sigma1(), HsailISA::StInst< MemDataType, SrcDataType, AddrOperandType >::StInst(), sys_getsysinfoFunc(), sys_setsysinfoFunc(), Stats::BinaryNode< Op >::total(), Stats::SumNode< Op >::total(), ArmISA::ArmStaticInst::uSatInt(), and ArmISA::vfpFpToFixed().
| Bitfield<17> X86ISA::os |
Definition at line 805 of file misc.hh.
Referenced by ArmISA::ArmStaticInst::ArmStaticInst(), BitfieldBackend::bitfieldBackendPrinter(), MSHR::delay(), sc_core::sc_fifo< T >::dump(), sc_gem5::ScSignalBaseT< sc_dt::sc_logic, WRITER_POLICY >::dump(), Trie< Addr, uint32_t >::dump(), GuestABI::dumpArgsFrom(), dumpDmesgEntry(), O3ThreadState< Impl >::dumpFuncProfile(), SimpleThread::dumpFuncProfile(), IdeController::EndBitUnion(), ArmISA::Memory64::fetchMicroop(), OutputDirectory::findOrCreate(), sc_gem5::UniqueNameGen::gen(), CxxConfigManager::getObject(), PowerISA::PowerStaticInst::insertCRField(), Minor::BranchData::isBranch(), MSHR::TargetList::isReset(), ArmISA::MemoryReg::MemoryReg(), Minor::LSQ::StoreBuffer::minorTrace(), MsrBase::MsrBase(), OutputDirectory::open(), Minor::operator<<(), sc_core::operator<<(), GenericISA::operator<<(), operator<<(), GuestABI::operator<<(), sc_dt::operator<<(), operator<<(), rgb_t::operator==(), Minor::InstId::operator==(), WriteQueueEntry::popTarget(), sc_dt::sc_bitref_r< X >::print(), sc_core::sc_fifo< T >::print(), sc_dt::sc_uint_bitref_r::print(), sc_gem5::ScSignalBaseT< sc_dt::sc_logic, WRITER_POLICY >::print(), sc_dt::sc_int_bitref_r::print(), sc_dt::sc_bit::print(), sc_dt::sc_logic::print(), sc_dt::sc_uint_subref_r::print(), sc_dt::sc_int_subref_r::print(), sc_dt::sc_concatref::print(), sc_dt::sc_proxy< sc_subref_r< X > >::print(), sc_dt::sc_unsigned_bitref_r::print(), sc_dt::sc_signed_bitref_r::print(), sc_dt::sc_unsigned_subref_r::print(), sc_dt::sc_uint_base::print(), sc_dt::sc_signed_subref_r::print(), sc_dt::sc_int_base::print(), sc_dt::sc_unsigned::print(), sc_dt::sc_signed::print(), ArmISA::Memory::printDest(), Linux::DmesgDumpEvent::process(), AnnotateDumpCallback::process(), Linux::KernelPanicEvent::process(), Minor::QueuedInst::QueuedInst(), Minor::LSQ::LSQRequest::setSkipped(), WriteQueueEntry::TargetList::TargetList(), sc_gem5::VcdTraceValBase::vcdType(), PseudoInst::writefile(), X86ISA::X86StaticInst::X86StaticInst(), and Printable::~Printable().
| Bitfield<62> X86ISA::over |
Definition at line 770 of file misc.hh.
Referenced by sc_dt::scfx_rep::overflow(), and sc_dt::overflow().
| Bitfield< 1, 0 > X86ISA::p |
Definition at line 152 of file pagetable.hh.
Referenced by X86ISA::GpuTLB::GpuTLB(), X86ISA::Interrupts::Interrupts(), X86ISA::GpuTLB::issueTLBLookup(), m5PageFault(), X86ISA::I8259::params(), X86ISA::I82094AA::params(), X86ISA::I8042::params(), X86ISA::GpuTLB::CpuSidePort::recvFunctional(), X86ISA::Interrupts::setRegNoEffect(), X86ISA::IntelMP::FloatingPointer::setTableAddr(), X86ISA::TLB::translate(), X86ISA::GpuTLB::translate(), and X86ISA::GpuTLB::translationReturn().
| Bitfield<20, 12> X86ISA::pael1 |
Definition at line 129 of file pagetable.hh.
| Bitfield<29, 21> X86ISA::pael2 |
Definition at line 130 of file pagetable.hh.
| Bitfield<31, 30> X86ISA::pael3 |
Definition at line 131 of file pagetable.hh.
Definition at line 53 of file isa_traits.hh.
Referenced by X86ISA::X86Process::argsInit(), X86ISA::TLB::finalizePhysical(), X86ISA::Interrupts::getAddrRanges(), X86ISA::I386Process::I386Process(), X86ISA::X86_64Process::initState(), X86ISA::I386Process::initState(), m5PageFault(), X86ISA::GpuTLB::translate(), and X86ISA::X86_64Process::X86_64Process().
| const Addr X86ISA::PageShift = 12 |
Definition at line 52 of file isa_traits.hh.
Referenced by X86ISA::LongModePTE::paddr(), and X86ISA::LongModePTE::tableSize().
| Bitfield<19> X86ISA::pc |
Definition at line 807 of file misc.hh.
Referenced by X86ISA::PCState::branching(), X86ISA::StackTrace::decodePrologue(), X86ISA::FpOp::FpOp(), ImmOp::ImmOp(), X86ISA::X86FaultBase::invoke(), X86ISA::X86Trap::invoke(), X86ISA::InitInterrupt::invoke(), X86ISA::LdStOp::LdStOp(), X86ISA::LdStSplitOp::LdStSplitOp(), McrrOp::McrrOp(), X86ISA::MediaOpImm::MediaOpImm(), X86ISA::MediaOpReg::MediaOpReg(), PowerISA::MiscOp::MiscOp(), MiscRegRegImmOp::MiscRegRegImmOp(), MrrcOp::MrrcOp(), MrsOp::MrsOp(), MsrImmOp::MsrImmOp(), MsrRegOp::MsrRegOp(), RegImmImmOp::RegImmImmOp(), RegImmOp::RegImmOp(), RegImmRegOp::RegImmRegOp(), RegImmRegShiftOp::RegImmRegShiftOp(), RegMiscRegImmOp::RegMiscRegImmOp(), X86ISA::RegOp::RegOp(), RegOp::RegOp(), X86ISA::RegOpImm::RegOpImm(), RegRegImmImmOp::RegRegImmImmOp(), RegRegImmOp::RegRegImmOp(), RegRegOp::RegRegOp(), RegRegRegImmOp::RegRegRegImmOp(), RegRegRegOp::RegRegRegOp(), RegRegRegRegOp::RegRegRegRegOp(), X86ISA::I386LinuxProcess::syscall(), UnknownOp::UnknownOp(), and X86ISA::X86StaticInst::X86StaticInst().
| Bitfield< 4 > X86ISA::pcd |
Definition at line 148 of file pagetable.hh.
| Bitfield<0> X86ISA::pe |
Definition at line 606 of file misc.hh.
Referenced by EtherLink::Link::serialize().
| Bitfield< 2 > X86ISA::pf |
Definition at line 552 of file misc.hh.
Referenced by MultiPrefetcher::getPacket(), Cache::handleTimingReqMiss(), MultiPrefetcher::nextPrefetchReadyTime(), ComputeUnit::DTLBPort::recvTimingResp(), and MultiPrefetcher::setCache().
| const uint64_t X86ISA::PFHandlerVirtAddr = 0xffff800000005000 |
Definition at line 72 of file system.hh.
Referenced by X86ISA::X86_64Process::initState().
| X86ISA::physAddr |
Definition at line 833 of file misc.hh.
Referenced by TraceCPU::ElasticDataGen::GraphNode::writeElementAsTrace().
| const Addr X86ISA::PhysAddrAPICRangeSize = 1 << 12 |
Definition at line 78 of file x86_traits.hh.
Referenced by X86ISA::Interrupts::getIntAddrRange(), and x86InterruptAddress().
Definition at line 75 of file x86_traits.hh.
Definition at line 72 of file x86_traits.hh.
Referenced by X86ISA::TLB::translateInt(), and X86ISA::GpuTLB::translateInt().
Definition at line 74 of file x86_traits.hh.
Definition at line 73 of file x86_traits.hh.
Referenced by X86ISA::TLB::translateInt(), and X86ISA::GpuTLB::translateInt().
| Bitfield< 0 > X86ISA::present |
Definition at line 994 of file misc.hh.
Referenced by X86ISA::Walker::WalkerState::name(), X86ISA::Walker::WalkerState::pageFault(), X86ISA::PageFault::PageFault(), PersistentTable::persistentRequestLock(), and X86ISA::LongModePTE::reset().
| Bitfield<7> X86ISA::prot |
Definition at line 584 of file misc.hh.
Referenced by mmap2Func(), socketFunc(), and socketpairFunc().
| Bitfield<7> X86ISA::ps |
Definition at line 145 of file pagetable.hh.
| Bitfield< 3 > X86ISA::pwt |
Definition at line 149 of file pagetable.hh.
| X86ISA::R |
Definition at line 51 of file int.hh.
Referenced by SC_MODULE().
| Bitfield< 2 > X86ISA::r |
Definition at line 936 of file misc.hh.
Referenced by X86ISA::RemoteGDB::X86GdbRegCache::getRegs(), X86ISA::RemoteGDB::AMD64GdbRegCache::getRegs(), X86ISA::RemoteGDB::X86GdbRegCache::setRegs(), and X86ISA::RemoteGDB::AMD64GdbRegCache::setRegs().
| const uint8_t X86ISA::RE = Rep |
Definition at line 55 of file decoder_tables.cc.
Referenced by SC_MODULE().
| Bitfield<5,3> X86ISA::reg |
Definition at line 89 of file types.hh.
Referenced by Trace::TarmacTracerRecordV8::addRegEntry(), Trace::TarmacTracerRecord::addRegEntry(), SimpleFreeList::addRegs(), RegAddrOperand< RegOperandType >::calcLane(), RegAddrOperand< RegOperandType >::calcVector(), Minor::Scoreboard::canInstIssue(), ArmISA::canReadAArch64SysReg(), ArmISA::canReadCoprocReg(), ArmISA::canWriteAArch64SysReg(), ArmISA::canWriteCoprocReg(), Minor::Scoreboard::clearInstDests(), HsailISA::decodeBr(), HsailISA::decodeBrn(), HsailISA::decodeCbr(), MipsISA::StackTrace::decodePrologue(), X86ISA::StackTrace::decodePrologue(), AlphaISA::StackTrace::decodePrologue(), RegAddrOperand< RegOperandType >::disassemble(), ArmV8KvmCPU::dump(), TimingExprReadIntReg::eval(), Minor::Scoreboard::execSeqNumToWaitFor(), findRegDataType(), RiscvISA::ISA::flattenCCIndex(), PowerISA::ISA::flattenCCIndex(), X86ISA::ISA::flattenCCIndex(), AlphaISA::ISA::flattenCCIndex(), MipsISA::ISA::flattenCCIndex(), SparcISA::ISA::flattenCCIndex(), ArmISA::ISA::flattenCCIndex(), RiscvISA::ISA::flattenFloatIndex(), X86ISA::ISA::flattenFloatIndex(), PowerISA::ISA::flattenFloatIndex(), AlphaISA::ISA::flattenFloatIndex(), MipsISA::ISA::flattenFloatIndex(), SparcISA::ISA::flattenFloatIndex(), ArmISA::ISA::flattenFloatIndex(), RiscvISA::ISA::flattenIntIndex(), PowerISA::ISA::flattenIntIndex(), AlphaISA::ISA::flattenIntIndex(), MipsISA::ISA::flattenIntIndex(), SparcISA::ISA::flattenIntIndex(), ArmISA::ISA::flattenIntIndex(), RiscvISA::ISA::flattenMiscIndex(), PowerISA::ISA::flattenMiscIndex(), X86ISA::ISA::flattenMiscIndex(), AlphaISA::ISA::flattenMiscIndex(), MipsISA::ISA::flattenMiscIndex(), SparcISA::ISA::flattenMiscIndex(), ArmISA::ISA::flattenMiscIndex(), RiscvISA::ISA::flattenVecElemIndex(), PowerISA::ISA::flattenVecElemIndex(), X86ISA::ISA::flattenVecElemIndex(), AlphaISA::ISA::flattenVecElemIndex(), MipsISA::ISA::flattenVecElemIndex(), SparcISA::ISA::flattenVecElemIndex(), ArmISA::ISA::flattenVecElemIndex(), RiscvISA::ISA::flattenVecIndex(), PowerISA::ISA::flattenVecIndex(), X86ISA::ISA::flattenVecIndex(), AlphaISA::ISA::flattenVecIndex(), MipsISA::ISA::flattenVecIndex(), SparcISA::ISA::flattenVecIndex(), ArmISA::ISA::flattenVecIndex(), RiscvISA::ISA::flattenVecPredIndex(), PowerISA::ISA::flattenVecPredIndex(), X86ISA::ISA::flattenVecPredIndex(), AlphaISA::ISA::flattenVecPredIndex(), MipsISA::ISA::flattenVecPredIndex(), SparcISA::ISA::flattenVecPredIndex(), ArmISA::ISA::flattenVecPredIndex(), MrsOp::generateDisassembly(), GuestABI::Argument< DefaultSyscallABI, Arg, typename std::enable_if< std::is_pointer< Arg >::value >::type >::get(), KvmKernelGicV2::getGicReg(), X86ISA::Interrupts::getPort(), PhysRegFile::getRegElemIds(), ArmV8KvmCPU::getSysRegMap(), SimpleThread::getWritableVecPredRegFlat(), Minor::ExecContext::getWritableVecPredRegOperand(), CheckerCPU::getWritableVecPredRegOperand(), SimpleExecContext::getWritableVecPredRegOperand(), SimpleThread::getWritableVecRegFlat(), Minor::ExecContext::getWritableVecRegOperand(), CheckerCPU::getWritableVecRegOperand(), SimpleExecContext::getWritableVecRegOperand(), RegAddrOperand< RegOperandType >::init(), PowerISA::PowerStaticInst::insertCRField(), ArmISA::intRegInMode(), ArmISA::MacroMemOp::MacroMemOp(), ArmISA::makeSP(), ArmISA::makeZero(), Minor::Scoreboard::markupInstDests(), ArmISA::TableWalker::memAttrsLPAE(), X86ISA::X86StaticInst::merge(), Trace::TarmacTracerRecord::mergeCCEntry(), CustomNoMaliGpu::onReset(), Net::EthAddr::operator uint64_t(), ArmISA::preUnflattenMiscReg(), MsrBase::printMsrBase(), EnergyCtrl::read(), X86ISA::Interrupts::read(), Sinic::Device::read(), NSGigE::read(), CheckerCPU::readCCRegOperand(), SimpleExecContext::readCCRegOperand(), Minor::ExecContext::readCCRegOperand(), Iris::ThreadContext::readFloatReg(), Minor::ExecContext::readFloatRegOperandBits(), SimpleExecContext::readFloatRegOperandBits(), CheckerCPU::readFloatRegOperandBits(), Minor::ExecContext::readIntRegOperand(), SimpleExecContext::readIntRegOperand(), CheckerCPU::readIntRegOperand(), ArmISA::ISA::readMiscRegNoEffect(), BaseO3DynInst< Impl >::readMiscRegOperand(), Minor::ExecContext::readMiscRegOperand(), SimpleExecContext::readMiscRegOperand(), CheckerCPU::readMiscRegOperand(), X86ISA::Interrupts::readReg(), X86ISA::Cmos::readRegister(), MipsISA::readRegOtherThread(), CheckerCPU::readVec16BitLaneOperand(), Minor::ExecContext::readVec16BitLaneOperand(), SimpleThread::readVec16BitLaneReg(), CheckerCPU::readVec32BitLaneOperand(), Minor::ExecContext::readVec32BitLaneOperand(), SimpleThread::readVec32BitLaneReg(), CheckerCPU::readVec64BitLaneOperand(), Minor::ExecContext::readVec64BitLaneOperand(), SimpleThread::readVec64BitLaneReg(), CheckerCPU::readVec8BitLaneOperand(), Minor::ExecContext::readVec8BitLaneOperand(), SimpleThread::readVec8BitLaneReg(), SimpleThread::readVecElemFlat(), Minor::ExecContext::readVecElemOperand(), CheckerCPU::readVecElemOperand(), SimpleExecContext::readVecElemOperand(), SimpleThread::readVecLaneFlat(), SimpleExecContext::readVecLaneOperand(), Iris::ThreadContext::readVecPredReg(), SimpleThread::readVecPredRegFlat(), Minor::ExecContext::readVecPredRegOperand(), CheckerCPU::readVecPredRegOperand(), SimpleExecContext::readVecPredRegOperand(), Iris::ThreadContext::readVecReg(), SimpleThread::readVecRegFlat(), Minor::ExecContext::readVecRegOperand(), CheckerCPU::readVecRegOperand(), SimpleExecContext::readVecRegOperand(), Minor::Scoreboard::Scoreboard(), Sinic::Device::serialize(), PhysRegFile::setCCReg(), SimpleExecContext::setCCRegOperand(), CheckerCPU::setCCRegOperand(), Minor::ExecContext::setCCRegOperand(), Minor::ExecContext::setFloatRegOperandBits(), SimpleExecContext::setFloatRegOperandBits(), CheckerCPU::setFloatRegOperandBits(), KvmKernelGicV2::setGicReg(), SimpleExecContext::setIntRegOperand(), Minor::ExecContext::setIntRegOperand(), CheckerCPU::setIntRegOperand(), ArmISA::ISA::setMiscRegNoEffect(), BaseO3DynInst< Impl >::setMiscRegOperand(), Minor::ExecContext::setMiscRegOperand(), SimpleExecContext::setMiscRegOperand(), CheckerCPU::setMiscRegOperand(), X86ISA::Interrupts::setReg(), X86ISA::Interrupts::setRegNoEffect(), MipsISA::setRegOtherThread(), SimpleThread::setVecElemFlat(), Minor::ExecContext::setVecElemOperand(), SimpleExecContext::setVecElemOperand(), CheckerCPU::setVecElemOperand(), SimpleThread::setVecLaneFlat(), CheckerCPU::setVecLaneOperandT(), Minor::ExecContext::setVecLaneOperandT(), SimpleExecContext::setVecLaneOperandT(), SimpleThread::setVecPredRegFlat(), Minor::ExecContext::setVecPredRegOperand(), SimpleExecContext::setVecPredRegOperand(), CheckerCPU::setVecPredRegOperand(), SimpleThread::setVecRegFlat(), Minor::ExecContext::setVecRegOperand(), SimpleExecContext::setVecRegOperand(), CheckerCPU::setVecRegOperand(), ArmISA::snsBankedIndex(), ArmISA::ISA::snsBankedIndex64(), stringToRegister(), ArmISA::unflattenMiscReg(), Sinic::Device::unserialize(), ArmV8KvmCPU::updateKvmState(), ArmKvmCPU::updateKvmStateCoProc(), ArmKvmCPU::updateTCStateCoProc(), ArmV8KvmCPU::updateThreadContext(), EnergyCtrl::write(), X86ISA::Interrupts::write(), NSGigE::write(), X86ISA::Cmos::writeRegister(), X86ISA::X86StaticInst::X86StaticInst(), MC146818::~MC146818(), and ThreadContext::~ThreadContext().
| const int X86ISA::ReturnAddressReg = 0 |
Definition at line 89 of file registers.hh.
Referenced by X86ISA::StackTrace::decodePrologue().
| const int X86ISA::ReturnValueReg = INTREG_RAX |
Definition at line 90 of file registers.hh.
| Bitfield<2,0> X86ISA::rm |
Definition at line 90 of file types.hh.
Referenced by X86ISA::EmulEnv::doModRM().
| const uint8_t X86ISA::RN = Repne |
Definition at line 56 of file decoder_tables.cc.
| const uint8_t X86ISA::RX = RexPrefix |
Definition at line 57 of file decoder_tables.cc.
| Bitfield<44> X86ISA::s |
Definition at line 929 of file misc.hh.
Referenced by Float16::Float16(), and Float16::operator float().
| X86ISA::scale |
Definition at line 94 of file types.hh.
Referenced by sc_dt::sc_fxval_fast::from_string(), MultiperspectivePerceptron::BLURRYPATH::getHash(), sc_dt::quantization(), sc_dt::scfx_print_exp(), ArmISA::vfpSFixedToFpD(), ArmISA::vfpSFixedToFpS(), ArmISA::vfpUFixedToFpD(), ArmISA::vfpUFixedToFpS(), and X86ISA::X86StaticInst::X86StaticInst().
| Bitfield<2,0> X86ISA::seg |
Definition at line 84 of file types.hh.
Referenced by MemoryImage::addSegments(), AoutObject::buildImage(), EcoffObject::buildImage(), MemoryImage::contains(), ElfObject::ElfObject(), X86ISA::X86_64Process::initState(), X86ISA::I386Process::initState(), X86ISA::InitInterrupt::invoke(), MemoryImage::maxAddr(), MemoryImage::minAddr(), MemoryImage::move(), X86ISA::GpuTLB::tlbLookup(), X86ISA::TLB::translate(), X86ISA::GpuTLB::translate(), and MemoryImage::write().
| const Request::FlagsType M5_VAR_USED X86ISA::SegmentFlagMask = mask(4) |
Definition at line 51 of file ldstflags.hh.
Referenced by X86ISA::GpuTLB::tlbLookup(), X86ISA::TLB::translate(), and X86ISA::GpuTLB::translate().
| Bitfield< 7 > X86ISA::sf |
Definition at line 547 of file misc.hh.
Referenced by ArmISA::DataAbort::annotate(), ArmISA::DataAbort::iss(), and AnnotateDumpCallback::process().
| Bitfield<15, 3> X86ISA::si |
Definition at line 862 of file misc.hh.
Referenced by X86ISA::Decoder::decode().
| const uint8_t X86ISA::SS = SSOverride |
Definition at line 50 of file decoder_tables.cc.
| Bitfield<17, 16> X86ISA::stack |
Definition at line 589 of file misc.hh.
Referenced by MipsISA::StackTrace::getstack(), X86ISA::StackTrace::getstack(), AlphaISA::StackTrace::getstack(), RiscvISA::StackTrace::getstack(), PowerISA::StackTrace::getstack(), ArmISA::StackTrace::getstack(), and setupAltStack().
| const int X86ISA::StackPointerReg = INTREG_RSP |
Definition at line 87 of file registers.hh.
Referenced by X86Linux::archClone(), and X86ISA::X86Process::argsInit().
| const uint64_t X86ISA::syscallCodeVirtAddr = 0xffff800000000000 |
Definition at line 66 of file system.hh.
Referenced by X86ISA::X86_64Process::initState().
| const int X86ISA::SyscallPseudoReturnReg = INTREG_RDX |
Definition at line 95 of file registers.hh.
| Bitfield<15> X86ISA::system |
Definition at line 999 of file misc.hh.
Referenced by dumpDmesgEntry(), exitImpl(), SimpleThread::getSystemPtr(), ArmISA::ISA::initializeMiscRegMetadata(), MultiLevelPageTable< EntryTypes >::initState(), Iob::Iob(), MultiLevelPageTable< EntryTypes >::map(), sc_gem5::Gem5ToTlmBridge< BITWIDTH >::nb_transport_bw(), Iris::ThreadContext::noThrow(), RealViewTemperatureSensor::read(), sc_gem5::Gem5ToTlmBridge< BITWIDTH >::recvTimingReq(), MultiLevelPageTable< EntryTypes >::remap(), and MultiLevelPageTable< EntryTypes >::unmap().
| Bitfield<8> X86ISA::tf |
Definition at line 571 of file misc.hh.
Referenced by sc_core::sc_close_vcd_trace_file(), sc_core::sc_create_vcd_trace_file(), sc_core::sc_trace(), sc_core::sc_trace_delta_cycles(), sc_core::sc_write_comment(), and sc_gem5::Scheduler::trace().
| Bitfield< 15 > X86ISA::trigger |
Definition at line 50 of file intmessage.hh.
Referenced by PIFPrefetcher::CompactorEntry::CompactorEntry(), PIFPrefetcher::CompactorEntry::distanceFromTrigger(), PIFPrefetcher::CompactorEntry::getPredictedAddresses(), PIFPrefetcher::CompactorEntry::hasAddress(), and PIFPrefetcher::CompactorEntry::inSameSpatialRegion().
|
static |
Definition at line 78 of file intmessage.hh.
| const uint64_t X86ISA::TSSVirtAddr = 0xffff800000003000 |
Definition at line 69 of file system.hh.
Referenced by X86ISA::X86_64Process::initState().
| Bitfield< 43, 40 > X86ISA::type |
Definition at line 729 of file misc.hh.
Referenced by X86ISA::IntelMP::BaseConfigEntry::writeOut().
| Bitfield<2> X86ISA::u |
Definition at line 150 of file pagetable.hh.
| Bitfield<16> X86ISA::usr |
Definition at line 804 of file misc.hh.
Referenced by NoMaliGpu::panicOnErr().
| const uint8_t X86ISA::V2 = Vex2Prefix |
Definition at line 58 of file decoder_tables.cc.
| const uint8_t X86ISA::V3 = Vex3Prefix |
Definition at line 59 of file decoder_tables.cc.
| Bitfield<63> X86ISA::val |
Definition at line 771 of file misc.hh.
Referenced by alignToPowerOfTwo(), ArmISA::AbortFault< DataAbort >::annotate(), ArmISA::DataAbort::annotate(), ArmISA::ISA::assert64(), bitsToFloat32(), bitsToFloat64(), ArmISA::bitsToFp(), BitfieldBackend::BitUnionOperators< Base >::BitUnionOperators(), MipsISA::buildRetPC(), FastModel::CortexA76::clockPeriodUpdated(), ArchTimer::compareValue(), composeBitVector(), MultiperspectivePerceptron::computeOutput(), sc_dt::sc_uint_subref_r::concat_get_data(), sc_dt::sc_int_subref_r::concat_get_data(), sc_dt::sc_uint_base::concat_get_data(), sc_dt::sc_int_base::concat_get_data(), sc_dt::sc_int_subref_r::concat_get_uint64(), MuxingKvmGic::copyCpuRegister(), MuxingKvmGic::copyDistRegister(), ArmISA::ArmStaticInst::cSwap(), ArmISA::DataAbort::DataAbort(), Stats::StatStor::dec(), Stats::AvgStor::dec(), GenericISA::DelaySlotPCState< MachInst >::DelaySlotPCState(), GenericISA::DelaySlotUPCState< MachInst >::DelaySlotUPCState(), PerfKvmCounterConfig::disabled(), ArmV8KvmCPU::dump(), ArmISA::EndBitUnion(), PerfKvmCounterConfig::exclude_host(), PerfKvmCounterConfig::exclude_hv(), HsailISA::LdInst< MemDataType, DestDataType, AddrOperandType >::execute(), MipsISA::ISA::filterCP0Write(), findLsbSet(), ArmISA::fixDest(), ArmISA::fixDivDest(), ArmISA::fixFpDFpSDest(), ArmISA::fixFpSFpDDest(), floatToBits32(), floatToBits64(), ArmISA::fpToBits(), futexFunc(), GenericTimerISA::GenericTimerISA(), Wavefront::getContext(), getExecutingAsid(), TAGEBase::getGHR(), X86ISA::Interrupts::getPort(), getsockoptFunc(), ArmProcess32::getSyscallArg(), SRegOperand::getTarget(), FullO3CPU< O3CPUImpl >::halt(), BloomFilter::H3::hash(), Stats::StatStor::inc(), Stats::AvgStor::inc(), ExecContext::initiateMemAMO(), PseudoInst::initParam(), Trie< Addr, uint32_t >::insert(), PowerISA::FloatOp::isNan(), SparcISA::ISA::isNonPriv(), RiscvISA::isquietnan< double >(), RiscvISA::isquietnan< float >(), ArmISA::AbortFault< DataAbort >::iss(), ArmISA::DataAbort::iss(), RiscvISA::issignalingnan< double >(), RiscvISA::issignalingnan< float >(), ArmISA::AbortFault< DataAbort >::isStage2(), sc_core::sc_report::make_warnings_errors(), X86ISA::X86StaticInst::merge(), GenericISA::PCStateBase::microPC(), GenericISA::DelaySlotPCState< MachInst >::nnpc(), GenericISA::SimplePCState< MachInst >::npc(), GenericISA::UPCState< MachInst >::nupc(), GenericISA::DelaySlotUPCState< MachInst >::nupc(), sc_dt::sc_uint_subref_r::operator uint_type(), sc_dt::sc_int_subref_r::operator uint_type(), std::hash< BitUnionType< T > >::operator()(), BitfieldTypeImpl< Base >::operator=(), BitfieldBackend::BitUnionOperators< Base >::operator=(), sc_dt::sc_uint_subref::operator=(), sc_dt::sc_int_subref::operator=(), sc_gem5::VcdTraceValTime::output(), sc_gem5::VcdTraceValInt< T >::output(), sc_dt::overflow(), GenericISA::SimplePCState< MachInst >::pc(), X86ISA::PCState::PCState(), DefaultCommit< Impl >::pcState(), O3ThreadContext< Impl >::pcState(), SimpleThread::pcState(), BaseDynInst< Impl >::pcState(), GenericISA::PCStateBase::PCStateBase(), SimpleThread::pcStateNoRecord(), PerfKvmCounterConfig::pinned(), ProbeListenerArgBase< uint64_t >::ProbeListenerArgBase(), IdleStartEvent::process(), CircularQueue< char >::push_back(), sc_dt::quantization(), DistIface::rankParam(), X86ISA::Interrupts::read(), Gicv3Distributor::read(), Iris::ThreadContext::readCCReg(), FastModel::CortexA76TC::readIntRegFlat(), ArmISA::PMU::readMiscReg(), ArmISA::ISA::readMiscReg(), ArmISA::ISA::readMiscRegNoEffect(), X86ISA::Interrupts::readReg(), X86ISA::Cmos::readRegister(), PhysRegFile::readVecElem(), CheckerCPU::recordPCChange(), Trie< Addr, uint32_t >::remove(), Sp804::Timer::restartCounter(), CpuLocalTimer::Timer::restartTimerCounter(), CpuLocalTimer::Timer::restartWatchdogCounter(), MipsISA::roundFP(), ArmISA::roundNEven(), RiscvISA::PCState::rv32(), Stats::DistStor::sample(), Stats::SparseHistStor::sample(), sc_dt::sc_proxy_out_of_bounds(), Flags< FlagsType >< FlagsType >::set(), GenericISA::SimplePCState< MachInst >::set(), SRegOperand::set(), GenericISA::UPCState< MachInst >::set(), DRegOperand::set(), X86ISA::PCState::set(), GenericISA::DelaySlotPCState< MachInst >::set(), CRegOperand::set(), GenericISA::DelaySlotUPCState< MachInst >::set(), Stats::StatStor::set(), Stats::AvgStor::set(), ListOperand::set(), FastModel::CortexA76Cluster::set_evs_param(), Gicv3CPUInterface::setBankedMiscReg(), MipsISA::setCauseIP(), PhysRegFile::setCCReg(), FastModel::CortexA76TC::setCCRegFlat(), Iris::ThreadContext::setCCRegFlat(), SimpleThread::setCCRegFlat(), SimpleExecContext::setCCRegOperand(), CheckerCPU::setCCRegOperand(), Minor::ExecContext::setCCRegOperand(), ArchTimer::setCompareValue(), Wavefront::setContext(), ArchTimer::setControl(), ArmISA::PMU::setCounterTypeRegister(), PhysRegFile::setFloatReg(), SimpleThread::setFloatRegFlat(), Minor::ExecContext::setFloatRegOperandBits(), SimpleExecContext::setFloatRegOperandBits(), CheckerCPU::setFloatRegOperandBits(), SparcISA::ISA::setFSReg(), SystemCounter::setHypControl(), RiscvISA::Interrupts::setIE(), PhysRegFile::setIntReg(), Iris::ThreadContext::setIntReg(), Iris::ThreadContext::setIntRegFlat(), SimpleThread::setIntRegFlat(), SimpleExecContext::setIntRegOperand(), Minor::ExecContext::setIntRegOperand(), CheckerCPU::setIntRegOperand(), RiscvISA::Interrupts::setIP(), AlphaISA::ISA::setIpr(), SystemCounter::setKernelControl(), CallArgMem::setLaneAddr(), Minor::MinorDynInst::setMemAccPredicate(), SimpleThread::setMemAccPredicate(), BaseDynInst< Impl >::setMemAccPredicate(), X86ISA::ISA::setMiscReg(), AlphaISA::ISA::setMiscReg(), ArmISA::PMU::setMiscReg(), BaseO3DynInst< Impl >::setMiscReg(), SparcISA::ISA::setMiscReg(), Gicv3CPUInterface::setMiscReg(), ArmISA::ISA::setMiscReg(), RiscvISA::ISA::setMiscRegNoEffect(), AlphaISA::ISA::setMiscRegNoEffect(), MipsISA::ISA::setMiscRegNoEffect(), SparcISA::ISA::setMiscRegNoEffect(), Iris::ThreadContext::setMiscRegNoEffect(), BaseO3DynInst< Impl >::setMiscRegOperand(), Minor::ExecContext::setMiscRegOperand(), SimpleExecContext::setMiscRegOperand(), CheckerCPU::setMiscRegOperand(), ArchTimer::setOffset(), Trace::InstRecord::setPredicate(), Minor::MinorDynInst::setPredicate(), SimpleThread::setPredicate(), BaseDynInst< Impl >::setPredicate(), SETranslatingPortProxy::setProcess(), X86ISA::Interrupts::setReg(), MipsISA::ISA::setRegMask(), X86ISA::Interrupts::setRegNoEffect(), MipsISA::setRegOtherThread(), SparcProcess::setSyscallReturn(), ArmISA::BaseISADevice::setThreadContext(), ArmISA::PMU::CounterState::setValue(), PhysRegFile::setVecElem(), O3ThreadContext< Impl >::setVecElem(), SimpleThread::setVecElem(), PhysRegFile::setVecLane(), O3ThreadContext< Impl >::setVecLane(), O3ThreadContext< Impl >::setVecLaneFlat(), SimpleThread::setVecLaneT(), PhysRegFile::setVecPredReg(), SimpleThread::setVecPredRegFlat(), PhysRegFile::setVecReg(), SimpleThread::setVecRegFlat(), GenericISA::SimplePCState< MachInst >::SimplePCState(), DistIface::sizeParam(), TEST(), GenericISA::UPCState< MachInst >::upc(), GenericISA::DelaySlotUPCState< MachInst >::upc(), GenericISA::UPCState< MachInst >::UPCState(), Stats::ScalarPrint::update(), MipsISA::ISA::updateCP0ReadView(), Stats::ValueToString(), sc_dt::vec_from_str(), ArmISA::vfpFpToFixed(), X86ISA::Speaker::write(), X86ISA::I8259::write(), AlphaBackdoor::write(), Gicv3Its::write(), CopyEngine::write(), X86ISA::Interrupts::write(), IGbE::write(), Wavefront::writeCallArgMem(), X86ISA::Cmos::writeRegister(), sc_dt::sc_uint_base::xor_reduce(), sc_dt::sc_int_base::xor_reduce(), BaseO3DynInst< Impl >::~BaseO3DynInst(), ArmISA::DummyISADevice::~DummyISADevice(), GpuDispatcher::~GpuDispatcher(), and ThreadContext::~ThreadContext().
| constexpr bool X86ISA::VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr |
Definition at line 110 of file registers.hh.
| constexpr size_t X86ISA::VecPredRegSizeBits = ::DummyVecPredRegSizeBits |
Definition at line 109 of file registers.hh.
| constexpr size_t X86ISA::VecRegSizeBytes = ::DummyVecRegSizeBytes |
Definition at line 103 of file registers.hh.
| X86ISA::vector |
Definition at line 46 of file intmessage.hh.
Referenced by APIC_INTERRUPT_REQUEST(), Iob::receiveDeviceInterrupt(), X86ISA::Interrupts::requestInterrupt(), Iob::serialize(), to_lower(), Iob::unserialize(), and Iob::writeIob().
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static |
| Bitfield< 3 > X86ISA::w |
Definition at line 151 of file pagetable.hh.
| Bitfield<15,0> X86ISA::X |
Definition at line 55 of file int.hh.
Referenced by ArmISA::addPACDA(), ArmISA::addPACDB(), ArmISA::addPACIA(), ArmISA::addPACIB(), ArmISA::authDA(), ArmISA::authDB(), ArmISA::authIA(), ArmISA::authIB(), sc_dt::sc_concref_r< X, Y >::get_cword(), sc_dt::sc_concref_r< X, Y >::get_word(), TAGEBase::handleAllocAndUReset(), sc_dt::sc_proxy< sc_subref_r< X > >::lrotate(), sc_dt::lrotate(), sc_dt::operator&=(), sc_dt::operator==(), sc_dt::sc_proxy< sc_subref_r< X > >::operator>>(), sc_dt::operator^=(), sc_dt::operator|=(), sc_dt::sc_proxy< sc_subref_r< X > >::operator~(), sc_dt::overflow(), sc_dt::sc_proxy< sc_subref_r< X > >::rrotate(), SC_MODULE(), sc_dt::sc_concref_r< X, Y >::set_cword(), sc_dt::sc_concref_r< X, Y >::set_word(), ArmISA::Crypto::sha1H(), ArmISA::Crypto::sha1Op(), ArmISA::Crypto::sha1Su0(), ArmISA::Crypto::sha1Su1(), ArmISA::Crypto::sha256H(), ArmISA::Crypto::sha256H2(), ArmISA::Crypto::sha256Su0(), ArmISA::Crypto::sha256Su1(), ArmISA::Crypto::sigma1(), and ArmISA::upperAndLowerRange().
| Bitfield< 6 > X86ISA::x |
Definition at line 105 of file types.hh.
Referenced by sc_dt::add_mants(), sc_dt::and_on_help(), sc_dt::sc_proxy< sc_subref_r< X > >::assign_(), sc_dt::assign_p_(), sc_dt::assign_v_(), sc_dt::b_and_assign_(), sc_dt::sc_proxy< sc_subref_r< X > >::b_not(), sc_dt::b_or_assign_(), sc_dt::b_xor_assign_(), ArmISA::TLBIOp::broadcast(), ArmISA::TLB::checkPermissions64(), LSQUnit< Impl >::checkSnoop(), sc_dt::scfx_rep::clear(), LSQUnit< Impl >::commitStores(), CopyEngine::CopyEngine(), SparcISA::copyRegs(), SparcISA::TLB::demapAll(), SparcISA::TLB::demapContext(), sc_dt::div_scfx_rep(), SparcISA::TLB::dumpAll(), Stats::Vector2dInfo::enable(), IGbE::DescCache< iGbReg::RxDesc >::fetchComplete(), SparcISA::TLB::flushAll(), ArmISA::TLB::flushAllNs(), ArmISA::TLB::flushAllSecurity(), ArmISA::TLB::flushAsid(), ArmISA::fp16_add(), ArmISA::fp16_div(), ArmISA::fp16_mul(), ArmISA::fp16_muladd(), ArmISA::fp16_sqrt(), ArmISA::fp32_add(), ArmISA::fp32_div(), ArmISA::fp32_mul(), ArmISA::fp32_muladd(), ArmISA::fp32_sqrt(), ArmISA::fp64_add(), ArmISA::fp64_div(), ArmISA::fp64_mul(), ArmISA::fp64_muladd(), ArmISA::fp64_sqrt(), ArmISA::fplibCompareEQ(), ArmISA::fplibCompareGE(), ArmISA::fplibCompareGT(), ArmISA::fplibCompareUN(), ArmISA::fplibMax(), ArmISA::fplibMin(), ArmISA::fplibRoundInt(), ArmISA::FPToFixed_16(), ArmISA::FPToFixed_32(), ArmISA::FPToFixed_64(), sc_dt::scfx_rep::get_bit(), PciDevice::getAddrRanges(), MultiperspectivePerceptron::ACYCLIC::getHash(), MultiperspectivePerceptron::MODHIST::getHash(), MultiperspectivePerceptron::RECENCY::getHash(), MultiperspectivePerceptron::PATH::getHash(), MultiperspectivePerceptron::LOCAL::getHash(), MultiperspectivePerceptron::MODPATH::getHash(), MultiperspectivePerceptron::GHISTPATH::getHash(), MultiperspectivePerceptron::GHISTMODPATH::getHash(), MultiperspectivePerceptron::BLURRYPATH::getHash(), MultiperspectivePerceptron::SGHISTPATH::getHash(), GicV2::GicV2(), Gicv2m::Gicv2m(), X86ISA::GpuTLB::GpuTLB(), tlm::tlm_generic_payload::has_mm(), MultiperspectivePerceptron::GHIST::hash(), MultiperspectivePerceptron::MPPBranchInfo::hashPC(), CPA::hwWe(), IGbE::IGbE(), AlphaISA::initializeIprTable(), SparcISA::TLB::insert(), Iob::Iob(), QTIsaac< ALPHA >::isaac(), ArmISA::TLB::lookup(), sc_dt::sc_proxy< sc_subref_r< X > >::lrotate(), m5_fegetround(), ArmISA::modeConv(), sc_dt::operator&=(), sc_dt::sc_proxy< sc_subref_r< X > >::operator<<=(), sc_dt::operator==(), sc_dt::sc_proxy< sc_subref_r< X > >::operator>>=(), sc_dt::operator^=(), sc_dt::operator|=(), sc_dt::or_on_help(), sc_dt::scfx_rep::overflow(), FrameBuffer::pixel(), power(), SparcISA::SparcStaticInst::printRegArray(), ArmISA::TLB::printTlb(), AnnotateDumpCallback::process(), sc_dt::scfx_rep::quantization(), RangeAddrMapper::RangeAddrMapper(), GicV2::readCpu(), SparcISA::ISA::readFSReg(), IGbE::DescCache< iGbReg::RxDesc >::reset(), sc_dt::sc_proxy< sc_subref_r< X > >::reverse(), QTIsaac< ALPHA >::rngstep(), sc_dt::scfx_rep::round(), sc_dt::sc_proxy< sc_subref_r< X > >::rrotate(), SC_MODULE(), sc_dt::scfx_rep::scfx_rep(), VncServer::sendFrameBufferUpdate(), Iob::serialize(), X86ISA::TLB::serialize(), SparcISA::TLB::serialize(), CopyEngine::serialize(), IGbE::DescCache< iGbReg::RxDesc >::serialize(), Pl111::serialize(), sc_dt::scfx_rep::set(), VncServer::setEncodings(), GicV2::softInt(), sc_dt::sub_mants(), sc_dt::sub_with_index(), swap_byte(), swap_byte16(), swap_byte32(), swap_byte64(), System::System(), TEST(), X86ISA::TLB::TLB(), SparcISA::TLB::TLB(), TsunamiCChip::TsunamiCChip(), Iob::unserialize(), X86ISA::TLB::unserialize(), SparcISA::TLB::unserialize(), CopyEngine::unserialize(), IGbE::DescCache< iGbReg::RxDesc >::unserialize(), Pl111::unserialize(), PhysicalMemory::unserializeStore(), GicV2::updateIntState(), sc_dt::vec_div_large(), sc_dt::vec_rem_large(), VGic::VGic(), SparcISA::vtophys(), IGbE::DescCache< iGbReg::RxDesc >::wbComplete(), PngWriter::write(), BmpWriter::write(), TsunamiCChip::write(), IGbE::DescCache< iGbReg::RxDesc >::writeback1(), sc_dt::xor_on_help(), CopyEngine::~CopyEngine(), GicV2::~GicV2(), mm::~mm(), QTIsaac< ALPHA >::randctx::~randctx(), and VGic::~VGic().
| const int X86ISA::ZeroReg = NUM_INTREGS |
Definition at line 86 of file registers.hh.
Referenced by X86ISA::X86StaticInst::printMem().