ExecContext bears the exec_context interface for Minor. More...

#include <exec_context.hh>

Inheritance diagram for Minor::ExecContext:

Public Member Functions
	ExecContext (MinorCPU &cpu_, SimpleThread &thread_, Execute &execute_, MinorDynInstPtr inst_)

	~ExecContext ()

Fault	initiateMemRead (Addr addr, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >()) override
	Initiate a timing memory read operation. More...

Fault	initiateHtmCmd (Request::Flags flags) override
	Initiate an HTM command, e.g. More...

Fault	writeMem (uint8_t data, unsigned int size, Addr addr, Request::Flags flags, uint64_t res, const std::vector< bool > &byte_enable=std::vector< bool >()) override
	For atomic-mode contexts, perform an atomic memory write operation. More...

Fault	initiateMemAMO (Addr addr, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op) override
	For timing-mode contexts, initiate an atomic AMO (atomic read-modify-write memory operation) More...

RegVal	readIntRegOperand (const StaticInst *si, int idx) override
	Reads an integer register. More...

RegVal	readFloatRegOperandBits (const StaticInst *si, int idx) override
	Reads a floating point register in its binary format, instead of by value. More...

const TheISA::VecRegContainer &	readVecRegOperand (const StaticInst *si, int idx) const override
	Vector Register Interfaces. More...

TheISA::VecRegContainer &	getWritableVecRegOperand (const StaticInst *si, int idx) override
	Gets destination vector register operand for modification. More...

TheISA::VecElem	readVecElemOperand (const StaticInst *si, int idx) const override
	Vector Elem Interfaces. More...

const TheISA::VecPredRegContainer &	readVecPredRegOperand (const StaticInst *si, int idx) const override
	Predicate registers interface. More...

TheISA::VecPredRegContainer &	getWritableVecPredRegOperand (const StaticInst *si, int idx) override
	Gets destination predicate register operand for modification. More...

void	setIntRegOperand (const StaticInst *si, int idx, RegVal val) override
	Sets an integer register to a value. More...

void	setFloatRegOperandBits (const StaticInst *si, int idx, RegVal val) override
	Sets the bits of a floating point register of single width to a binary value. More...

void	setVecRegOperand (const StaticInst *si, int idx, const TheISA::VecRegContainer &val) override

void	setVecPredRegOperand (const StaticInst *si, int idx, const TheISA::VecPredRegContainer &val) override

void	setVecElemOperand (const StaticInst *si, int idx, const TheISA::VecElem val) override
	Sets a vector register to a value. More...

bool	readPredicate () const override

void	setPredicate (bool val) override

bool	readMemAccPredicate () const override

void	setMemAccPredicate (bool val) override

uint64_t	getHtmTransactionUid () const override

uint64_t	newHtmTransactionUid () const override

bool	inHtmTransactionalState () const override

uint64_t	getHtmTransactionalDepth () const override

TheISA::PCState	pcState () const override

void	pcState (const TheISA::PCState &val) override

RegVal	readMiscRegNoEffect (int misc_reg) const

RegVal	readMiscReg (int misc_reg) override
	Reads a miscellaneous register, handling any architectural side effects due to reading that register. More...

void	setMiscReg (int misc_reg, RegVal val) override
	Sets a miscellaneous register, handling any architectural side effects due to writing that register. More...

RegVal	readMiscRegOperand (const StaticInst *si, int idx) override

void	setMiscRegOperand (const StaticInst *si, int idx, RegVal val) override

void	syscall () override
	Executes a syscall. More...

ThreadContext *	tcBase () const override
	Returns a pointer to the ThreadContext. More...

unsigned int	readStCondFailures () const override
	Returns the number of consecutive store conditional failures. More...

void	setStCondFailures (unsigned int st_cond_failures) override
	Sets the number of consecutive store conditional failures. More...

ContextID	contextId ()

void	demapPage (Addr vaddr, uint64_t asn) override
	Invalidate a page in the DTLB and ITLB. More...

RegVal	readCCRegOperand (const StaticInst *si, int idx) override

void	setCCRegOperand (const StaticInst *si, int idx, RegVal val) override

void	demapInstPage (Addr vaddr, uint64_t asn)

void	demapDataPage (Addr vaddr, uint64_t asn)

BaseCPU *	getCpuPtr ()

void	armMonitor (Addr address) override

bool	mwait (PacketPtr pkt) override

void	mwaitAtomic (ThreadContext *tc) override

AddressMonitor *	getAddrMonitor () override


ConstVecLane8	readVec8BitLaneOperand (const StaticInst *si, int idx) const override
	Vector Register Lane Interfaces. More...

ConstVecLane16	readVec16BitLaneOperand (const StaticInst *si, int idx) const override
	Reads source vector 16bit operand. More...

ConstVecLane32	readVec32BitLaneOperand (const StaticInst *si, int idx) const override
	Reads source vector 32bit operand. More...

ConstVecLane64	readVec64BitLaneOperand (const StaticInst *si, int idx) const override
	Reads source vector 64bit operand. More...

template<typename LD >
void	setVecLaneOperandT (const StaticInst *si, int idx, const LD &val)
	Write a lane of the destination vector operand. More...

virtual void	setVecLaneOperand (const StaticInst *si, int idx, const LaneData< LaneSize::Byte > &val) override
	Write a lane of the destination vector operand. More...

virtual void	setVecLaneOperand (const StaticInst *si, int idx, const LaneData< LaneSize::TwoByte > &val) override

virtual void	setVecLaneOperand (const StaticInst *si, int idx, const LaneData< LaneSize::FourByte > &val) override

virtual void	setVecLaneOperand (const StaticInst *si, int idx, const LaneData< LaneSize::EightByte > &val) override

Public Member Functions inherited from ExecContext
virtual void	setVecRegOperand (const StaticInst *si, int idx, const VecRegContainer &val)=0
	Sets a destination vector register operand to a value. More...

virtual void	setVecPredRegOperand (const StaticInst *si, int idx, const VecPredRegContainer &val)=0
	Sets a destination predicate register operand to a value. More...

virtual Fault	readMem (Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >())
	Perform an atomic memory read operation. More...

virtual Fault	amoMem (Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op)
	For atomic-mode contexts, perform an atomic AMO (a.k.a., Atomic Read-Modify-Write Memory Operation) More...

Public Attributes
MinorCPU &	cpu

SimpleThread &	thread
	ThreadState object, provides all the architectural state. More...

Execute &	execute
	The execute stage so we can peek at its contents. More...

MinorDynInstPtr	inst
	Instruction for the benefit of memory operations and for PC. More...

Additional Inherited Members
Public Types inherited from ExecContext
typedef TheISA::PCState	PCState

using	VecRegContainer = TheISA::VecRegContainer

using	VecElem = TheISA::VecElem

using	VecPredRegContainer = TheISA::VecPredRegContainer

Detailed Description

ExecContext bears the exec_context interface for Minor.

This nicely separates that interface from other classes such as Pipeline, MinorCPU and DynMinorInst and makes it easier to see what state is accessed by it.

Definition at line 69 of file exec_context.hh.

Constructor & Destructor Documentation

◆ ExecContext()

Minor::ExecContext::ExecContext	(	MinorCPU &	cpu_,
		SimpleThread &	thread_,
		Execute &	execute_,
		MinorDynInstPtr	inst_
	)

inline

Definition at line 83 of file exec_context.hh.

References DPRINTF, inst, pcState(), SimpleThread::setIntReg(), setMemAccPredicate(), setPredicate(), thread, and ArmISA::ZeroReg.

◆ ~ExecContext()

Minor::ExecContext::~ExecContext ( )

inline

Definition at line 99 of file exec_context.hh.

References inst, readMemAccPredicate(), and readPredicate().

Member Function Documentation

◆ armMonitor()

void Minor::ExecContext::armMonitor ( Addr address )

inlineoverridevirtual

Implements ExecContext.

Definition at line 473 of file exec_context.hh.

References BaseCPU::armMonitor(), getCpuPtr(), and inst.

◆ contextId()

ContextID Minor::ExecContext::contextId ( )

inline

Definition at line 430 of file exec_context.hh.

References SimpleThread::contextId(), and thread.

◆ demapDataPage()

void Minor::ExecContext::demapDataPage	(	Addr	vaddr,
		uint64_t	asn
	)

inline

Definition at line 464 of file exec_context.hh.

References BaseTLB::demapPage(), SimpleThread::getDTBPtr(), thread, and MipsISA::vaddr.

◆ demapInstPage()

void Minor::ExecContext::demapInstPage	(	Addr	vaddr,
		uint64_t	asn
	)

inline

Definition at line 458 of file exec_context.hh.

References BaseTLB::demapPage(), SimpleThread::getITBPtr(), thread, and MipsISA::vaddr.

◆ demapPage()

void Minor::ExecContext::demapPage	(	Addr	vaddr,
		uint64_t	asn
	)

inlineoverridevirtual

Invalidate a page in the DTLB and ITLB.

Implements ExecContext.

Definition at line 435 of file exec_context.hh.

References BaseTLB::demapPage(), SimpleThread::getDTBPtr(), SimpleThread::getITBPtr(), thread, and MipsISA::vaddr.

◆ getAddrMonitor()

AddressMonitor* Minor::ExecContext::getAddrMonitor ( )

inlineoverridevirtual

Implements ExecContext.

Definition at line 482 of file exec_context.hh.

References BaseCPU::getCpuAddrMonitor(), getCpuPtr(), and inst.

◆ getCpuPtr()

BaseCPU* Minor::ExecContext::getCpuPtr ( )

inline

Definition at line 469 of file exec_context.hh.

References cpu.

Referenced by armMonitor(), getAddrMonitor(), mwait(), and mwaitAtomic().

◆ getHtmTransactionalDepth()

uint64_t Minor::ExecContext::getHtmTransactionalDepth ( ) const

inlineoverridevirtual

Implements ExecContext.

Definition at line 369 of file exec_context.hh.

References panic.

◆ getHtmTransactionUid()

uint64_t Minor::ExecContext::getHtmTransactionUid ( ) const

inlineoverridevirtual

Implements ExecContext.

Definition at line 345 of file exec_context.hh.

References panic.

◆ getWritableVecPredRegOperand()

TheISA::VecPredRegContainer& Minor::ExecContext::getWritableVecPredRegOperand	(	const StaticInst *	si,
		int	idx
	)

inlineoverridevirtual

Gets destination predicate register operand for modification.

Implements ExecContext.

Definition at line 192 of file exec_context.hh.

References SimpleThread::getWritableVecPredReg(), X86ISA::reg, ArmISA::si, and thread.

◆ getWritableVecRegOperand()

TheISA::VecRegContainer& Minor::ExecContext::getWritableVecRegOperand	(	const StaticInst *	si,
		int	idx
	)

inlineoverridevirtual

Gets destination vector register operand for modification.

Implements ExecContext.

Definition at line 168 of file exec_context.hh.

References SimpleThread::getWritableVecReg(), X86ISA::reg, ArmISA::si, and thread.

◆ inHtmTransactionalState()

bool Minor::ExecContext::inHtmTransactionalState ( ) const

inlineoverridevirtual

Implements ExecContext.

Definition at line 361 of file exec_context.hh.

◆ initiateHtmCmd()

Fault Minor::ExecContext::initiateHtmCmd ( Request::Flags flags )

inlineoverridevirtual

Initiate an HTM command, e.g.

tell Ruby we're starting/stopping a transaction

Implements ExecContext.

Definition at line 117 of file exec_context.hh.

References NoFault, and panic.

◆ initiateMemAMO()

Fault Minor::ExecContext::initiateMemAMO	(	Addr	addr,
		unsigned int	size,
		Request::Flags	flags,
		AtomicOpFunctorPtr	amo_op
	)

inlineoverridevirtual

For timing-mode contexts, initiate an atomic AMO (atomic read-modify-write memory operation)

Reimplemented from ExecContext.

Definition at line 135 of file exec_context.hh.

References addr, execute, Minor::Execute::getLSQ(), inst, and Minor::LSQ::pushRequest().

◆ initiateMemRead()

Fault Minor::ExecContext::initiateMemRead	(	Addr	addr,
		unsigned int	size,
		Request::Flags	flags,
		const std::vector< bool > &	byte_enable = `std::vector<bool>()`
	)

inlineoverridevirtual

Initiate a timing memory read operation.

Must be overridden for exec contexts that support timing memory mode. Not pure virtual since exec contexts that only support atomic memory mode need not override (though in that case this function should never be called).

Reimplemented from ExecContext.

Definition at line 106 of file exec_context.hh.

References addr, execute, Minor::Execute::getLSQ(), inst, and Minor::LSQ::pushRequest().

◆ mwait()

bool Minor::ExecContext::mwait ( PacketPtr pkt )

inlineoverridevirtual

Implements ExecContext.

Definition at line 476 of file exec_context.hh.

References getCpuPtr(), inst, and BaseCPU::mwait().

◆ mwaitAtomic()

void Minor::ExecContext::mwaitAtomic ( ThreadContext * tc )

inlineoverridevirtual

Implements ExecContext.

Definition at line 479 of file exec_context.hh.

References SimpleThread::dtb, getCpuPtr(), inst, BaseCPU::mwaitAtomic(), and thread.

◆ newHtmTransactionUid()

uint64_t Minor::ExecContext::newHtmTransactionUid ( ) const

inlineoverridevirtual

Implements ExecContext.

Definition at line 353 of file exec_context.hh.

References panic.

◆ pcState() [1/2]

TheISA::PCState Minor::ExecContext::pcState ( ) const

inlineoverridevirtual

Implements ExecContext.

Definition at line 377 of file exec_context.hh.

References SimpleThread::pcState(), and thread.

Referenced by ExecContext().

◆ pcState() [2/2]

void Minor::ExecContext::pcState ( const TheISA::PCState & val )

inlineoverridevirtual

Implements ExecContext.

Definition at line 383 of file exec_context.hh.

References SimpleThread::pcState(), thread, and X86ISA::val.

◆ readCCRegOperand()

RegVal Minor::ExecContext::readCCRegOperand	(	const StaticInst *	si,
		int	idx
	)

inlineoverridevirtual

Implements ExecContext.

Definition at line 442 of file exec_context.hh.

References SimpleThread::readCCReg(), X86ISA::reg, ArmISA::si, and thread.

◆ readFloatRegOperandBits()

RegVal Minor::ExecContext::readFloatRegOperandBits	(	const StaticInst *	si,
		int	idx
	)

inlineoverridevirtual

Reads a floating point register in its binary format, instead of by value.

Implements ExecContext.

Definition at line 152 of file exec_context.hh.

References SimpleThread::readFloatReg(), X86ISA::reg, ArmISA::si, and thread.

◆ readIntRegOperand()

RegVal Minor::ExecContext::readIntRegOperand	(	const StaticInst *	si,
		int	idx
	)

inlineoverridevirtual

Reads an integer register.

Implements ExecContext.

Definition at line 144 of file exec_context.hh.

References SimpleThread::readIntReg(), X86ISA::reg, ArmISA::si, and thread.

◆ readMemAccPredicate()

bool Minor::ExecContext::readMemAccPredicate ( ) const

inlineoverridevirtual

Implements ExecContext.

Definition at line 332 of file exec_context.hh.

References SimpleThread::readMemAccPredicate(), and thread.

Referenced by Minor::Execute::executeMemRefInst(), Minor::Execute::handleMemResponse(), and ~ExecContext().

◆ readMiscReg()

RegVal Minor::ExecContext::readMiscReg ( int misc_reg )

inlineoverridevirtual

Reads a miscellaneous register, handling any architectural side effects due to reading that register.

Implements ExecContext.

Definition at line 395 of file exec_context.hh.

References SimpleThread::readMiscReg(), and thread.

◆ readMiscRegNoEffect()

RegVal Minor::ExecContext::readMiscRegNoEffect ( int misc_reg ) const

inline

Definition at line 389 of file exec_context.hh.

References SimpleThread::readMiscRegNoEffect(), and thread.

◆ readMiscRegOperand()

RegVal Minor::ExecContext::readMiscRegOperand	(	const StaticInst *	si,
		int	idx
	)

inlineoverridevirtual

Implements ExecContext.

Definition at line 407 of file exec_context.hh.

References SimpleThread::readMiscReg(), X86ISA::reg, ArmISA::si, and thread.

◆ readPredicate()

bool Minor::ExecContext::readPredicate ( ) const

inlineoverridevirtual

Implements ExecContext.

Definition at line 320 of file exec_context.hh.

References SimpleThread::readPredicate(), and thread.

Referenced by Minor::Execute::commitInst(), Minor::Execute::executeMemRefInst(), Minor::Execute::handleMemResponse(), and ~ExecContext().

◆ readStCondFailures()

unsigned int Minor::ExecContext::readStCondFailures ( ) const

inlineoverridevirtual

Returns the number of consecutive store conditional failures.

Implements ExecContext.

Definition at line 427 of file exec_context.hh.

◆ readVec16BitLaneOperand()

ConstVecLane16 Minor::ExecContext::readVec16BitLaneOperand	(	const StaticInst *	si,
		int	idx
	)		const

inlineoverridevirtual

Reads source vector 16bit operand.

Implements ExecContext.

Definition at line 247 of file exec_context.hh.

References SimpleThread::readVec16BitLaneReg(), X86ISA::reg, ArmISA::si, and thread.

◆ readVec32BitLaneOperand()

ConstVecLane32 Minor::ExecContext::readVec32BitLaneOperand	(	const StaticInst *	si,
		int	idx
	)		const

inlineoverridevirtual

Reads source vector 32bit operand.

Implements ExecContext.

Definition at line 257 of file exec_context.hh.

References SimpleThread::readVec32BitLaneReg(), X86ISA::reg, ArmISA::si, and thread.

◆ readVec64BitLaneOperand()

ConstVecLane64 Minor::ExecContext::readVec64BitLaneOperand	(	const StaticInst *	si,
		int	idx
	)		const

inlineoverridevirtual

Reads source vector 64bit operand.

Implements ExecContext.

Definition at line 267 of file exec_context.hh.

References SimpleThread::readVec64BitLaneReg(), X86ISA::reg, ArmISA::si, and thread.

◆ readVec8BitLaneOperand()

ConstVecLane8 Minor::ExecContext::readVec8BitLaneOperand	(	const StaticInst *	si,
		int	idx
	)		const

inlineoverridevirtual

Vector Register Lane Interfaces.

Reads source vector 8bit operand.

Implements ExecContext.

Definition at line 237 of file exec_context.hh.

References SimpleThread::readVec8BitLaneReg(), X86ISA::reg, ArmISA::si, and thread.

◆ readVecElemOperand()

TheISA::VecElem Minor::ExecContext::readVecElemOperand	(	const StaticInst *	si,
		int	idx
	)		const

inlineoverridevirtual

Vector Elem Interfaces.

Reads an element of a vector register.

Implements ExecContext.

Definition at line 176 of file exec_context.hh.

References SimpleThread::readVecElem(), X86ISA::reg, ArmISA::si, and thread.

◆ readVecPredRegOperand()

const TheISA::VecPredRegContainer& Minor::ExecContext::readVecPredRegOperand	(	const StaticInst *	si,
		int	idx
	)		const

inlineoverridevirtual

Predicate registers interface.

Reads source predicate register operand.

Implements ExecContext.

Definition at line 184 of file exec_context.hh.

References SimpleThread::readVecPredReg(), X86ISA::reg, ArmISA::si, and thread.

◆ readVecRegOperand()

const TheISA::VecRegContainer& Minor::ExecContext::readVecRegOperand	(	const StaticInst *	si,
		int	idx
	)		const

inlineoverridevirtual

Vector Register Interfaces.

Reads source vector register operand.

Implements ExecContext.

Definition at line 160 of file exec_context.hh.

References SimpleThread::readVecReg(), X86ISA::reg, ArmISA::si, and thread.

◆ setCCRegOperand()

void Minor::ExecContext::setCCRegOperand	(	const StaticInst *	si,
		int	idx,
		RegVal	val
	)

inlineoverridevirtual

Implements ExecContext.

Definition at line 450 of file exec_context.hh.

References X86ISA::reg, SimpleThread::setCCReg(), ArmISA::si, thread, and X86ISA::val.

◆ setFloatRegOperandBits()

void Minor::ExecContext::setFloatRegOperandBits	(	const StaticInst *	si,
		int	idx,
		RegVal	val
	)

inlineoverridevirtual

Sets the bits of a floating point register of single width to a binary value.

Implements ExecContext.

Definition at line 208 of file exec_context.hh.

References X86ISA::reg, SimpleThread::setFloatReg(), ArmISA::si, thread, and X86ISA::val.

◆ setIntRegOperand()

void Minor::ExecContext::setIntRegOperand	(	const StaticInst *	si,
		int	idx,
		RegVal	val
	)

inlineoverridevirtual

Sets an integer register to a value.

Implements ExecContext.

Definition at line 200 of file exec_context.hh.

References X86ISA::reg, SimpleThread::setIntReg(), ArmISA::si, thread, and X86ISA::val.

◆ setMemAccPredicate()

void Minor::ExecContext::setMemAccPredicate ( bool val )

inlineoverridevirtual

Implements ExecContext.

Definition at line 338 of file exec_context.hh.

References SimpleThread::setMemAccPredicate(), thread, and X86ISA::val.

Referenced by Minor::LSQ::LSQRequest::completeDisabledMemAccess(), and ExecContext().

◆ setMiscReg()

void Minor::ExecContext::setMiscReg	(	int	misc_reg,
		RegVal	val
	)

inlineoverridevirtual

Sets a miscellaneous register, handling any architectural side effects due to writing that register.

Implements ExecContext.

Definition at line 401 of file exec_context.hh.

References SimpleThread::setMiscReg(), thread, and X86ISA::val.

◆ setMiscRegOperand()

void Minor::ExecContext::setMiscRegOperand	(	const StaticInst *	si,
		int	idx,
		RegVal	val
	)

inlineoverridevirtual

Implements ExecContext.

Definition at line 415 of file exec_context.hh.

References X86ISA::reg, SimpleThread::setMiscReg(), ArmISA::si, thread, and X86ISA::val.

◆ setPredicate()

void Minor::ExecContext::setPredicate ( bool val )

inlineoverridevirtual

Implements ExecContext.

Definition at line 326 of file exec_context.hh.

References SimpleThread::setPredicate(), thread, and X86ISA::val.

Referenced by ExecContext().

◆ setStCondFailures()

void Minor::ExecContext::setStCondFailures ( unsigned int sc_failures )

inlineoverridevirtual

Sets the number of consecutive store conditional failures.

Implements ExecContext.

Definition at line 428 of file exec_context.hh.

◆ setVecElemOperand()

void Minor::ExecContext::setVecElemOperand	(	const StaticInst *	si,
		int	idx,
		const TheISA::VecElem	val
	)

inlineoverridevirtual

Sets a vector register to a value.

Implements ExecContext.

Definition at line 311 of file exec_context.hh.

References X86ISA::reg, SimpleThread::setVecElem(), ArmISA::si, thread, and X86ISA::val.

◆ setVecLaneOperand() [1/4]

virtual void Minor::ExecContext::setVecLaneOperand	(	const StaticInst *	si,
		int	idx,
		const LaneData< LaneSize::Byte > &	val
	)

inlineoverridevirtual

Write a lane of the destination vector operand.

Implements ExecContext.

Definition at line 285 of file exec_context.hh.

References setVecLaneOperandT(), ArmISA::si, and X86ISA::val.

◆ setVecLaneOperand() [2/4]

virtual void Minor::ExecContext::setVecLaneOperand	(	const StaticInst *	si,
		int	idx,
		const LaneData< LaneSize::EightByte > &	val
	)

inlineoverridevirtual

Implements ExecContext.

Definition at line 303 of file exec_context.hh.

References setVecLaneOperandT(), ArmISA::si, and X86ISA::val.

◆ setVecLaneOperand() [3/4]

virtual void Minor::ExecContext::setVecLaneOperand	(	const StaticInst *	si,
		int	idx,
		const LaneData< LaneSize::FourByte > &	val
	)

inlineoverridevirtual

Implements ExecContext.

Definition at line 297 of file exec_context.hh.

References setVecLaneOperandT(), ArmISA::si, and X86ISA::val.

◆ setVecLaneOperand() [4/4]

virtual void Minor::ExecContext::setVecLaneOperand	(	const StaticInst *	si,
		int	idx,
		const LaneData< LaneSize::TwoByte > &	val
	)

inlineoverridevirtual

Implements ExecContext.

Definition at line 291 of file exec_context.hh.

References setVecLaneOperandT(), ArmISA::si, and X86ISA::val.

◆ setVecLaneOperandT()

template<typename LD >

void Minor::ExecContext::setVecLaneOperandT	(	const StaticInst *	si,
		int	idx,
		const LD &	val
	)

inline

Write a lane of the destination vector operand.

Definition at line 278 of file exec_context.hh.

References X86ISA::reg, SimpleThread::setVecLane(), ArmISA::si, thread, and X86ISA::val.

Referenced by setVecLaneOperand().

◆ setVecPredRegOperand()

void Minor::ExecContext::setVecPredRegOperand	(	const StaticInst *	si,
		int	idx,
		const TheISA::VecPredRegContainer &	val
	)

inlineoverride

Definition at line 225 of file exec_context.hh.

References X86ISA::reg, SimpleThread::setVecPredReg(), ArmISA::si, thread, and X86ISA::val.

◆ setVecRegOperand()

void Minor::ExecContext::setVecRegOperand	(	const StaticInst *	si,
		int	idx,
		const TheISA::VecRegContainer &	val
	)

inlineoverride

Definition at line 216 of file exec_context.hh.

References X86ISA::reg, SimpleThread::setVecReg(), ArmISA::si, thread, and X86ISA::val.

◆ syscall()

void Minor::ExecContext::syscall ( )

inlineoverridevirtual

Executes a syscall.

Implements ExecContext.

Definition at line 422 of file exec_context.hh.

References SimpleThread::syscall(), and thread.

◆ tcBase()

ThreadContext* Minor::ExecContext::tcBase ( ) const

inlineoverridevirtual

Returns a pointer to the ThreadContext.

Implements ExecContext.

Definition at line 424 of file exec_context.hh.

References SimpleThread::getTC(), and thread.

◆ writeMem()

Fault Minor::ExecContext::writeMem	(	uint8_t *	data,
		unsigned int	size,
		Addr	addr,
		Request::Flags	flags,
		uint64_t *	res,
		const std::vector< bool > &	byte_enable = `std::vector< bool >()`
	)

inlineoverridevirtual

For atomic-mode contexts, perform an atomic memory write operation.

For timing-mode contexts, initiate a timing memory write operation.

Implements ExecContext.

Definition at line 124 of file exec_context.hh.

References addr, data, execute, Minor::Execute::getLSQ(), inst, and Minor::LSQ::pushRequest().

Member Data Documentation

◆ cpu

MinorCPU& Minor::ExecContext::cpu

Definition at line 72 of file exec_context.hh.

Referenced by getCpuPtr().

◆ execute

Execute& Minor::ExecContext::execute

The execute stage so we can peek at its contents.

Definition at line 78 of file exec_context.hh.

Referenced by initiateMemAMO(), initiateMemRead(), and writeMem().

◆ inst

MinorDynInstPtr Minor::ExecContext::inst

Instruction for the benefit of memory operations and for PC.

Definition at line 81 of file exec_context.hh.

Referenced by armMonitor(), ExecContext(), getAddrMonitor(), initiateMemAMO(), initiateMemRead(), mwait(), mwaitAtomic(), writeMem(), and ~ExecContext().

◆ thread

SimpleThread& Minor::ExecContext::thread

ThreadState object, provides all the architectural state.

Definition at line 75 of file exec_context.hh.

Referenced by contextId(), demapDataPage(), demapInstPage(), demapPage(), ExecContext(), getWritableVecPredRegOperand(), getWritableVecRegOperand(), mwaitAtomic(), pcState(), readCCRegOperand(), readFloatRegOperandBits(), readIntRegOperand(), readMemAccPredicate(), readMiscReg(), readMiscRegNoEffect(), readMiscRegOperand(), readPredicate(), readVec16BitLaneOperand(), readVec32BitLaneOperand(), readVec64BitLaneOperand(), readVec8BitLaneOperand(), readVecElemOperand(), readVecPredRegOperand(), readVecRegOperand(), setCCRegOperand(), setFloatRegOperandBits(), setIntRegOperand(), setMemAccPredicate(), setMiscReg(), setMiscRegOperand(), setPredicate(), setVecElemOperand(), setVecLaneOperandT(), setVecPredRegOperand(), setVecRegOperand(), syscall(), and tcBase().

The documentation for this class was generated from the following file:

cpu/minor/exec_context.hh

Public Member Functions

Public Attributes

Additional Inherited Members

Detailed Description

Constructor & Destructor Documentation

◆ ExecContext()

◆ ~ExecContext()

Member Function Documentation

◆ armMonitor()

◆ contextId()

◆ demapDataPage()

◆ demapInstPage()

◆ demapPage()

◆ getAddrMonitor()

◆ getCpuPtr()

◆ getHtmTransactionalDepth()

◆ getHtmTransactionUid()

◆ getWritableVecPredRegOperand()

◆ getWritableVecRegOperand()

◆ inHtmTransactionalState()

◆ initiateHtmCmd()

◆ initiateMemAMO()

◆ initiateMemRead()

◆ mwait()

◆ mwaitAtomic()

◆ newHtmTransactionUid()

◆ pcState() [1/2]

◆ pcState() [2/2]

◆ readCCRegOperand()

◆ readFloatRegOperandBits()

◆ readIntRegOperand()

◆ readMemAccPredicate()

◆ readMiscReg()

◆ readMiscRegNoEffect()

◆ readMiscRegOperand()

◆ readPredicate()

◆ readStCondFailures()

◆ readVec16BitLaneOperand()

◆ readVec32BitLaneOperand()

◆ readVec64BitLaneOperand()

◆ readVec8BitLaneOperand()

◆ readVecElemOperand()

◆ readVecPredRegOperand()

◆ readVecRegOperand()

◆ setCCRegOperand()

◆ setFloatRegOperandBits()

◆ setIntRegOperand()

◆ setMemAccPredicate()

◆ setMiscReg()

◆ setMiscRegOperand()

◆ setPredicate()

◆ setStCondFailures()

◆ setVecElemOperand()

◆ setVecLaneOperand() [1/4]

◆ setVecLaneOperand() [2/4]

◆ setVecLaneOperand() [3/4]

◆ setVecLaneOperand() [4/4]

◆ setVecLaneOperandT()

◆ setVecPredRegOperand()

◆ setVecRegOperand()

◆ syscall()

◆ tcBase()

◆ writeMem()

Member Data Documentation

◆ cpu

◆ execute

◆ inst

◆ thread