gem5  v21.2.1.1
cache.hh
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40 
46 #ifndef __MEM_CACHE_CACHE_HH__
47 #define __MEM_CACHE_CACHE_HH__
48 
49 #include <cstdint>
50 #include <unordered_set>
51 
52 #include "base/compiler.hh"
53 #include "base/types.hh"
54 #include "mem/cache/base.hh"
55 #include "mem/packet.hh"
56 
57 namespace gem5
58 {
59 
60 class CacheBlk;
61 struct CacheParams;
62 class MSHR;
63 
67 class Cache : public BaseCache
68 {
69  protected:
73  const bool doFastWrites;
74 
80  std::unordered_set<RequestPtr> outstandingSnoop;
81 
82  protected:
87 
88  bool access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,
89  PacketList &writebacks) override;
90 
91  void handleTimingReqHit(PacketPtr pkt, CacheBlk *blk,
92  Tick request_time) override;
93 
94  void handleTimingReqMiss(PacketPtr pkt, CacheBlk *blk,
95  Tick forward_time,
96  Tick request_time) override;
97 
98  void recvTimingReq(PacketPtr pkt) override;
99 
100  void doWritebacks(PacketList& writebacks, Tick forward_time) override;
101 
102  void doWritebacksAtomic(PacketList& writebacks) override;
103 
104  void serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt,
105  CacheBlk *blk) override;
106 
107  void recvTimingSnoopReq(PacketPtr pkt) override;
108 
109  void recvTimingSnoopResp(PacketPtr pkt) override;
110 
112  PacketList &writebacks) override;
113 
114  Tick recvAtomic(PacketPtr pkt) override;
115 
116  Tick recvAtomicSnoop(PacketPtr pkt) override;
117 
118  void satisfyRequest(PacketPtr pkt, CacheBlk *blk,
119  bool deferred_response = false,
120  bool pending_downgrade = false) override;
121 
122  void doTimingSupplyResponse(PacketPtr req_pkt, const uint8_t *blk_data,
123  bool already_copied, bool pending_inval);
124 
137  uint32_t handleSnoop(PacketPtr pkt, CacheBlk *blk,
138  bool is_timing, bool is_deferred, bool pending_inval);
139 
140  [[nodiscard]] PacketPtr evictBlock(CacheBlk *blk) override;
141 
149 
151  bool needs_writable,
152  bool is_whole_line_write) const override;
153 
158  bool isCachedAbove(PacketPtr pkt, bool is_timing = true);
159 
160  public:
162  Cache(const CacheParams &p);
163 
172  bool sendMSHRQueuePacket(MSHR* mshr) override;
173 };
174 
175 } // namespace gem5
176 
177 #endif // __MEM_CACHE_CACHE_HH__
gem5::MSHR
Miss Status and handling Register.
Definition: mshr.hh:74
base.hh
gem5::Cache::handleAtomicReqMiss
Cycles handleAtomicReqMiss(PacketPtr pkt, CacheBlk *&blk, PacketList &writebacks) override
Handle a request in atomic mode that missed in this cache.
Definition: cache.cc:563
gem5::Cache::sendMSHRQueuePacket
bool sendMSHRQueuePacket(MSHR *mshr) override
Take an MSHR, turn it into a suitable downstream packet, and send it out.
Definition: cache.cc:1359
gem5::Cache::recvAtomic
Tick recvAtomic(PacketPtr pkt) override
Performs the access specified by the request.
Definition: cache.cc:653
gem5::Cache::evictBlock
PacketPtr evictBlock(CacheBlk *blk) override
Evict a cache block.
Definition: cache.cc:900
gem5::Cache::recvTimingSnoopReq
void recvTimingSnoopReq(PacketPtr pkt) override
Snoops bus transactions to maintain coherence.
Definition: cache.cc:1200
gem5::Cache::handleTimingReqMiss
void handleTimingReqMiss(PacketPtr pkt, CacheBlk *blk, Tick forward_time, Tick request_time) override
Definition: cache.cc:324
gem5::Cache::handleSnoop
uint32_t handleSnoop(PacketPtr pkt, CacheBlk *blk, bool is_timing, bool is_deferred, bool pending_inval)
Perform an upward snoop if needed, and update the block state (possibly invalidating the block).
Definition: cache.cc:984
gem5::CacheBlk
A Basic Cache block.
Definition: cache_blk.hh:70
packet.hh
gem5::Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:78
gem5::Cache::recvAtomicSnoop
Tick recvAtomicSnoop(PacketPtr pkt) override
Snoop for the provided request in the cache and return the estimated time taken.
Definition: cache.cc:1318
gem5::Cache::Cache
Cache(const CacheParams &p)
Instantiates a basic cache object.
Definition: cache.cc:69
gem5::BaseCache
A basic cache interface.
Definition: base.hh:95
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::Cache::handleTimingReqHit
void handleTimingReqHit(PacketPtr pkt, CacheBlk *blk, Tick request_time) override
Definition: cache.cc:313
gem5::X86ISA::CacheParams
@ CacheParams
Definition: cpuid.cc:45
gem5::Cache::promoteWholeLineWrites
void promoteWholeLineWrites(PacketPtr pkt)
Turn line-sized writes into WriteInvalidate transactions.
Definition: cache.cc:301
compiler.hh
gem5::Cache::outstandingSnoop
std::unordered_set< RequestPtr > outstandingSnoop
Store the outstanding requests that we are expecting snoop responses from so we can determine which s...
Definition: cache.hh:80
gem5::Cache::serviceMSHRTargets
void serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt, CacheBlk *blk) override
Service non-deferred MSHR targets using the received response.
Definition: cache.cc:684
gem5::Cache
A coherent cache that can be arranged in flexible topologies.
Definition: cache.hh:67
gem5::Cache::cleanEvictBlk
PacketPtr cleanEvictBlk(CacheBlk *blk)
Create a CleanEvict request for the given block.
Definition: cache.cc:911
gem5::Cache::createMissPacket
PacketPtr createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk, bool needs_writable, bool is_whole_line_write) const override
Create an appropriate downstream bus request packet.
Definition: cache.cc:477
gem5::Cache::doWritebacks
void doWritebacks(PacketList &writebacks, Tick forward_time) override
Insert writebacks into the write buffer.
Definition: cache.cc:190
gem5::Cache::recvTimingSnoopResp
void recvTimingSnoopResp(PacketPtr pkt) override
Handle a snoop response.
Definition: cache.cc:267
gem5::Cache::doFastWrites
const bool doFastWrites
This cache should allocate a block on a line-sized write miss.
Definition: cache.hh:73
types.hh
gem5::Cache::satisfyRequest
void satisfyRequest(PacketPtr pkt, CacheBlk *blk, bool deferred_response=false, bool pending_downgrade=false) override
Perform any necessary updates to the block and perform any data exchange between the packet and the b...
Definition: cache.cc:78
gem5::Cache::access
bool access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat, PacketList &writebacks) override
Does all the processing necessary to perform the provided request.
Definition: cache.cc:161
std::list
STL list class.
Definition: stl.hh:51
gem5::Cache::isCachedAbove
bool isCachedAbove(PacketPtr pkt, bool is_timing=true)
Send up a snoop request and find cached copies.
Definition: cache.cc:1331
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::Cache::doWritebacksAtomic
void doWritebacksAtomic(PacketList &writebacks) override
Send writebacks down the memory hierarchy in atomic mode.
Definition: cache.cc:232
gem5::Cache::doTimingSupplyResponse
void doTimingSupplyResponse(PacketPtr req_pkt, const uint8_t *blk_data, bool already_copied, bool pending_inval)
Definition: cache.cc:939
gem5::Cache::recvTimingReq
void recvTimingReq(PacketPtr pkt) override
Performs the access specified by the request.
Definition: cache.cc:403

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