gem5  v21.1.0.2
mshr.hh
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40 
46 #ifndef __MEM_CACHE_MSHR_HH__
47 #define __MEM_CACHE_MSHR_HH__
48 
49 #include <cassert>
50 #include <iosfwd>
51 #include <list>
52 #include <string>
53 #include <vector>
54 
55 #include "base/printable.hh"
56 #include "base/trace.hh"
57 #include "base/types.hh"
58 #include "debug/MSHR.hh"
59 #include "mem/cache/queue_entry.hh"
60 #include "mem/packet.hh"
61 #include "mem/request.hh"
62 #include "sim/cur_tick.hh"
63 
64 namespace gem5
65 {
66 
67 class BaseCache;
68 
74 class MSHR : public QueueEntry, public Printable
75 {
76 
80  template<typename Entry>
81  friend class Queue;
82  friend class MSHRQueue;
83 
84  private:
85 
88 
114 
117 
120 
121  public:
122 
125 
127  bool isForward;
128 
129  class Target : public QueueEntry::Target
130  {
131  public:
132 
133  enum Source
134  {
138  };
139 
140  const Source source;
141 
158 
159  const bool allocOnFill;
160 
162  Target(PacketPtr _pkt, Tick _readyTime, Counter _order,
163  Source _source, bool _markedPending, bool alloc_on_fill)
164  : QueueEntry::Target(_pkt, _readyTime, _order), source(_source),
165  markedPending(_markedPending), allocOnFill(alloc_on_fill)
166  {}
167  };
168 
169  class TargetList : public std::list<Target>, public Named
170  {
171 
172  public:
182 
183  TargetList(const std::string &name = ".unnamedTargetList");
184 
193  void updateFlags(PacketPtr pkt, Target::Source source,
194  bool alloc_on_fill);
195 
202  void init(Addr blk_addr, Addr blk_size) {
203  blkAddr = blk_addr;
204  blkSize = blk_size;
205  writesBitmap.resize(blk_size);
206 
207  resetFlags();
208  }
209 
210  void resetFlags() {
211  canMergeWrites = true;
212  std::fill(writesBitmap.begin(), writesBitmap.end(), false);
213 
214  needsWritable = false;
215  hasUpgrade = false;
216  allocOnFill = false;
217  hasFromCache = false;
218  }
219 
226  void populateFlags();
227 
235  void updateWriteFlags(PacketPtr pkt);
236 
243  bool isReset() const {
244  return !needsWritable && !hasUpgrade && !allocOnFill &&
246  }
247 
261  Target::Source source, bool markPending, bool alloc_on_fill);
262 
267  void replaceUpgrades();
268 
269  void clearDownstreamPending();
270  void clearDownstreamPending(iterator begin, iterator end);
272  void print(std::ostream &os, int verbosity,
273  const std::string &prefix) const;
274 
282  bool isWholeLineWrite() const
283  {
284  return std::all_of(writesBitmap.begin(), writesBitmap.end(),
285  [](bool i) { return i; });
286  }
287 
288  private:
291 
294 
297 
298  // NOTE: std::vector<bool> might not meet satisfy the
299  // ForwardIterator requirement and therefore cannot be used
300  // for writesBitmap.
306  };
307 
311  typedef List::iterator Iterator;
312 
319  bool needsWritable() const { return targets.needsWritable; }
320 
321  bool isCleaning() const {
322  PacketPtr pkt = targets.front().pkt;
323  return pkt->isClean();
324  }
325 
326  bool isPendingModified() const {
327  assert(inService); return pendingModified;
328  }
329 
330  bool hasPostInvalidate() const {
331  assert(inService); return postInvalidate;
332  }
333 
334  bool hasPostDowngrade() const {
335  assert(inService); return postDowngrade;
336  }
337 
338  bool sendPacket(BaseCache &cache) override;
339 
340  bool allocOnFill() const {
341  return targets.allocOnFill;
342  }
343 
349  bool hasFromCache() const {
350  return targets.hasFromCache;
351  }
352 
353  private:
363  void promoteIf(const std::function<bool (Target &)>& pred);
364 
370 
376 
379 
381 
382  public:
390  bool isWholeLineWrite() const {
391  return targets.isWholeLineWrite();
392  }
393 
403  void allocate(Addr blk_addr, unsigned blk_size, PacketPtr pkt,
404  Tick when_ready, Counter _order, bool alloc_on_fill);
405 
406  void markInService(bool pending_modified_resp);
407 
408  void clearDownstreamPending();
409 
413  void deallocate();
414 
419  void allocateTarget(PacketPtr target, Tick when, Counter order,
420  bool alloc_on_fill);
421  bool handleSnoop(PacketPtr target, Counter order);
422 
424  MSHR(const std::string &name);
425 
430  int getNumTargets() const
431  { return targets.size() + deferredTargets.size(); }
432 
445  TargetList extractServiceableTargets(PacketPtr pkt);
446 
451  bool hasTargets() const { return !targets.empty(); }
452 
458  {
459  assert(hasTargets());
460  return &targets.front();
461  }
462 
466  void popTarget()
467  {
468  DPRINTF(MSHR, "Force deallocating MSHR targets: %s\n",
469  targets.front().pkt->print());
470  targets.pop_front();
471  }
472 
473  bool promoteDeferredTargets();
474 
483  void promoteReadable();
484 
492  void promoteWritable();
493 
495 
500  void delay(Tick delay_ticks)
501  {
502  assert(readyTime <= curTick());
503  readyTime = curTick() + delay_ticks;
504  }
505 
509  void print(std::ostream &os,
510  int verbosity = 0,
511  const std::string &prefix = "") const override;
518  std::string print() const;
519 
520  bool matchBlockAddr(const Addr addr, const bool is_secure) const override;
521  bool matchBlockAddr(const PacketPtr pkt) const override;
522  bool conflictAddr(const QueueEntry* entry) const override;
523 };
524 
525 } // namespace gem5
526 
527 #endif // __MEM_CACHE_MSHR_HH__
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
gem5::MSHR
Miss Status and handling Register.
Definition: mshr.hh:74
gem5::MSHR::TargetList::writesBitmap
std::vector< char > writesBitmap
Track which bytes are written by requests in this target list.
Definition: mshr.hh:305
gem5::MSHR::TargetList::isWholeLineWrite
bool isWholeLineWrite() const
Check if this list contains writes that cover an entire cache line.
Definition: mshr.hh:282
gem5::MipsISA::fill
fill
Definition: pra_constants.hh:57
gem5::MSHR::TargetList::replaceUpgrades
void replaceUpgrades()
Convert upgrades to the equivalent request if the cache line they refer to would have been invalid (U...
Definition: mshr.cc:221
gem5::MSHR::TargetList::hasFromCache
bool hasFromCache
Determine whether there was at least one non-snooping target coming from another cache.
Definition: mshr.hh:181
queue_entry.hh
gem5::MSHR::TargetList::print
void print(std::ostream &os, int verbosity, const std::string &prefix) const
Definition: mshr.cc:276
gem5::MSHR::TargetList::updateWriteFlags
void updateWriteFlags(PacketPtr pkt)
Add the specified packet in the TargetList.
Definition: mshr.cc:118
gem5::MSHR::TargetList::TargetList
TargetList(const std::string &name=".unnamedTargetList")
Definition: mshr.cc:73
gem5::MSHR::allocOnFill
bool allocOnFill() const
Definition: mshr.hh:340
gem5::MSHR::isForward
bool isForward
True if the entry is just a simple forward from an upper level.
Definition: mshr.hh:127
gem5::MSHR::promoteIf
void promoteIf(const std::function< bool(Target &)> &pred)
Promotes deferred targets that satisfy a predicate.
Definition: mshr.cc:620
gem5::MSHR::pendingModified
bool pendingModified
Here we use one flag to track both if:
Definition: mshr.hh:113
gem5::MSHR::TargetList::add
void add(PacketPtr pkt, Tick readyTime, Counter order, Target::Source source, bool markPending, bool alloc_on_fill)
Add the specified packet in the TargetList.
Definition: mshr.cc:163
gem5::MSHR::matchBlockAddr
bool matchBlockAddr(const Addr addr, const bool is_secure) const override
Check if entry corresponds to the one being looked for.
Definition: mshr.cc:746
cur_tick.hh
gem5::MSHR::hasPostInvalidate
bool hasPostInvalidate() const
Definition: mshr.hh:330
gem5::MSHR::promoteDeferredTargets
bool promoteDeferredTargets()
Definition: mshr.cc:581
gem5::MSHR::promoteWritable
void promoteWritable()
Promotes deferred targets that do not require writable.
Definition: mshr.cc:664
gem5::MSHR::postInvalidate
bool postInvalidate
Did we snoop an invalidate while waiting for data?
Definition: mshr.hh:116
gem5::MSHR::TargetList::blkSize
Addr blkSize
Size of the cache block.
Definition: mshr.hh:293
gem5::MSHR::TargetList::canMergeWrites
bool canMergeWrites
Indicates whether we can merge incoming write requests.
Definition: mshr.hh:296
gem5::QueueEntry::Target
A queue entry is holding packets that will be serviced as soon as resources are available.
Definition: queue_entry.hh:87
std::vector< char >
gem5::MSHR::postDowngrade
bool postDowngrade
Did we snoop a read while waiting for data?
Definition: mshr.hh:119
gem5::MSHR::markInService
void markInService(bool pending_modified_resp)
Definition: mshr.cc:343
gem5::MSHR::sendPacket
bool sendPacket(BaseCache &cache) override
Send this queue entry as a downstream packet, with the exact behaviour depending on the specific entr...
Definition: mshr.cc:706
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::MSHR::TargetList::clearDownstreamPending
void clearDownstreamPending()
Definition: mshr.cc:256
request.hh
gem5::QueueEntry::order
Counter order
Order number assigned to disambiguate writes and misses.
Definition: queue_entry.hh:113
printable.hh
gem5::QueueEntry::readyTime
Tick readyTime
Tick when ready to issue.
Definition: queue_entry.hh:74
packet.hh
gem5::MSHR::TargetList::populateFlags
void populateFlags()
Goes through the list of targets and uses them to populate the flags of this TargetList.
Definition: mshr.cc:109
gem5::Named
Interface for things with names.
Definition: named.hh:38
gem5::MSHR::allocIter
Iterator allocIter
Pointer to this MSHR on the allocated list.
Definition: mshr.hh:375
gem5::MSHR::TargetList::hasUpgrade
bool hasUpgrade
Definition: mshr.hh:174
gem5::MSHR::Target::FromCPU
@ FromCPU
Definition: mshr.hh:135
gem5::Printable
Abstract base class for objects which support being printed to a stream for debugging.
Definition: printable.hh:47
gem5::MSHR::allocateTarget
void allocateTarget(PacketPtr target, Tick when, Counter order, bool alloc_on_fill)
Add a request to the list of targets.
Definition: mshr.cc:376
gem5::MSHR::readyIter
Iterator readyIter
Pointer to this MSHR on the ready list.
Definition: mshr.hh:369
gem5::Named::name
virtual std::string name() const
Definition: named.hh:47
gem5::MSHR::needsWritable
bool needsWritable() const
The pending* and post* flags are only valid if inService is true.
Definition: mshr.hh:319
gem5::BaseCache
A basic cache interface.
Definition: base.hh:95
gem5::MSHR::TargetList::resetFlags
void resetFlags()
Definition: mshr.hh:210
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::MSHR::popTarget
void popTarget()
Pop first target.
Definition: mshr.hh:466
gem5::MSHR::List
std::list< MSHR * > List
A list of MSHRs.
Definition: mshr.hh:309
gem5::MSHR::isPendingModified
bool isPendingModified() const
Definition: mshr.hh:326
gem5::MSHR::Target::source
const Source source
Request from cpu, memory, or prefetcher?
Definition: mshr.hh:140
gem5::MSHR::Target::allocOnFill
const bool allocOnFill
Should the response servicing this target list allocate in the cache?
Definition: mshr.hh:159
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::MSHR::Target
Definition: mshr.hh:129
gem5::MSHR::TargetList::init
void init(Addr blk_addr, Addr blk_size)
Reset state.
Definition: mshr.hh:202
gem5::MSHR::TargetList::updateFlags
void updateFlags(PacketPtr pkt, Target::Source source, bool alloc_on_fill)
Use the provided packet and the source to update the flags of this TargetList.
Definition: mshr.cc:81
gem5::MSHR::print
std::string print() const
A no-args wrapper of print(std::ostream...) meant to be invoked from DPRINTFs avoiding string overhea...
Definition: mshr.cc:738
gem5::MSHR::isWholeLineWrite
bool isWholeLineWrite() const
Check if this MSHR contains only compatible writes, and if they span the entire cache line.
Definition: mshr.hh:390
gem5::Queue
A high-level queue interface, to be used by both the MSHR queue and the write buffer.
Definition: queue.hh:70
gem5::MSHR::downstreamPending
bool downstreamPending
Flag set by downstream caches.
Definition: mshr.hh:87
gem5::MSHR::hasFromCache
bool hasFromCache() const
Determine if there are non-deferred requests from other caches.
Definition: mshr.hh:349
gem5::MSHR::TargetList
Definition: mshr.hh:169
gem5::MSHR::wasWholeLineWrite
bool wasWholeLineWrite
Track if we sent this as a whole line write or not.
Definition: mshr.hh:124
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::MSHR::deferredTargets
TargetList deferredTargets
Definition: mshr.hh:380
gem5::MSHR::TargetList::trySatisfyFunctional
bool trySatisfyFunctional(PacketPtr pkt)
Definition: mshr.cc:263
gem5::MSHR::conflictAddr
bool conflictAddr(const QueueEntry *entry) const override
Check if given entry's packets conflict with this' entries packets.
Definition: mshr.cc:760
gem5::MSHR::TargetList::blkAddr
Addr blkAddr
Address of the cache block for this list of targets.
Definition: mshr.hh:290
gem5::MSHR::Target::markedPending
bool markedPending
We use this flag to track whether we have cleared the downstreamPending flag for the MSHR of the cach...
Definition: mshr.hh:157
gem5::MSHR::targets
TargetList targets
List of all requests that match the address.
Definition: mshr.hh:378
gem5::Packet::isClean
bool isClean() const
Definition: packet.hh:600
gem5::MSHR::TargetList::allocOnFill
bool allocOnFill
Set when the response should allocate on fill.
Definition: mshr.hh:176
types.hh
gem5::X86ISA::os
Bitfield< 17 > os
Definition: misc.hh:809
gem5::MSHR::getNumTargets
int getNumTargets() const
Returns the current number of allocated targets.
Definition: mshr.hh:430
gem5::MSHR::Target::Source
Source
Definition: mshr.hh:133
gem5::MSHR::isCleaning
bool isCleaning() const
Definition: mshr.hh:321
gem5::MSHR::trySatisfyFunctional
bool trySatisfyFunctional(PacketPtr pkt)
Definition: mshr.cc:691
gem5::MSHR::Target::FromSnoop
@ FromSnoop
Definition: mshr.hh:136
gem5::MSHR::TargetList::needsWritable
bool needsWritable
Definition: mshr.hh:173
gem5::MSHR::handleSnoop
bool handleSnoop(PacketPtr target, Counter order)
Definition: mshr.cc:423
gem5::statistics::Counter
double Counter
All counters are of 64-bit values.
Definition: types.hh:47
gem5::MSHR::clearDownstreamPending
void clearDownstreamPending()
Definition: mshr.cc:333
gem5::MSHR::promoteReadable
void promoteReadable()
Promotes deferred targets that do not require writable.
Definition: mshr.cc:643
gem5::QueueEntry
A queue entry base class, to be used by both the MSHRs and write-queue entries.
Definition: queue_entry.hh:62
gem5::MSHRQueue
A Class for maintaining a list of pending and allocated memory requests.
Definition: mshr_queue.hh:61
gem5::MSHR::allocate
void allocate(Addr blk_addr, unsigned blk_size, PacketPtr pkt, Tick when_ready, Counter _order, bool alloc_on_fill)
Allocate a miss to this MSHR.
Definition: mshr.cc:303
gem5::MSHR::hasTargets
bool hasTargets() const
Returns true if there are targets left.
Definition: mshr.hh:451
gem5::MSHR::TargetList::isReset
bool isReset() const
Tests if the flags of this TargetList have their default values.
Definition: mshr.hh:243
gem5::MSHR::extractServiceableTargets
TargetList extractServiceableTargets(PacketPtr pkt)
Extracts the subset of the targets that can be serviced given a received response.
Definition: mshr.cc:547
gem5::MSHR::deallocate
void deallocate()
Mark this MSHR as free.
Definition: mshr.cc:364
trace.hh
gem5::MSHR::Target::FromPrefetcher
@ FromPrefetcher
Definition: mshr.hh:137
gem5::MSHR::Target::Target
Target(PacketPtr _pkt, Tick _readyTime, Counter _order, Source _source, bool _markedPending, bool alloc_on_fill)
Definition: mshr.hh:162
std::list
STL list class.
Definition: stl.hh:51
gem5::MSHR::MSHR
MSHR(const std::string &name)
A simple constructor.
Definition: mshr.cc:62
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::MSHR::hasPostDowngrade
bool hasPostDowngrade() const
Definition: mshr.hh:334
gem5::MSHR::getTarget
QueueEntry::Target * getTarget() override
Returns a reference to the first target.
Definition: mshr.hh:457
gem5::MSHR::delay
void delay(Tick delay_ticks)
Adds a delay relative to the current tick to the current MSHR.
Definition: mshr.hh:500
gem5::QueueEntry::inService
bool inService
True if the entry has been sent downstream.
Definition: queue_entry.hh:110
gem5::MSHR::Iterator
List::iterator Iterator
MSHR list iterator.
Definition: mshr.hh:311
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84

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