46#ifndef __MEM_CACHE_MSHR_HH__
47#define __MEM_CACHE_MSHR_HH__
58#include "debug/MSHR.hh"
80 template<
typename Entry>
163 Source _source,
bool _markedPending,
bool alloc_on_fill)
272 void print(std::ostream &
os,
int verbosity,
273 const std::string &prefix)
const;
285 [](
bool i) { return i; });
420 Tick when_ready,
Counter _order,
bool alloc_on_fill);
484 DPRINTF(
MSHR,
"Force deallocating MSHR targets: %s\n",
527 const std::string &prefix =
"")
const override;
534 std::string
print()
const;
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,...
A Class for maintaining a list of pending and allocated memory requests.
void updateFlags(PacketPtr pkt, Target::Source source, bool alloc_on_fill)
Use the provided packet and the source to update the flags of this TargetList.
void replaceUpgrades()
Convert upgrades to the equivalent request if the cache line they refer to would have been invalid (U...
void populateFlags()
Goes through the list of targets and uses them to populate the flags of this TargetList.
Addr blkSize
Size of the cache block.
bool trySatisfyFunctional(PacketPtr pkt)
bool isReset() const
Tests if the flags of this TargetList have their default values.
Addr blkAddr
Address of the cache block for this list of targets.
bool allocOnFill
Set when the response should allocate on fill.
std::vector< char > writesBitmap
Track which bytes are written by requests in this target list.
void add(PacketPtr pkt, Tick readyTime, Counter order, Target::Source source, bool markPending, bool alloc_on_fill)
Add the specified packet in the TargetList.
void print(std::ostream &os, int verbosity, const std::string &prefix) const
bool canMergeWrites
Indicates whether we can merge incoming write requests.
void updateWriteFlags(PacketPtr pkt)
Add the specified packet in the TargetList.
TargetList(const std::string &name=".unnamedTargetList")
void clearDownstreamPending(iterator begin, iterator end)
void init(Addr blk_addr, Addr blk_size)
Reset state.
bool isWholeLineWrite() const
Check if this list contains writes that cover an entire cache line.
bool hasFromCache
Determine whether there was at least one non-snooping target coming from another cache.
void clearDownstreamPending()
Target(PacketPtr _pkt, Tick _readyTime, Counter _order, Source _source, bool _markedPending, bool alloc_on_fill)
const bool allocOnFill
Should the response servicing this target list allocate in the cache?
bool markedPending
We use this flag to track whether we have cleared the downstreamPending flag for the MSHR of the cach...
const Source source
Request from cpu, memory, or prefetcher?
Miss Status and handling Register.
bool postInvalidate
Did we snoop an invalidate while waiting for data?
TargetList targets
List of all requests that match the address.
void clearDownstreamPending()
bool wasWholeLineWrite
Track if we sent this as a whole line write or not.
void updateLockedRMWReadTarget(PacketPtr pkt)
Replaces the matching packet in the Targets list with a dummy packet to ensure the MSHR remains alloc...
std::string print() const
A no-args wrapper of print(std::ostream...) meant to be invoked from DPRINTFs avoiding string overhea...
MSHR(const std::string &name)
A simple constructor.
void promoteIf(const std::function< bool(Target &)> &pred)
Promotes deferred targets that satisfy a predicate.
void delay(Tick delay_ticks)
Adds a delay relative to the current tick to the current MSHR.
void markInService(bool pending_modified_resp)
bool downstreamPending
Flag set by downstream caches.
TargetList extractServiceableTargets(PacketPtr pkt)
Extracts the subset of the targets that can be serviced given a received response.
bool isPendingModified() const
List::iterator Iterator
MSHR list iterator.
bool postDowngrade
Did we snoop a read while waiting for data?
bool conflictAddr(const QueueEntry *entry) const override
Check if given entry's packets conflict with this' entries packets.
void promoteReadable()
Promotes deferred targets that do not require writable.
void popTarget()
Pop first target.
bool pendingModified
Here we use one flag to track both if:
void allocate(Addr blk_addr, unsigned blk_size, PacketPtr pkt, Tick when_ready, Counter _order, bool alloc_on_fill)
Allocate a miss to this MSHR.
TargetList deferredTargets
bool sendPacket(BaseCache &cache) override
Send this queue entry as a downstream packet, with the exact behaviour depending on the specific entr...
int getNumTargets() const
Returns the current number of allocated targets.
bool trySatisfyFunctional(PacketPtr pkt)
bool hasPostDowngrade() const
QueueEntry::Target * getTarget() override
Returns a reference to the first target.
Iterator readyIter
Pointer to this MSHR on the ready list.
bool matchBlockAddr(const Addr addr, const bool is_secure) const override
Check if entry corresponds to the one being looked for.
bool handleSnoop(PacketPtr target, Counter order)
bool needsWritable() const
The pending* and post* flags are only valid if inService is true.
bool isForward
True if the entry is just a simple forward from an upper level.
bool hasLockedRMWReadTarget()
Determine if there are any LockedRMWReads in the Targets list.
bool hasFromCache() const
Determine if there are non-deferred requests from other caches.
bool promoteDeferredTargets()
bool isWholeLineWrite() const
Check if this MSHR contains only compatible writes, and if they span the entire cache line.
void allocateTarget(PacketPtr target, Tick when, Counter order, bool alloc_on_fill)
Add a request to the list of targets.
void promoteWritable()
Promotes deferred targets that do not require writable.
bool hasPostInvalidate() const
void deallocate()
Mark this MSHR as free.
Iterator allocIter
Pointer to this MSHR on the allocated list.
std::list< MSHR * > List
A list of MSHRs.
bool hasTargets() const
Returns true if there are targets left.
Interface for things with names.
virtual std::string name() const
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Abstract base class for objects which support being printed to a stream for debugging.
A queue entry is holding packets that will be serviced as soon as resources are available.
A queue entry base class, to be used by both the MSHRs and write-queue entries.
Counter order
Order number assigned to disambiguate writes and misses.
bool inService
True if the entry has been sent downstream.
Tick readyTime
Tick when ready to issue.
A high-level queue interface, to be used by both the MSHR queue and the write buffer.
double Counter
All counters are of 64-bit values.
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Tick curTick()
The universal simulation clock.
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
uint64_t Tick
Tick count type.
Declaration of the Packet class.
Declaration of a request, the overall memory request consisting of the parts of the request that are ...