#include <cache_blk.hh>

Inheritance diagram for gem5::CacheBlk:

Classes
class	Lock
	Represents that the indicated thread context has a "lock" on the block, in the LL/SC sense. More...

Public Types
enum	CoherenceBits : unsigned { WritableBit = 0x02 , ReadableBit = 0x04 , DirtyBit = 0x08 , AllBits = 0x0E }
	Cache block's enum listing the supported coherence bits. More...

Public Member Functions
	CacheBlk ()

	CacheBlk (const CacheBlk &)=delete

CacheBlk &	operator= (const CacheBlk &)=delete

	CacheBlk (const CacheBlk &&)=delete

virtual CacheBlk &	operator= (CacheBlk &&other)
	Move assignment operator. More...

virtual	~CacheBlk ()

virtual void	invalidate () override
	Invalidate the block and clear all state. More...

void	setCoherenceBits (unsigned bits)
	Sets the corresponding coherence bits. More...

void	clearCoherenceBits (unsigned bits)
	Clear the corresponding coherence bits. More...

bool	isSet (unsigned bits) const
	Checks the given coherence bits are set. More...

bool	wasPrefetched () const
	Check if this block was the result of a hardware prefetch, yet to be touched. More...

void	clearPrefetched ()
	Clear the prefetching bit. More...

void	setPrefetched ()
	Marks this blocks as a recently prefetched block. More...

Tick	getWhenReady () const
	Get tick at which block's data will be available for access. More...

void	setWhenReady (const Tick tick)
	Set tick at which block's data will be available for access. More...

uint32_t	getTaskId () const
	Get the task id associated to this block. More...

uint32_t	getSrcRequestorId () const
	Get the requestor id associated to this block. More...

unsigned	getRefCount () const
	Get the number of references to this block since insertion. More...

void	increaseRefCount ()
	Get the number of references to this block since insertion. More...

Tick	getAge () const
	Get the block's age, that is, the number of ticks since its insertion. More...

void	insert (const Addr tag, const bool is_secure, const int src_requestor_ID, const uint32_t task_ID)
	Set member variables when a block insertion occurs. More...

void	trackLoadLocked (PacketPtr pkt)
	Track the fact that a local locked was issued to the block. More...

void	clearLoadLocks (const RequestPtr &req)
	Clear the any load lock that intersect the request, and is from a different context. More...

std::string	print () const override
	Pretty-print tag, set and way, and interpret state bits to readable form including mapping to a MOESI state. More...

bool	checkWrite (PacketPtr pkt)
	Handle interaction of load-locked operations and stores. More...

virtual void	insert (const Addr tag, const bool is_secure)
	Insert the block by assigning it a tag and marking it valid. More...

Public Member Functions inherited from gem5::TaggedEntry
	TaggedEntry ()

	~TaggedEntry ()=default

virtual bool	isValid () const
	Checks if the entry is valid. More...

bool	isSecure () const
	Check if this block holds data from the secure memory space. More...

virtual Addr	getTag () const
	Get tag associated to this block. More...

virtual bool	matchTag (Addr tag, bool is_secure) const
	Checks if the given tag information corresponds to this entry's. More...

virtual void	insert (const Addr tag, const bool is_secure)
	Insert the block by assigning it a tag and marking it valid. More...

std::string	print () const override
	Prints relevant information about this entry. More...

Public Member Functions inherited from gem5::ReplaceableEntry
	ReplaceableEntry ()=default

virtual	~ReplaceableEntry ()=default

virtual void	setPosition (const uint32_t set, const uint32_t way)
	Set both the set and way. More...

uint32_t	getSet () const
	Get set number. More...

uint32_t	getWay () const
	Get way number. More...

Public Attributes
uint8_t *	data = nullptr
	Contains a copy of the data in this block for easy access. More...

Tick	whenReady = 0
	Which curTick() will this block be accessible. More...

Public Attributes inherited from gem5::ReplaceableEntry
std::shared_ptr< replacement_policy::ReplacementData >	replacementData
	Replacement data associated to this entry. More...

Protected Member Functions
void	setTaskId (const uint32_t task_id)
	Set the task id value. More...

void	setSrcRequestorId (const uint32_t id)
	Set the source requestor id. More...

void	setRefCount (const unsigned count)
	Set the number of references to this block since insertion. More...

void	setTickInserted ()
	Set the current tick as this block's insertion tick. More...

Protected Member Functions inherited from gem5::TaggedEntry
virtual void	setTag (Addr tag)
	Set tag associated to this block. More...

virtual void	setSecure ()
	Set secure bit. More...

virtual void	setValid ()
	Set valid bit. More...

Protected Attributes
std::list< Lock >	lockList
	List of thread contexts that have performed a load-locked (LL) on the block since the last store. More...

unsigned	coherence
	The current coherence status of this block. More...

Protected Attributes inherited from gem5::ReplaceableEntry
uint32_t	_set
	Set to which this entry belongs. More...

uint32_t	_way
	Way (relative position within the set) to which this entry belongs. More...

Private Attributes
uint32_t	_taskId = 0
	Task Id associated with this block. More...

int	_srcRequestorId = 0
	holds the source requestor ID for this block. More...

unsigned	_refCount = 0
	Number of references to this block since it was brought in. More...

Tick	_tickInserted = 0
	Tick on which the block was inserted in the cache. More...

bool	_prefetched = 0
	Whether this block is an unaccessed hardware prefetch. More...

Detailed Description

A Basic Cache block.

Contains information regarding its coherence, prefetching status, as well as a pointer to its data.

Definition at line 70 of file cache_blk.hh.

Member Enumeration Documentation

◆ CoherenceBits

enum gem5::CacheBlk::CoherenceBits : unsigned

Cache block's enum listing the supported coherence bits.

The valid bit is not defined here because it is part of a TaggedEntry.

Enumerator
WritableBit	write permission
ReadableBit	Read permission. Note that a block can be valid but not readable if there is an outstanding write upgrade miss.
DirtyBit	dirty (modified)
AllBits	Helper enum value that includes all other bits. Whenever a new bits is added, this should be updated.

Definition at line 77 of file cache_blk.hh.

Constructor & Destructor Documentation

◆ CacheBlk() [1/3]

gem5::CacheBlk::CacheBlk ( )

inline

Definition at line 155 of file cache_blk.hh.

References invalidate().

◆ CacheBlk() [2/3]

gem5::CacheBlk::CacheBlk ( const CacheBlk & )

delete

◆ CacheBlk() [3/3]

gem5::CacheBlk::CacheBlk ( const CacheBlk && )

delete

◆ ~CacheBlk()

virtual gem5::CacheBlk::~CacheBlk ( )

inlinevirtual

Definition at line 195 of file cache_blk.hh.

Member Function Documentation

◆ checkWrite()

bool gem5::CacheBlk::checkWrite ( PacketPtr pkt )

inline

Handle interaction of load-locked operations and stores.

Returns: True if write should proceed, false otherwise. Returns false only in the case of a failed store conditional.

Definition at line 412 of file cache_blk.hh.

References clearLoadLocks(), gem5::Packet::isLLSC(), gem5::Packet::isWrite(), gem5::VegaISA::l, lockList, and gem5::Packet::req.

Referenced by gem5::BaseCache::satisfyRequest().

◆ clearCoherenceBits()

void gem5::CacheBlk::clearCoherenceBits ( unsigned bits )

inline

Clear the corresponding coherence bits.

Parameters

bits	The coherence bits to be cleared.

Definition at line 231 of file cache_blk.hh.

References gem5::bits(), and coherence.

Referenced by gem5::Cache::handleSnoop(), gem5::BaseCache::handleTimingReqHit(), gem5::BaseCache::handleTimingReqMiss(), invalidate(), gem5::BaseCache::recvTimingResp(), gem5::BaseCache::satisfyRequest(), gem5::Cache::satisfyRequest(), gem5::Cache::serviceMSHRTargets(), gem5::BaseCache::writebackBlk(), gem5::BaseCache::writebackVisitor(), and gem5::BaseCache::writecleanBlk().

◆ clearLoadLocks()

void gem5::CacheBlk::clearLoadLocks ( const RequestPtr & req )

inline

Clear the any load lock that intersect the request, and is from a different context.

Definition at line 345 of file cache_blk.hh.

References gem5::VegaISA::l, and lockList.

Referenced by checkWrite().

◆ clearPrefetched()

void gem5::CacheBlk::clearPrefetched ( )

inline

Clear the prefetching bit.

Either because it was recently used, or due to the block being invalidated.

Definition at line 255 of file cache_blk.hh.

References _prefetched.

Referenced by invalidate(), and gem5::BaseCache::recvTimingReq().

◆ getAge()

Tick gem5::CacheBlk::getAge ( ) const

inline

Get the block's age, that is, the number of ticks since its insertion.

Returns: The block's age.

Definition at line 302 of file cache_blk.hh.

References _tickInserted, and gem5::curTick().

Referenced by gem5::BaseTags::computeStatsVisitor().

◆ getRefCount()

unsigned gem5::CacheBlk::getRefCount ( ) const

inline

Get the number of references to this block since insertion.

Definition at line 291 of file cache_blk.hh.

References _refCount.

Referenced by gem5::BaseTags::cleanupRefsVisitor(), and gem5::BaseTags::invalidate().

◆ getSrcRequestorId()

uint32_t gem5::CacheBlk::getSrcRequestorId ( ) const

inline

Get the requestor id associated to this block.

Definition at line 288 of file cache_blk.hh.

References _srcRequestorId.

Referenced by gem5::BaseTags::invalidate().

◆ getTaskId()

uint32_t gem5::CacheBlk::getTaskId ( ) const

inline

Get the task id associated to this block.

Definition at line 285 of file cache_blk.hh.

References _taskId.

Referenced by gem5::Cache::cleanEvictBlk(), gem5::BaseTags::computeStatsVisitor(), gem5::BaseCache::writebackBlk(), gem5::BaseCache::writebackVisitor(), and gem5::BaseCache::writecleanBlk().

◆ getWhenReady()

Tick gem5::CacheBlk::getWhenReady ( ) const

inline

Get tick at which block's data will be available for access.

Returns: Data ready tick.

Definition at line 265 of file cache_blk.hh.

References gem5::MaxTick, and whenReady.

Referenced by gem5::BaseCache::calculateAccessLatency().

◆ increaseRefCount()

void gem5::CacheBlk::increaseRefCount ( )

inline

Get the number of references to this block since insertion.

Definition at line 294 of file cache_blk.hh.

References _refCount.

Referenced by gem5::BaseSetAssoc::accessBlock(), gem5::SectorTags::accessBlock(), and insert().

◆ insert() [1/2]

virtual void gem5::TaggedEntry::insert

inline

Insert the block by assigning it a tag and marking it valid.

Touches block if it hadn't been touched previously.

Parameters

tag	The tag value.

Definition at line 93 of file tagged_entry.hh.

Referenced by gem5::TempCacheBlk::insert(), gem5::SectorSubBlk::insert(), insert(), and operator=().

◆ insert() [2/2]

void gem5::CacheBlk::insert	(	const Addr	tag,
		const bool	is_secure,
		const int	src_requestor_ID,
		const uint32_t	task_ID
	)

Set member variables when a block insertion occurs.

Resets reference count to 1 (the insertion counts as a reference), and touch block if it hadn't been touched previously. Sets the insertion tick to the current tick. Marks the block valid.

Parameters

tag	Block address tag.
is_secure	Whether the block is in secure space or not.
src_requestor_ID	The source requestor ID.
task_ID	The new task ID.

Definition at line 50 of file cache_blk.cc.

References increaseRefCount(), insert(), gem5::TaggedEntry::isValid(), setSrcRequestorId(), setTaskId(), and setTickInserted().

Referenced by gem5::BaseTags::insertBlock().

◆ invalidate()

virtual void gem5::CacheBlk::invalidate ( )

inlineoverridevirtual

Invalidate the block and clear all state.

Reimplemented from gem5::TaggedEntry.

Reimplemented in gem5::CompressionBlk, gem5::SectorSubBlk, and gem5::TempCacheBlk.

Definition at line 200 of file cache_blk.hh.

References AllBits, clearCoherenceBits(), clearPrefetched(), gem5::TaggedEntry::invalidate(), gem5::Request::invldRequestorId, lockList, gem5::MaxTick, setRefCount(), setSrcRequestorId(), setTaskId(), setWhenReady(), and gem5::context_switch_task_id::Unknown.

Referenced by CacheBlk(), gem5::TempCacheBlk::invalidate(), gem5::SectorSubBlk::invalidate(), and gem5::BaseTags::invalidate().

◆ isSet()

bool gem5::CacheBlk::isSet ( unsigned bits ) const

inline

Checks the given coherence bits are set.

Returns: True if the block is readable.

Definition at line 239 of file cache_blk.hh.

References gem5::bits(), coherence, and gem5::TaggedEntry::isValid().

◆ operator=() [1/2]

virtual CacheBlk& gem5::CacheBlk::operator= ( CacheBlk && other )

inlinevirtual

Move assignment operator.

This should only be used to move an existing valid entry into an invalid one, not to create a new entry. In the end the valid entry will become invalid, and the invalid, valid. All location related variables will remain the same, that is, an entry cannot move its data, just its metadata contents.

Reimplemented in gem5::CompressionBlk.

Definition at line 172 of file cache_blk.hh.

References gem5::curTick(), insert(), gem5::TaggedEntry::isValid(), lockList, setCoherenceBits(), setPrefetched(), setRefCount(), setSrcRequestorId(), setTaskId(), and setWhenReady().

◆ operator=() [2/2]

CacheBlk& gem5::CacheBlk::operator= ( const CacheBlk & )

delete

Referenced by gem5::CompressionBlk::operator=().

◆ print()

std::string gem5::CacheBlk::print ( ) const

inlineoverridevirtual

Pretty-print tag, set and way, and interpret state bits to readable form including mapping to a MOESI state.

Returns: string with basic state information

state M O E S I writable 1 0 1 0 0 dirty 1 1 0 0 0 valid 1 1 1 1 0

state writable dirty valid M 1 1 1 O 0 1 1 E 1 0 1 S 0 0 1 I 0 0 0

Note that only one cache ever has a block in Modified or Owned state, i.e., only one cache owns the block, or equivalently has the DirtyBit bit set. However, multiple caches on the same path to memory can have a block in the Exclusive state (despite the name). Exclusive means this cache has the only copy at this level of the hierarchy, i.e., there may be copies in caches above this cache (in various states), but there are no peers that have copies on this branch of the hierarchy, and no caches at or above this level on any other branch have copies either.

Reimplemented from gem5::ReplaceableEntry.

Reimplemented in gem5::CompressionBlk, gem5::SectorSubBlk, and gem5::FALRUBlk.

Definition at line 364 of file cache_blk.hh.

References coherence, gem5::csprintf(), DirtyBit, isSet(), gem5::TaggedEntry::isValid(), gem5::TaggedEntry::print(), ReadableBit, gem5::VegaISA::s, state, wasPrefetched(), and WritableBit.

Referenced by gem5::BaseCache::access(), gem5::BaseCache::allocateBlock(), gem5::Cache::handleAtomicReqMiss(), gem5::BaseCache::handleFill(), gem5::Cache::handleSnoop(), gem5::FALRUBlk::print(), gem5::SectorSubBlk::print(), gem5::BaseCache::recvAtomic(), gem5::BaseCache::sendMSHRQueuePacket(), and gem5::BaseCache::updateCompressionData().

◆ setCoherenceBits()

void gem5::CacheBlk::setCoherenceBits ( unsigned bits )

inline

Sets the corresponding coherence bits.

Parameters

bits	The coherence bits to be set.

Definition at line 220 of file cache_blk.hh.

References gem5::bits(), coherence, and gem5::TaggedEntry::isValid().

Referenced by gem5::BaseCache::access(), gem5::NoncoherentCache::access(), gem5::BaseCache::cmpAndSwap(), gem5::BaseCache::handleFill(), operator=(), gem5::BaseCache::recvTimingReq(), gem5::BaseCache::recvTimingResp(), gem5::BaseCache::satisfyRequest(), and gem5::Cache::serviceMSHRTargets().

◆ setPrefetched()

void gem5::CacheBlk::setPrefetched ( )

inline

Marks this blocks as a recently prefetched block.

Definition at line 258 of file cache_blk.hh.

References _prefetched.

Referenced by operator=(), gem5::Cache::serviceMSHRTargets(), and gem5::NoncoherentCache::serviceMSHRTargets().

◆ setRefCount()

void gem5::CacheBlk::setRefCount ( const unsigned count )

inlineprotected

Set the number of references to this block since insertion.

Definition at line 470 of file cache_blk.hh.

References _refCount, and gem5::X86ISA::count.

Referenced by invalidate(), and operator=().

◆ setSrcRequestorId()

void gem5::CacheBlk::setSrcRequestorId ( const uint32_t id )

inlineprotected

Set the source requestor id.

Definition at line 467 of file cache_blk.hh.

References _srcRequestorId, and gem5::ArmISA::id.

Referenced by insert(), invalidate(), and operator=().

◆ setTaskId()

void gem5::CacheBlk::setTaskId ( const uint32_t task_id )

inlineprotected

Set the task id value.

Definition at line 464 of file cache_blk.hh.

References _taskId.

Referenced by insert(), invalidate(), and operator=().

◆ setTickInserted()

void gem5::CacheBlk::setTickInserted ( )

inlineprotected

Set the current tick as this block's insertion tick.

Definition at line 473 of file cache_blk.hh.

References _tickInserted, and gem5::curTick().

Referenced by insert().

◆ setWhenReady()

void gem5::CacheBlk::setWhenReady ( const Tick tick )

inline

Set tick at which block's data will be available for access.

The new tick must be chronologically sequential with respect to previous accesses.

Parameters

tick	New data ready tick.

Definition at line 278 of file cache_blk.hh.

References _tickInserted, and whenReady.

Referenced by gem5::BaseCache::access(), gem5::BaseCache::handleFill(), invalidate(), and operator=().

◆ trackLoadLocked()

void gem5::CacheBlk::trackLoadLocked ( PacketPtr pkt )

inline

Track the fact that a local locked was issued to the block.

Invalidate any previous LL to the same address.

Definition at line 327 of file cache_blk.hh.

References gem5::Packet::isLLSC(), gem5::VegaISA::l, lockList, and gem5::Packet::req.

Referenced by gem5::BaseCache::satisfyRequest().

◆ wasPrefetched()

bool gem5::CacheBlk::wasPrefetched ( ) const

inline

Check if this block was the result of a hardware prefetch, yet to be touched.

Returns: True if the block was a hardware prefetch, unaccesed.

Definition at line 249 of file cache_blk.hh.

References _prefetched.

Referenced by gem5::BaseCache::hasBeenPrefetched(), gem5::BaseCache::invalidateBlock(), print(), and gem5::BaseCache::recvTimingReq().

Member Data Documentation

◆ _prefetched

bool gem5::CacheBlk::_prefetched = 0

private

Whether this block is an unaccessed hardware prefetch.

Definition at line 492 of file cache_blk.hh.

Referenced by clearPrefetched(), setPrefetched(), and wasPrefetched().

◆ _refCount

unsigned gem5::CacheBlk::_refCount = 0

private

Number of references to this block since it was brought in.

Definition at line 483 of file cache_blk.hh.

Referenced by getRefCount(), increaseRefCount(), and setRefCount().

◆ _srcRequestorId

int gem5::CacheBlk::_srcRequestorId = 0

private

holds the source requestor ID for this block.

Definition at line 480 of file cache_blk.hh.

Referenced by getSrcRequestorId(), and setSrcRequestorId().

◆ _taskId

uint32_t gem5::CacheBlk::_taskId = 0

private

Task Id associated with this block.

Definition at line 477 of file cache_blk.hh.

Referenced by getTaskId(), and setTaskId().

◆ _tickInserted

Tick gem5::CacheBlk::_tickInserted = 0

private

Tick on which the block was inserted in the cache.

Its value is only meaningful if the block is valid.

Definition at line 489 of file cache_blk.hh.

Referenced by getAge(), setTickInserted(), and setWhenReady().

◆ coherence

unsigned gem5::CacheBlk::coherence

protected

The current coherence status of this block.

See also: CoherenceBits

Definition at line 456 of file cache_blk.hh.

Referenced by clearCoherenceBits(), isSet(), print(), and setCoherenceBits().

◆ data

uint8_t* gem5::CacheBlk::data = nullptr

Contains a copy of the data in this block for easy access.

This is used for efficient execution when the data could be actually stored in another format (COW, compressed, sub-blocked, etc). In all cases the data stored here should be kept consistant with the actual data referenced by this block.

Definition at line 103 of file cache_blk.hh.

Referenced by gem5::BaseCache::cmpAndSwap(), gem5::BaseCache::functionalAccess(), gem5::Cache::handleSnoop(), gem5::BaseCache::satisfyRequest(), gem5::BaseSetAssoc::tagsInit(), gem5::CompressedTags::tagsInit(), gem5::FALRU::tagsInit(), gem5::SectorTags::tagsInit(), gem5::TempCacheBlk::TempCacheBlk(), gem5::BaseCache::updateBlockData(), gem5::BaseCache::writebackBlk(), gem5::BaseCache::writebackVisitor(), gem5::BaseCache::writecleanBlk(), and gem5::TempCacheBlk::~TempCacheBlk().

◆ lockList

std::list<Lock> gem5::CacheBlk::lockList

protected

List of thread contexts that have performed a load-locked (LL) on the block since the last store.

Definition at line 152 of file cache_blk.hh.

Referenced by checkWrite(), clearLoadLocks(), invalidate(), operator=(), and trackLoadLocked().

◆ whenReady

Tick gem5::CacheBlk::whenReady = 0

Which curTick() will this block be accessible.

Its value is only meaningful if the block is valid.

Definition at line 109 of file cache_blk.hh.

Referenced by getWhenReady(), and setWhenReady().

The documentation for this class was generated from the following files:

mem/cache/cache_blk.hh
mem/cache/cache_blk.cc

Classes

Public Types

Public Member Functions

Public Attributes

Protected Member Functions

Protected Attributes

Private Attributes

Detailed Description

Member Enumeration Documentation

◆ CoherenceBits

Constructor & Destructor Documentation

◆ CacheBlk() [1/3]

◆ CacheBlk() [2/3]

◆ CacheBlk() [3/3]

◆ ~CacheBlk()

Member Function Documentation

◆ checkWrite()

◆ clearCoherenceBits()

◆ clearLoadLocks()

◆ clearPrefetched()

◆ getAge()

◆ getRefCount()

◆ getSrcRequestorId()

◆ getTaskId()

◆ getWhenReady()

◆ increaseRefCount()

◆ insert() [1/2]

◆ insert() [2/2]

◆ invalidate()

◆ isSet()

◆ operator=() [1/2]

◆ operator=() [2/2]

◆ print()

◆ setCoherenceBits()

◆ setPrefetched()

◆ setRefCount()

◆ setSrcRequestorId()

◆ setTaskId()

◆ setTickInserted()

◆ setWhenReady()

◆ trackLoadLocked()

◆ wasPrefetched()

Member Data Documentation

◆ _prefetched

◆ _refCount

◆ _srcRequestorId

◆ _taskId

◆ _tickInserted

◆ coherence

◆ data

◆ lockList

◆ whenReady