gem5  v22.1.0.0
execute.hh
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2013-2014 ARM Limited
3  * All rights reserved
4  *
5  * The license below extends only to copyright in the software and shall
6  * not be construed as granting a license to any other intellectual
7  * property including but not limited to intellectual property relating
8  * to a hardware implementation of the functionality of the software
9  * licensed hereunder. You may use the software subject to the license
10  * terms below provided that you ensure that this notice is replicated
11  * unmodified and in its entirety in all distributions of the software,
12  * modified or unmodified, in source code or in binary form.
13  *
14  * Redistribution and use in source and binary forms, with or without
15  * modification, are permitted provided that the following conditions are
16  * met: redistributions of source code must retain the above copyright
17  * notice, this list of conditions and the following disclaimer;
18  * redistributions in binary form must reproduce the above copyright
19  * notice, this list of conditions and the following disclaimer in the
20  * documentation and/or other materials provided with the distribution;
21  * neither the name of the copyright holders nor the names of its
22  * contributors may be used to endorse or promote products derived from
23  * this software without specific prior written permission.
24  *
25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36  */
37 
45 #ifndef __CPU_MINOR_EXECUTE_HH__
46 #define __CPU_MINOR_EXECUTE_HH__
47 
48 #include <vector>
49 
50 #include "base/named.hh"
51 #include "base/types.hh"
52 #include "cpu/minor/buffers.hh"
53 #include "cpu/minor/cpu.hh"
54 #include "cpu/minor/func_unit.hh"
55 #include "cpu/minor/lsq.hh"
56 #include "cpu/minor/pipe_data.hh"
57 #include "cpu/minor/scoreboard.hh"
58 
59 namespace gem5
60 {
61 
63 namespace minor
64 {
65 
68 class Execute : public Named
69 {
70  protected:
71 
74 
77 
80 
82  unsigned int issueLimit;
83 
85  unsigned int memoryIssueLimit;
86 
88  unsigned int commitLimit;
89 
91  unsigned int memoryCommitLimit;
92 
97 
100 
102  unsigned int numFuncUnits;
103 
107 
110 
113 
117 
120  unsigned int noCostFUIndex;
121 
124 
127 
130 
131  public: /* Public for Pipeline to be able to pass it to Decode */
133 
134  protected:
146  {
147  NotDraining, /* Not draining, possibly running */
148  DrainCurrentInst, /* Draining to end of inst/macroop */
149  DrainHaltFetch, /* Halting Fetch after completing current inst */
150  DrainAllInsts /* Discarding all remaining insts */
151  };
152 
154  {
156  ExecuteThreadInfo(unsigned int insts_committed) :
157  inputIndex(0),
159  instsBeingCommitted(insts_committed),
160  streamSeqNum(InstId::firstStreamSeqNum),
161  lastPredictionSeqNum(InstId::firstPredictionSeqNum),
163  { }
164 
166  inputIndex(other.inputIndex),
169  streamSeqNum(other.streamSeqNum),
171  drainState(other.drainState)
172  { }
173 
176 
179 
182  unsigned int inputIndex;
183 
187 
191 
197 
203 
206  };
207 
209 
213 
214  protected:
215  friend std::ostream &operator <<(std::ostream &os, DrainState state);
216 
219  const ForwardInstData *getInput(ThreadID tid);
220 
222  void popInput(ThreadID tid);
223 
227  void tryToBranch(MinorDynInstPtr inst, Fault fault, BranchData &branch);
228 
232  MinorDynInstPtr inst, const PCStateBase &target, BranchData &branch);
233 
240  LSQ::LSQRequestPtr response, BranchData &branch,
241  Fault &fault);
242 
254  bool executeMemRefInst(MinorDynInstPtr inst, BranchData &branch,
255  bool &failed_predicate, Fault &fault);
256 
258  bool isInterrupted(ThreadID thread_id) const;
259 
261  bool isInbetweenInsts(ThreadID thread_id) const;
262 
265  bool takeInterrupt(ThreadID thread_id, BranchData &branch);
266 
268  unsigned int issue(ThreadID thread_id);
269 
272  bool tryPCEvents(ThreadID thread_id);
273 
277 
281  ThreadID checkInterrupts(BranchData& branch, bool& interrupted);
282 
285  bool hasInterrupt(ThreadID thread_id);
286 
301  bool commitInst(MinorDynInstPtr inst, bool early_memory_issue,
302  BranchData &branch, Fault &fault, bool &committed,
303  bool &completed_mem_issue);
304 
312  void commit(ThreadID thread_id, bool only_commit_microops, bool discard,
313  BranchData &branch);
314 
316  void setDrainState(ThreadID thread_id, DrainState state);
317 
322 
323  public:
324  Execute(const std::string &name_,
325  MinorCPU &cpu_,
326  const BaseMinorCPUParams &params,
329 
330  ~Execute();
331 
332  public:
333 
336 
338  LSQ &getLSQ() { return lsq; }
339 
343 
346  bool instIsHeadInst(MinorDynInstPtr inst);
347 
349  void evaluate();
350 
351  void minorTrace() const;
352 
355  bool isDrained();
356 
358  unsigned int drain();
359  void drainResume();
360 };
361 
362 } // namespace minor
363 } // namespace gem5
364 
365 #endif /* __CPU_MINOR_EXECUTE_HH__ */
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,...
Classes for buffer, queue and FIFO behaviour.
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:79
Provide a non-protected base class for Minor's Ports as derived classes are created by Fetch1 and Exe...
Definition: cpu.hh:107
MinorCPU is an in-order CPU model with four fixed pipeline stages:
Definition: cpu.hh:86
A collection of MinorFUs.
Definition: func_unit.hh:190
Interface for things with names.
Definition: named.hh:39
Forward data betwen Execute and Fetch1 carrying change-of-address/stream information.
Definition: pipe_data.hh:67
Execute stage.
Definition: execute.hh:69
bool setTraceTimeOnIssue
Modify instruction trace times on issue.
Definition: execute.hh:112
void handleMemResponse(MinorDynInstPtr inst, LSQ::LSQRequestPtr response, BranchData &branch, Fault &fault)
Handle extracting mem ref responses from the memory queues and completing the associated instructions...
Definition: execute.cc:326
bool processMoreThanOneInput
If true, more than one input line can be processed each cycle if there is room to execute more instru...
Definition: execute.hh:96
LSQ lsq
Dcache port to pass on to the CPU.
Definition: execute.hh:123
void evaluate()
Pass on input/buffer data to the output if you can.
Definition: execute.cc:1459
unsigned int commitLimit
Number of instructions that can be committed per cycle.
Definition: execute.hh:88
void popInput(ThreadID tid)
Pop an element off the input buffer, if there are any.
Definition: execute.cc:212
unsigned int memoryCommitLimit
Number of memory instructions that can be committed per cycle.
Definition: execute.hh:91
friend std::ostream & operator<<(std::ostream &os, DrainState state)
Definition: execute.cc:1831
bool executeMemRefInst(MinorDynInstPtr inst, BranchData &branch, bool &failed_predicate, Fault &fault)
Execute a memory reference instruction.
Definition: execute.cc:451
unsigned int issue(ThreadID thread_id)
Try and issue instructions from the inputBuffer.
Definition: execute.cc:548
unsigned int noCostFUIndex
The FU index of the non-existent costless FU for instructions which pass the MinorDynInst::isNoCostIn...
Definition: execute.hh:120
unsigned int memoryIssueLimit
Number of memory ops that can be issued per cycle.
Definition: execute.hh:85
Latch< ForwardInstData >::Output inp
Input port carrying instructions from Decode.
Definition: execute.hh:73
ThreadID commitPriority
Definition: execute.hh:212
void commit(ThreadID thread_id, bool only_commit_microops, bool discard, BranchData &branch)
Try and commit instructions from the ends of the functional unit pipelines.
Definition: execute.cc:1069
MinorCPU & cpu
Pointer back to the containing CPU.
Definition: execute.hh:79
ThreadID getIssuingThread()
Definition: execute.cc:1792
unsigned int drain()
Like the drain interface on SimObject.
Definition: execute.cc:1863
unsigned int issueLimit
Number of instructions that can be issued per cycle.
Definition: execute.hh:82
bool instIsRightStream(MinorDynInstPtr inst)
Does the given instruction have the right stream sequence number to be committed?
Definition: execute.cc:1911
void setDrainState(ThreadID thread_id, DrainState state)
Set the drain state (with useful debugging messages)
Definition: execute.cc:1856
bool setTraceTimeOnCommit
Modify instruction trace times on commit.
Definition: execute.hh:109
ThreadID checkInterrupts(BranchData &branch, bool &interrupted)
Check all threads for possible interrupts.
Definition: execute.cc:1646
void updateBranchData(ThreadID tid, BranchData::Reason reason, MinorDynInstPtr inst, const PCStateBase &target, BranchData &branch)
Actually create a branch to communicate to Fetch1/Fetch2 and, if that is a stream-changing branch upd...
Definition: execute.cc:300
DrainState
Stage cycle-by-cycle state.
Definition: execute.hh:146
MinorFUPool & fuDescriptions
Descriptions of the functional units we want to generate.
Definition: execute.hh:99
bool allowEarlyMemIssue
Allow mem refs to leave their FUs before reaching the head of the in flight insts queue if their depe...
Definition: execute.hh:116
unsigned int numFuncUnits
Number of functional units to produce.
Definition: execute.hh:102
std::vector< FUPipeline * > funcUnits
The execution functional units.
Definition: execute.hh:129
void tryToBranch(MinorDynInstPtr inst, Fault fault, BranchData &branch)
Generate Branch data based (into branch) on an observed (or not) change in PC while executing an inst...
Definition: execute.cc:221
bool commitInst(MinorDynInstPtr inst, bool early_memory_issue, BranchData &branch, Fault &fault, bool &committed, bool &completed_mem_issue)
Commit a single instruction.
Definition: execute.cc:927
Cycles longestFuLatency
Longest latency of any FU, useful for setting up the activity recoder.
Definition: execute.hh:106
bool hasInterrupt(ThreadID thread_id)
Checks if a specific thread has an interrupt.
Definition: execute.cc:1681
bool isInterrupted(ThreadID thread_id) const
Has an interrupt been raised.
Definition: execute.cc:417
bool isInbetweenInsts(ThreadID thread_id) const
Are we between instructions? Can we be interrupted?
Definition: execute.cc:1452
Execute(const std::string &name_, MinorCPU &cpu_, const BaseMinorCPUParams &params, Latch< ForwardInstData >::Output inp_, Latch< BranchData >::Input out_)
Definition: execute.cc:64
ThreadID interruptPriority
Definition: execute.hh:210
std::vector< Scoreboard > scoreboard
Scoreboard of instruction dependencies.
Definition: execute.hh:126
bool takeInterrupt(ThreadID thread_id, BranchData &branch)
Act on an interrupt.
Definition: execute.cc:423
std::vector< ExecuteThreadInfo > executeInfo
Definition: execute.hh:208
std::vector< InputBuffer< ForwardInstData > > inputBuffer
Definition: execute.hh:132
void doInstCommitAccounting(MinorDynInstPtr inst)
Do the stats handling and instruction count and PC event events related to the new instruction/op cou...
Definition: execute.cc:863
MinorCPU::MinorCPUPort & getDcachePort()
Returns the DcachePort owned by this Execute to pass upwards.
Definition: execute.cc:1928
bool instIsHeadInst(MinorDynInstPtr inst)
Returns true if the given instruction is at the head of the inFlightInsts instruction queue.
Definition: execute.cc:1917
const ForwardInstData * getInput(ThreadID tid)
Get a piece of data to work on from the inputBuffer, or 0 if there is no data.
Definition: execute.cc:199
void minorTrace() const
Definition: execute.cc:1692
LSQ & getLSQ()
To allow ExecContext to find the LSQ.
Definition: execute.hh:338
Latch< BranchData >::Input out
Input port carrying stream changes to Fetch1.
Definition: execute.hh:76
ThreadID issuePriority
Definition: execute.hh:211
bool isDrained()
After thread suspension, has Execute been drained of in-flight instructions and memory accesses.
Definition: execute.cc:1885
ThreadID getCommittingThread()
Use the current threading policy to determine the next thread to decode from.
Definition: execute.cc:1725
bool tryPCEvents(ThreadID thread_id)
Try to act on PC-related events.
Definition: execute.cc:841
Forward flowing data between Fetch2,Decode,Execute carrying a packet of instructions of a width appro...
Definition: pipe_data.hh:285
Id for lines and instructions.
Definition: dyn_inst.hh:77
Derived SenderState to carry data access info.
Definition: lsq.hh:130
Encapsulate wires on either input or output of the latch.
Definition: buffers.hh:253
Wrapper for a queue type to act as a pipeline stage input queue.
Definition: buffers.hh:405
STL vector class.
Definition: stl.hh:37
Top level definition of the Minor in-order CPU model.
atomic_var_t state
Definition: helpers.cc:188
Execute function unit descriptions and pipeline implementations.
A load/store queue that allows outstanding reads and writes.
A simple instruction scoreboard for tracking dependencies in Execute.
Bitfield< 17 > os
Definition: misc.hh:810
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
std::shared_ptr< FaultBase > Fault
Definition: types.hh:248
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:235
uint64_t InstSeqNum
Definition: inst_seq.hh:40
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi)
Minor contains all the definitions within the MinorCPU apart from the CPU class itself.
Contains class definitions for data flowing between pipeline stages in the top-level structure portio...
unsigned int inputIndex
Index that we've completed upto in getInput data.
Definition: execute.hh:182
ForwardInstData instsBeingCommitted
Structure for reporting insts currently being processed/retired for MinorTrace.
Definition: execute.hh:190
bool lastCommitWasEndOfMacroop
The last commit was the end of a full instruction so an interrupt can safely happen.
Definition: execute.hh:186
Queue< QueuedInst, ReportTraitsAdaptor< QueuedInst > > * inFlightInsts
In-order instructions either in FUs or the LSQ.
Definition: execute.hh:175
DrainState drainState
State progression for draining NotDraining -> ...
Definition: execute.hh:205
InstSeqNum lastPredictionSeqNum
A prediction number for use where one isn't available from an instruction.
Definition: execute.hh:202
ExecuteThreadInfo(const ExecuteThreadInfo &other)
Definition: execute.hh:165
InstSeqNum streamSeqNum
Source of sequence number for instuction streams.
Definition: execute.hh:196
ExecuteThreadInfo(unsigned int insts_committed)
Constructor.
Definition: execute.hh:156
Queue< QueuedInst, ReportTraitsAdaptor< QueuedInst > > * inFUMemInsts
Memory ref instructions still in the FUs.
Definition: execute.hh:178

Generated on Wed Dec 21 2022 10:22:30 for gem5 by doxygen 1.9.1