gem5 v24.0.0.0
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execute.hh
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1/*
2 * Copyright (c) 2013-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
45#ifndef __CPU_MINOR_EXECUTE_HH__
46#define __CPU_MINOR_EXECUTE_HH__
47
48#include <vector>
49
50#include "base/named.hh"
51#include "base/types.hh"
52#include "cpu/minor/buffers.hh"
53#include "cpu/minor/cpu.hh"
55#include "cpu/minor/lsq.hh"
58
59namespace gem5
60{
61
62namespace minor
63{
64
67class Execute : public Named
68{
69 protected:
70
73
76
79
81 unsigned int issueLimit;
82
84 unsigned int memoryIssueLimit;
85
87 unsigned int commitLimit;
88
90 unsigned int memoryCommitLimit;
91
96
99
101 unsigned int numFuncUnits;
102
106
109
112
116
119 unsigned int noCostFUIndex;
120
123
126
129
130 public: /* Public for Pipeline to be able to pass it to Decode */
132
133 protected:
145 {
146 NotDraining, /* Not draining, possibly running */
147 DrainCurrentInst, /* Draining to end of inst/macroop */
148 DrainHaltFetch, /* Halting Fetch after completing current inst */
149 DrainAllInsts /* Discarding all remaining insts */
150 };
151
206
208
212
213 protected:
214 friend std::ostream &operator <<(std::ostream &os, DrainState state);
215
219
221 void popInput(ThreadID tid);
222
226 void tryToBranch(MinorDynInstPtr inst, Fault fault, BranchData &branch);
227
231 MinorDynInstPtr inst, const PCStateBase &target, BranchData &branch);
232
239 LSQ::LSQRequestPtr response, BranchData &branch,
240 Fault &fault);
241
254 bool &failed_predicate, Fault &fault);
255
257 bool isInterrupted(ThreadID thread_id) const;
258
260 bool isInbetweenInsts(ThreadID thread_id) const;
261
264 bool takeInterrupt(ThreadID thread_id, BranchData &branch);
265
267 unsigned int issue(ThreadID thread_id);
268
271 bool tryPCEvents(ThreadID thread_id);
272
276
280 ThreadID checkInterrupts(BranchData& branch, bool& interrupted);
281
284 bool hasInterrupt(ThreadID thread_id);
285
300 bool commitInst(MinorDynInstPtr inst, bool early_memory_issue,
301 BranchData &branch, Fault &fault, bool &committed,
302 bool &completed_mem_issue);
303
311 void commit(ThreadID thread_id, bool only_commit_microops, bool discard,
312 BranchData &branch);
313
315 void setDrainState(ThreadID thread_id, DrainState state);
316
321
322 public:
323 Execute(const std::string &name_,
324 MinorCPU &cpu_,
325 const BaseMinorCPUParams &params,
328
329 ~Execute();
330
331 public:
332
335
337 LSQ &getLSQ() { return lsq; }
338
342
346
348 void evaluate();
349
350 void minorTrace() const;
351
354 bool isDrained();
355
357 unsigned int drain();
358 void drainResume();
359};
360
361} // namespace minor
362} // namespace gem5
363
364#endif /* __CPU_MINOR_EXECUTE_HH__ */
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,...
Classes for buffer, queue and FIFO behaviour.
Cycles is a wrapper class for representing cycle counts, i.e.
Definition types.hh:79
Provide a non-protected base class for Minor's Ports as derived classes are created by Fetch1 and Exe...
Definition cpu.hh:106
MinorCPU is an in-order CPU model with four fixed pipeline stages:
Definition cpu.hh:85
A collection of MinorFUs.
Definition func_unit.hh:190
Interface for things with names.
Definition named.hh:39
Forward data betwen Execute and Fetch1 carrying change-of-address/stream information.
Definition pipe_data.hh:66
Execute stage.
Definition execute.hh:68
LSQ & getLSQ()
To allow ExecContext to find the LSQ.
Definition execute.hh:337
bool setTraceTimeOnIssue
Modify instruction trace times on issue.
Definition execute.hh:111
void handleMemResponse(MinorDynInstPtr inst, LSQ::LSQRequestPtr response, BranchData &branch, Fault &fault)
Handle extracting mem ref responses from the memory queues and completing the associated instructions...
Definition execute.cc:325
bool processMoreThanOneInput
If true, more than one input line can be processed each cycle if there is room to execute more instru...
Definition execute.hh:95
LSQ lsq
Dcache port to pass on to the CPU.
Definition execute.hh:122
void evaluate()
Pass on input/buffer data to the output if you can.
Definition execute.cc:1421
unsigned int commitLimit
Number of instructions that can be committed per cycle.
Definition execute.hh:87
void popInput(ThreadID tid)
Pop an element off the input buffer, if there are any.
Definition execute.cc:211
unsigned int memoryCommitLimit
Number of memory instructions that can be committed per cycle.
Definition execute.hh:90
bool executeMemRefInst(MinorDynInstPtr inst, BranchData &branch, bool &failed_predicate, Fault &fault)
Execute a memory reference instruction.
Definition execute.cc:450
unsigned int issue(ThreadID thread_id)
Try and issue instructions from the inputBuffer.
Definition execute.cc:547
unsigned int noCostFUIndex
The FU index of the non-existent costless FU for instructions which pass the MinorDynInst::isNoCostIn...
Definition execute.hh:119
unsigned int memoryIssueLimit
Number of memory ops that can be issued per cycle.
Definition execute.hh:84
Latch< ForwardInstData >::Output inp
Input port carrying instructions from Decode.
Definition execute.hh:72
ThreadID commitPriority
Definition execute.hh:211
void commit(ThreadID thread_id, bool only_commit_microops, bool discard, BranchData &branch)
Try and commit instructions from the ends of the functional unit pipelines.
Definition execute.cc:1030
MinorCPU & cpu
Pointer back to the containing CPU.
Definition execute.hh:78
ThreadID getIssuingThread()
Definition execute.cc:1754
unsigned int drain()
Like the drain interface on SimObject.
Definition execute.cc:1825
unsigned int issueLimit
Number of instructions that can be issued per cycle.
Definition execute.hh:81
bool instIsRightStream(MinorDynInstPtr inst)
Does the given instruction have the right stream sequence number to be committed?
Definition execute.cc:1873
void setDrainState(ThreadID thread_id, DrainState state)
Set the drain state (with useful debugging messages)
Definition execute.cc:1818
bool setTraceTimeOnCommit
Modify instruction trace times on commit.
Definition execute.hh:108
ThreadID checkInterrupts(BranchData &branch, bool &interrupted)
Check all threads for possible interrupts.
Definition execute.cc:1608
void updateBranchData(ThreadID tid, BranchData::Reason reason, MinorDynInstPtr inst, const PCStateBase &target, BranchData &branch)
Actually create a branch to communicate to Fetch1/Fetch2 and, if that is a stream-changing branch upd...
Definition execute.cc:299
friend std::ostream & operator<<(std::ostream &os, DrainState state)
Definition execute.cc:1793
DrainState
Stage cycle-by-cycle state.
Definition execute.hh:145
MinorFUPool & fuDescriptions
Descriptions of the functional units we want to generate.
Definition execute.hh:98
bool allowEarlyMemIssue
Allow mem refs to leave their FUs before reaching the head of the in flight insts queue if their depe...
Definition execute.hh:115
unsigned int numFuncUnits
Number of functional units to produce.
Definition execute.hh:101
std::vector< FUPipeline * > funcUnits
The execution functional units.
Definition execute.hh:128
void tryToBranch(MinorDynInstPtr inst, Fault fault, BranchData &branch)
Generate Branch data based (into branch) on an observed (or not) change in PC while executing an inst...
Definition execute.cc:220
bool commitInst(MinorDynInstPtr inst, bool early_memory_issue, BranchData &branch, Fault &fault, bool &committed, bool &completed_mem_issue)
Commit a single instruction.
Definition execute.cc:888
Cycles longestFuLatency
Longest latency of any FU, useful for setting up the activity recoder.
Definition execute.hh:105
bool hasInterrupt(ThreadID thread_id)
Checks if a specific thread has an interrupt.
Definition execute.cc:1643
bool isInterrupted(ThreadID thread_id) const
Has an interrupt been raised.
Definition execute.cc:416
bool isInbetweenInsts(ThreadID thread_id) const
Are we between instructions? Can we be interrupted?
Definition execute.cc:1414
Execute(const std::string &name_, MinorCPU &cpu_, const BaseMinorCPUParams &params, Latch< ForwardInstData >::Output inp_, Latch< BranchData >::Input out_)
Definition execute.cc:63
ThreadID interruptPriority
Definition execute.hh:209
std::vector< Scoreboard > scoreboard
Scoreboard of instruction dependencies.
Definition execute.hh:125
bool takeInterrupt(ThreadID thread_id, BranchData &branch)
Act on an interrupt.
Definition execute.cc:422
std::vector< ExecuteThreadInfo > executeInfo
Definition execute.hh:207
std::vector< InputBuffer< ForwardInstData > > inputBuffer
Definition execute.hh:131
void doInstCommitAccounting(MinorDynInstPtr inst)
Do the stats handling and instruction count and PC event events related to the new instruction/op cou...
Definition execute.cc:856
MinorCPU::MinorCPUPort & getDcachePort()
Returns the DcachePort owned by this Execute to pass upwards.
Definition execute.cc:1890
bool instIsHeadInst(MinorDynInstPtr inst)
Returns true if the given instruction is at the head of the inFlightInsts instruction queue.
Definition execute.cc:1879
const ForwardInstData * getInput(ThreadID tid)
Get a piece of data to work on from the inputBuffer, or 0 if there is no data.
Definition execute.cc:198
void minorTrace() const
Definition execute.cc:1654
Latch< BranchData >::Input out
Input port carrying stream changes to Fetch1.
Definition execute.hh:75
ThreadID issuePriority
Definition execute.hh:210
bool isDrained()
After thread suspension, has Execute been drained of in-flight instructions and memory accesses.
Definition execute.cc:1847
ThreadID getCommittingThread()
Use the current threading policy to determine the next thread to decode from.
Definition execute.cc:1687
bool tryPCEvents(ThreadID thread_id)
Try to act on PC-related events.
Definition execute.cc:834
Forward flowing data between Fetch2,Decode,Execute carrying a packet of instructions of a width appro...
Definition pipe_data.hh:284
Id for lines and instructions.
Definition dyn_inst.hh:76
Derived SenderState to carry data access info.
Definition lsq.hh:129
Encapsulate wires on either input or output of the latch.
Definition buffers.hh:252
Wrapper for a queue type to act as a pipeline stage input queue.
Definition buffers.hh:404
STL vector class.
Definition stl.hh:37
Top level definition of the Minor in-order CPU model.
atomic_var_t state
Definition helpers.cc:211
Execute function unit descriptions and pipeline implementations.
A load/store queue that allows outstanding reads and writes.
A simple instruction scoreboard for tracking dependencies in Execute.
Bitfield< 17 > os
Definition misc.hh:838
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
std::shared_ptr< FaultBase > Fault
Definition types.hh:249
int16_t ThreadID
Thread index/ID type.
Definition types.hh:235
uint64_t InstSeqNum
Definition inst_seq.hh:40
Minor contains all the definitions within the MinorCPU apart from the CPU class itself.
Contains class definitions for data flowing between pipeline stages in the top-level structure portio...
unsigned int inputIndex
Index that we've completed upto in getInput data.
Definition execute.hh:181
ForwardInstData instsBeingCommitted
Structure for reporting insts currently being processed/retired for MinorTrace.
Definition execute.hh:189
bool lastCommitWasEndOfMacroop
The last commit was the end of a full instruction so an interrupt can safely happen.
Definition execute.hh:185
Queue< QueuedInst, ReportTraitsAdaptor< QueuedInst > > * inFlightInsts
In-order instructions either in FUs or the LSQ.
Definition execute.hh:174
DrainState drainState
State progression for draining NotDraining -> ... -> DrainAllInsts.
Definition execute.hh:204
InstSeqNum lastPredictionSeqNum
A prediction number for use where one isn't available from an instruction.
Definition execute.hh:201
ExecuteThreadInfo(const ExecuteThreadInfo &other)
Definition execute.hh:164
InstSeqNum streamSeqNum
Source of sequence number for instuction streams.
Definition execute.hh:195
ExecuteThreadInfo(unsigned int insts_committed)
Constructor.
Definition execute.hh:155
Queue< QueuedInst, ReportTraitsAdaptor< QueuedInst > > * inFUMemInsts
Memory ref instructions still in the FUs.
Definition execute.hh:177

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