45#ifndef __CPU_MINOR_EXECUTE_HH__
46#define __CPU_MINOR_EXECUTE_HH__
254 bool &failed_predicate,
Fault &fault);
302 bool &completed_mem_issue);
311 void commit(
ThreadID thread_id,
bool only_commit_microops,
bool discard,
323 Execute(
const std::string &name_,
325 const BaseMinorCPUParams ¶ms,
357 unsigned int drain();
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,...
Classes for buffer, queue and FIFO behaviour.
Cycles is a wrapper class for representing cycle counts, i.e.
Provide a non-protected base class for Minor's Ports as derived classes are created by Fetch1 and Exe...
MinorCPU is an in-order CPU model with four fixed pipeline stages:
A collection of MinorFUs.
Interface for things with names.
Forward data betwen Execute and Fetch1 carrying change-of-address/stream information.
LSQ & getLSQ()
To allow ExecContext to find the LSQ.
bool setTraceTimeOnIssue
Modify instruction trace times on issue.
void handleMemResponse(MinorDynInstPtr inst, LSQ::LSQRequestPtr response, BranchData &branch, Fault &fault)
Handle extracting mem ref responses from the memory queues and completing the associated instructions...
bool processMoreThanOneInput
If true, more than one input line can be processed each cycle if there is room to execute more instru...
LSQ lsq
Dcache port to pass on to the CPU.
void evaluate()
Pass on input/buffer data to the output if you can.
unsigned int commitLimit
Number of instructions that can be committed per cycle.
void popInput(ThreadID tid)
Pop an element off the input buffer, if there are any.
unsigned int memoryCommitLimit
Number of memory instructions that can be committed per cycle.
bool executeMemRefInst(MinorDynInstPtr inst, BranchData &branch, bool &failed_predicate, Fault &fault)
Execute a memory reference instruction.
unsigned int issue(ThreadID thread_id)
Try and issue instructions from the inputBuffer.
unsigned int noCostFUIndex
The FU index of the non-existent costless FU for instructions which pass the MinorDynInst::isNoCostIn...
unsigned int memoryIssueLimit
Number of memory ops that can be issued per cycle.
Latch< ForwardInstData >::Output inp
Input port carrying instructions from Decode.
void commit(ThreadID thread_id, bool only_commit_microops, bool discard, BranchData &branch)
Try and commit instructions from the ends of the functional unit pipelines.
MinorCPU & cpu
Pointer back to the containing CPU.
ThreadID getIssuingThread()
unsigned int drain()
Like the drain interface on SimObject.
unsigned int issueLimit
Number of instructions that can be issued per cycle.
bool instIsRightStream(MinorDynInstPtr inst)
Does the given instruction have the right stream sequence number to be committed?
void setDrainState(ThreadID thread_id, DrainState state)
Set the drain state (with useful debugging messages)
bool setTraceTimeOnCommit
Modify instruction trace times on commit.
ThreadID checkInterrupts(BranchData &branch, bool &interrupted)
Check all threads for possible interrupts.
void updateBranchData(ThreadID tid, BranchData::Reason reason, MinorDynInstPtr inst, const PCStateBase &target, BranchData &branch)
Actually create a branch to communicate to Fetch1/Fetch2 and, if that is a stream-changing branch upd...
friend std::ostream & operator<<(std::ostream &os, DrainState state)
DrainState
Stage cycle-by-cycle state.
MinorFUPool & fuDescriptions
Descriptions of the functional units we want to generate.
bool allowEarlyMemIssue
Allow mem refs to leave their FUs before reaching the head of the in flight insts queue if their depe...
unsigned int numFuncUnits
Number of functional units to produce.
std::vector< FUPipeline * > funcUnits
The execution functional units.
void tryToBranch(MinorDynInstPtr inst, Fault fault, BranchData &branch)
Generate Branch data based (into branch) on an observed (or not) change in PC while executing an inst...
bool commitInst(MinorDynInstPtr inst, bool early_memory_issue, BranchData &branch, Fault &fault, bool &committed, bool &completed_mem_issue)
Commit a single instruction.
Cycles longestFuLatency
Longest latency of any FU, useful for setting up the activity recoder.
bool hasInterrupt(ThreadID thread_id)
Checks if a specific thread has an interrupt.
bool isInterrupted(ThreadID thread_id) const
Has an interrupt been raised.
bool isInbetweenInsts(ThreadID thread_id) const
Are we between instructions? Can we be interrupted?
Execute(const std::string &name_, MinorCPU &cpu_, const BaseMinorCPUParams ¶ms, Latch< ForwardInstData >::Output inp_, Latch< BranchData >::Input out_)
ThreadID interruptPriority
std::vector< Scoreboard > scoreboard
Scoreboard of instruction dependencies.
bool takeInterrupt(ThreadID thread_id, BranchData &branch)
Act on an interrupt.
std::vector< ExecuteThreadInfo > executeInfo
std::vector< InputBuffer< ForwardInstData > > inputBuffer
void doInstCommitAccounting(MinorDynInstPtr inst)
Do the stats handling and instruction count and PC event events related to the new instruction/op cou...
MinorCPU::MinorCPUPort & getDcachePort()
Returns the DcachePort owned by this Execute to pass upwards.
bool instIsHeadInst(MinorDynInstPtr inst)
Returns true if the given instruction is at the head of the inFlightInsts instruction queue.
const ForwardInstData * getInput(ThreadID tid)
Get a piece of data to work on from the inputBuffer, or 0 if there is no data.
Latch< BranchData >::Input out
Input port carrying stream changes to Fetch1.
bool isDrained()
After thread suspension, has Execute been drained of in-flight instructions and memory accesses.
ThreadID getCommittingThread()
Use the current threading policy to determine the next thread to decode from.
bool tryPCEvents(ThreadID thread_id)
Try to act on PC-related events.
Forward flowing data between Fetch2,Decode,Execute carrying a packet of instructions of a width appro...
Id for lines and instructions.
Derived SenderState to carry data access info.
Wrapper for a queue type to act as a pipeline stage input queue.
Top level definition of the Minor in-order CPU model.
Execute function unit descriptions and pipeline implementations.
A load/store queue that allows outstanding reads and writes.
A simple instruction scoreboard for tracking dependencies in Execute.
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
std::shared_ptr< FaultBase > Fault
int16_t ThreadID
Thread index/ID type.
Minor contains all the definitions within the MinorCPU apart from the CPU class itself.
Contains class definitions for data flowing between pipeline stages in the top-level structure portio...
unsigned int inputIndex
Index that we've completed upto in getInput data.
ForwardInstData instsBeingCommitted
Structure for reporting insts currently being processed/retired for MinorTrace.
bool lastCommitWasEndOfMacroop
The last commit was the end of a full instruction so an interrupt can safely happen.
Queue< QueuedInst, ReportTraitsAdaptor< QueuedInst > > * inFlightInsts
In-order instructions either in FUs or the LSQ.
DrainState drainState
State progression for draining NotDraining -> ... -> DrainAllInsts.
InstSeqNum lastPredictionSeqNum
A prediction number for use where one isn't available from an instruction.
ExecuteThreadInfo(const ExecuteThreadInfo &other)
InstSeqNum streamSeqNum
Source of sequence number for instuction streams.
ExecuteThreadInfo(unsigned int insts_committed)
Constructor.
Queue< QueuedInst, ReportTraitsAdaptor< QueuedInst > > * inFUMemInsts
Memory ref instructions still in the FUs.