gem5  v21.1.0.2
Public Types | Public Member Functions | Static Public Member Functions | Public Attributes | Protected Member Functions | List of all members
gem5::minor::LSQ::LSQRequest Class Referenceabstract

Derived SenderState to carry data access info. More...

#include <lsq.hh>

Inheritance diagram for gem5::minor::LSQ::LSQRequest:
gem5::BaseMMU::Translation gem5::Packet::SenderState gem5::minor::LSQ::SingleDataRequest gem5::minor::LSQ::SpecialDataRequest gem5::minor::LSQ::SplitDataRequest gem5::minor::LSQ::BarrierDataRequest gem5::minor::LSQ::FailedDataRequest

Public Types

enum  LSQRequestState {
  NotIssued, InTranslation, Translated, Failed,
  RequestIssuing, StoreToStoreBuffer, RequestNeedsRetry, StoreInStoreBuffer,
  StoreBufferIssuing, StoreBufferNeedsRetry, Complete
}
 

Public Member Functions

 LSQRequest (LSQ &port_, MinorDynInstPtr inst_, bool isLoad_, RegIndex zero_reg, PacketDataPtr data_=NULL, uint64_t *res_=NULL)
 
virtual ~LSQRequest ()
 
void makePacket ()
 Make a packet to use with the memory transaction. More...
 
bool skippedMemAccess ()
 Was no memory access attempted for this request? More...
 
void setSkipped ()
 Set this request as having been skipped before a memory transfer was attempt. More...
 
AddrRangeCoverage containsAddrRangeOf (LSQRequest *other_request)
 Does this request's address range fully cover the range of other_request? More...
 
virtual void startAddrTranslation ()=0
 Start the address translation process for this request. More...
 
virtual PacketPtr getHeadPacket ()=0
 Get the next packet to issue for this request. More...
 
virtual void stepToNextPacket ()=0
 Step to the next packet for the next call to getHeadPacket. More...
 
virtual bool sentAllPackets ()=0
 Have all packets been sent? More...
 
virtual bool hasPacketsInMemSystem ()=0
 True if this request has any issued packets in the memory system and so can't be interrupted until it gets responses. More...
 
virtual void retireResponse (PacketPtr packet_)=0
 Retire a response packet into the LSQRequest packet possibly completing this transfer. More...
 
virtual bool isBarrier ()
 Is this a request a barrier? More...
 
bool needsToBeSentToStoreBuffer ()
 This request, once processed by the requests/transfers queues, will need to go to the store buffer. More...
 
void setState (LSQRequestState new_state)
 Set state and output trace output. More...
 
bool isComplete () const
 Has this request been completed. More...
 
void reportData (std::ostream &os) const
 MinorTrace report interface. More...
 
- Public Member Functions inherited from gem5::BaseMMU::Translation
virtual ~Translation ()
 
virtual void finish (const Fault &fault, const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode)=0
 
virtual bool squashed () const
 This function is used by the page table walker to determine if it should translate the a pending request or if the underlying request has been squashed. More...
 
- Public Member Functions inherited from gem5::Packet::SenderState
 SenderState ()
 
virtual ~SenderState ()
 

Static Public Member Functions

static AddrRangeCoverage containsAddrRangeOf (Addr req1_addr, unsigned int req1_size, Addr req2_addr, unsigned int req2_size)
 Does address range req1 (req1_addr to req1_addr + req1_size - 1) fully cover, partially cover or not cover at all the range req2. More...
 

Public Attributes

LSQport
 Owning port. More...
 
const RegIndex zeroReg
 
MinorDynInstPtr inst
 Instruction which made this request. More...
 
bool isLoad
 Load/store indication used for building packet. More...
 
PacketDataPtr data
 Dynamically allocated and populated data carried for building write packets. More...
 
PacketPtr packet
 
RequestPtr request
 The underlying request of this LSQRequest. More...
 
uint64_t * res
 Res from pushRequest. More...
 
bool skipped
 Was skipped. More...
 
bool issuedToMemory
 This in an access other than a normal cacheable load that's visited the memory system. More...
 
bool isTranslationDelayed
 Address translation is delayed due to table walk. More...
 
LSQRequestState state
 
- Public Attributes inherited from gem5::Packet::SenderState
SenderStatepredecessor
 

Protected Member Functions

void markDelayed ()
 BaseMMU::Translation interface. More...
 
void tryToSuppressFault ()
 Instructions may want to suppress translation faults (e.g. More...
 
void disableMemAccess ()
 
void completeDisabledMemAccess ()
 

Detailed Description

Derived SenderState to carry data access info.

through address translation, the queues in this port and back from the memory system.

Definition at line 129 of file lsq.hh.

Member Enumeration Documentation

◆ LSQRequestState

Enumerator
NotIssued 
InTranslation 
Translated 
Failed 
RequestIssuing 
StoreToStoreBuffer 
RequestNeedsRetry 
StoreInStoreBuffer 
StoreBufferIssuing 
StoreBufferNeedsRetry 
Complete 

Definition at line 174 of file lsq.hh.

Constructor & Destructor Documentation

◆ LSQRequest()

gem5::minor::LSQ::LSQRequest::LSQRequest ( LSQ port_,
MinorDynInstPtr  inst_,
bool  isLoad_,
RegIndex  zero_reg,
PacketDataPtr  data_ = NULL,
uint64_t *  res_ = NULL 
)

Definition at line 61 of file lsq.cc.

References request.

◆ ~LSQRequest()

gem5::minor::LSQ::LSQRequest::~LSQRequest ( )
virtual

Definition at line 1465 of file lsq.cc.

References data, and packet.

Member Function Documentation

◆ completeDisabledMemAccess()

void gem5::minor::LSQ::LSQRequest::completeDisabledMemAccess ( )
protected

◆ containsAddrRangeOf() [1/2]

LSQ::AddrRangeCoverage gem5::minor::LSQ::LSQRequest::containsAddrRangeOf ( Addr  req1_addr,
unsigned int  req1_size,
Addr  req2_addr,
unsigned int  req2_size 
)
static

Does address range req1 (req1_addr to req1_addr + req1_size - 1) fully cover, partially cover or not cover at all the range req2.

Definition at line 124 of file lsq.cc.

References gem5::minor::LSQ::FullAddrRangeCoverage, gem5::minor::LSQ::NoAddrRangeCoverage, and gem5::minor::LSQ::PartialAddrRangeCoverage.

Referenced by gem5::minor::LSQ::StoreBuffer::canForwardDataToLoad(), and gem5::minor::LSQ::StoreBuffer::forwardStoreData().

◆ containsAddrRangeOf() [2/2]

AddrRangeCoverage gem5::minor::LSQ::LSQRequest::containsAddrRangeOf ( LSQRequest other_request)

Does this request's address range fully cover the range of other_request?

◆ disableMemAccess()

void gem5::minor::LSQ::LSQRequest::disableMemAccess ( )
protected

Definition at line 117 of file lsq.cc.

References DPRINTFS.

◆ getHeadPacket()

virtual PacketPtr gem5::minor::LSQ::LSQRequest::getHeadPacket ( )
pure virtual

Get the next packet to issue for this request.

For split transfers, it will be necessary to step through the available packets by calling do { getHeadPacket ; stepToNextPacket } while (!sentAllPackets) and by retiring response using retireResponse

Implemented in gem5::minor::LSQ::SplitDataRequest, gem5::minor::LSQ::SingleDataRequest, and gem5::minor::LSQ::SpecialDataRequest.

Referenced by gem5::minor::LSQ::tryToSend().

◆ hasPacketsInMemSystem()

virtual bool gem5::minor::LSQ::LSQRequest::hasPacketsInMemSystem ( )
pure virtual

True if this request has any issued packets in the memory system and so can't be interrupted until it gets responses.

Implemented in gem5::minor::LSQ::SplitDataRequest, gem5::minor::LSQ::SingleDataRequest, and gem5::minor::LSQ::SpecialDataRequest.

Referenced by gem5::minor::LSQ::recvTimingResp(), and gem5::minor::LSQ::tryToSendToTransfers().

◆ isBarrier()

bool gem5::minor::LSQ::LSQRequest::isBarrier ( )
virtual

◆ isComplete()

bool gem5::minor::LSQ::LSQRequest::isComplete ( ) const

Has this request been completed.

This includes all reasons for completion: successful transfers, faults, skipped because of preceding faults

Definition at line 181 of file lsq.cc.

References gem5::Complete, and gem5::minor::LSQ::state.

Referenced by gem5::minor::LSQ::findResponse(), gem5::minor::LSQ::recvTimingResp(), gem5::minor::LSQ::StoreBuffer::step(), and gem5::minor::LSQ::tryToSendToTransfers().

◆ makePacket()

void gem5::minor::LSQ::LSQRequest::makePacket ( )

Make a packet to use with the memory transaction.

Definition at line 1726 of file lsq.cc.

References data, gem5::minor::makePacketForRequest(), and gem5::NoFault.

◆ markDelayed()

void gem5::minor::LSQ::LSQRequest::markDelayed ( )
inlineprotectedvirtual

BaseMMU::Translation interface.

Implements gem5::BaseMMU::Translation.

Definition at line 200 of file lsq.hh.

References isTranslationDelayed.

◆ needsToBeSentToStoreBuffer()

bool gem5::minor::LSQ::LSQRequest::needsToBeSentToStoreBuffer ( )

This request, once processed by the requests/transfers queues, will need to go to the store buffer.

Definition at line 167 of file lsq.cc.

References gem5::minor::LSQ::state.

Referenced by gem5::minor::Execute::handleMemResponse().

◆ reportData()

void gem5::minor::LSQ::LSQRequest::reportData ( std::ostream &  os) const

MinorTrace report interface.

Definition at line 189 of file lsq.cc.

References gem5::X86ISA::os, and gem5::minor::LSQ::state.

Referenced by gem5::minor::LSQ::StoreBuffer::minorTrace().

◆ retireResponse()

virtual void gem5::minor::LSQ::LSQRequest::retireResponse ( PacketPtr  packet_)
pure virtual

Retire a response packet into the LSQRequest packet possibly completing this transfer.

Implemented in gem5::minor::LSQ::SplitDataRequest, gem5::minor::LSQ::SingleDataRequest, and gem5::minor::LSQ::SpecialDataRequest.

Referenced by gem5::minor::LSQ::recvTimingResp().

◆ sentAllPackets()

virtual bool gem5::minor::LSQ::LSQRequest::sentAllPackets ( )
pure virtual

◆ setSkipped()

void gem5::minor::LSQ::LSQRequest::setSkipped ( )
inline

Set this request as having been skipped before a memory transfer was attempt.

Definition at line 225 of file lsq.hh.

References skipped.

Referenced by gem5::minor::LSQ::tryToSendToTransfers().

◆ setState()

void gem5::minor::LSQ::LSQRequest::setState ( LSQRequestState  new_state)

◆ skippedMemAccess()

bool gem5::minor::LSQ::LSQRequest::skippedMemAccess ( )
inline

Was no memory access attempted for this request?

Definition at line 221 of file lsq.hh.

References skipped.

◆ startAddrTranslation()

virtual void gem5::minor::LSQ::LSQRequest::startAddrTranslation ( )
pure virtual

Start the address translation process for this request.

This will issue a translation request to the TLB.

Implemented in gem5::minor::LSQ::SplitDataRequest, gem5::minor::LSQ::SingleDataRequest, and gem5::minor::LSQ::SpecialDataRequest.

Referenced by gem5::minor::LSQ::pushRequest().

◆ stepToNextPacket()

virtual void gem5::minor::LSQ::LSQRequest::stepToNextPacket ( )
pure virtual

Step to the next packet for the next call to getHeadPacket.

Implemented in gem5::minor::LSQ::SplitDataRequest, gem5::minor::LSQ::SingleDataRequest, and gem5::minor::LSQ::SpecialDataRequest.

Referenced by gem5::minor::LSQ::tryToSend().

◆ tryToSuppressFault()

void gem5::minor::LSQ::LSQRequest::tryToSuppressFault ( )
protected

Instructions may want to suppress translation faults (e.g.

non-faulting vector loads).

Definition at line 81 of file lsq.cc.

References DPRINTFS, gem5::NoFault, gem5::SimpleThread::pcState(), and gem5::minor::LSQ::zeroReg.

Member Data Documentation

◆ data

PacketDataPtr gem5::minor::LSQ::LSQRequest::data

Dynamically allocated and populated data carried for building write packets.

Definition at line 148 of file lsq.hh.

Referenced by ~LSQRequest().

◆ inst

MinorDynInstPtr gem5::minor::LSQ::LSQRequest::inst

◆ isLoad

bool gem5::minor::LSQ::LSQRequest::isLoad

Load/store indication used for building packet.

This isn't carried by Request so we need to keep it here

Definition at line 144 of file lsq.hh.

Referenced by gem5::minor::LSQ::StoreBuffer::forwardStoreData(), gem5::minor::LSQ::moveFromRequestsToTransfers(), gem5::minor::LSQ::popResponse(), gem5::minor::LSQ::tryToSend(), and gem5::minor::LSQ::tryToSendToTransfers().

◆ issuedToMemory

bool gem5::minor::LSQ::LSQRequest::issuedToMemory

This in an access other than a normal cacheable load that's visited the memory system.

Definition at line 169 of file lsq.hh.

Referenced by gem5::minor::LSQ::popResponse(), and gem5::minor::LSQ::tryToSendToTransfers().

◆ isTranslationDelayed

bool gem5::minor::LSQ::LSQRequest::isTranslationDelayed

Address translation is delayed due to table walk.

Definition at line 172 of file lsq.hh.

Referenced by markDelayed().

◆ packet

PacketPtr gem5::minor::LSQ::LSQRequest::packet

◆ port

LSQ& gem5::minor::LSQ::LSQRequest::port

Owning port.

Definition at line 135 of file lsq.hh.

◆ request

RequestPtr gem5::minor::LSQ::LSQRequest::request

◆ res

uint64_t* gem5::minor::LSQ::LSQRequest::res

Res from pushRequest.

Definition at line 160 of file lsq.hh.

◆ skipped

bool gem5::minor::LSQ::LSQRequest::skipped

Was skipped.

Set to indicate any reason (faulted, bad stream sequence number, in a fault shadow) that this request did not perform a memory transfer

Definition at line 165 of file lsq.hh.

Referenced by setSkipped(), and skippedMemAccess().

◆ state

LSQRequestState gem5::minor::LSQ::LSQRequest::state

◆ zeroReg

const RegIndex gem5::minor::LSQ::LSQRequest::zeroReg

Definition at line 137 of file lsq.hh.


The documentation for this class was generated from the following files:

Generated on Tue Sep 21 2021 12:31:32 for gem5 by doxygen 1.8.17