gem5  v22.0.0.2
lsq.hh
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37 
45 #ifndef __CPU_MINOR_NEW_LSQ_HH__
46 #define __CPU_MINOR_NEW_LSQ_HH__
47 
48 #include <string>
49 #include <vector>
50 
51 #include "base/named.hh"
52 #include "cpu/minor/buffers.hh"
53 #include "cpu/minor/cpu.hh"
54 #include "cpu/minor/pipe_data.hh"
55 #include "cpu/minor/trace.hh"
56 #include "mem/packet.hh"
57 
58 namespace gem5
59 {
60 
62 namespace minor
63 {
64 
65 /* Forward declaration */
66 class Execute;
67 
68 class LSQ : public Named
69 {
70  protected:
74 
75  protected:
78  {
79  MemoryRunning, /* Default. Step dcache queues when possible. */
80  MemoryNeedsRetry /* Request rejected, will be asked to retry */
81  };
82 
84  friend std::ostream &operator <<(std::ostream &os,
86 
89  {
90  PartialAddrRangeCoverage, /* Two ranges partly overlap */
91  FullAddrRangeCoverage, /* One range fully covers another */
92  NoAddrRangeCoverage /* Two ranges are disjoint */
93  };
94 
97  {
98  protected:
101 
102  public:
103  DcachePort(std::string name, LSQ &lsq_, MinorCPU &cpu) :
104  MinorCPU::MinorCPUPort(name, cpu), lsq(lsq_)
105  { }
106 
107  protected:
108  bool recvTimingResp(PacketPtr pkt) override
109  { return lsq.recvTimingResp(pkt); }
110 
111  void recvReqRetry() override { lsq.recvReqRetry(); }
112 
113  bool isSnooping() const override { return true; }
114 
115  void recvTimingSnoopReq(PacketPtr pkt) override
116  { return lsq.recvTimingSnoopReq(pkt); }
117 
118  void recvFunctionalSnoop(PacketPtr pkt) override { }
119  };
120 
122 
123  public:
127  class LSQRequest :
128  public BaseMMU::Translation, /* For TLB lookups */
129  public Packet::SenderState /* For packing into a Packet */
130  {
131  public:
134 
137 
140  bool isLoad;
141 
145 
146  /* Requests carry packets on their way to the memory system.
147  * When a Packet returns from the memory system, its
148  * request needs to have its packet updated as this
149  * may have changed in flight */
151 
154 
156  uint64_t *res;
157 
161  bool skipped;
162 
166 
169 
171  {
172  NotIssued, /* Newly created */
173  InTranslation, /* TLB accessed, no reply yet */
174  Translated, /* Finished address translation */
175  Failed, /* The starting start of FailedDataRequests */
176  RequestIssuing, /* Load/store issued to memory in the requests
177  queue */
178  StoreToStoreBuffer, /* Store in transfers on its way to the
179  store buffer */
180  RequestNeedsRetry, /* Retry needed for load */
181  StoreInStoreBuffer, /* Store in the store buffer, before issuing
182  a memory transfer */
183  StoreBufferIssuing, /* Store in store buffer and has been
184  issued */
185  StoreBufferNeedsRetry, /* Retry needed for store */
186  /* All completed states. Includes
187  completed loads, TLB faults and skipped requests whose
188  seqNum's no longer match */
190  };
191 
193 
194  protected:
197 
200  void tryToSuppressFault();
201 
202  void disableMemAccess();
204 
205  public:
206  LSQRequest(LSQ &port_, MinorDynInstPtr inst_, bool isLoad_,
207  PacketDataPtr data_ = NULL, uint64_t *res_ = NULL);
208 
209  virtual ~LSQRequest();
210 
211  public:
213  void makePacket();
214 
216  bool skippedMemAccess() { return skipped; }
217 
220  void setSkipped() { skipped = true; }
221 
225  Addr req1_addr, unsigned int req1_size,
226  Addr req2_addr, unsigned int req2_size);
227 
231 
234  virtual void startAddrTranslation() = 0;
235 
240  virtual PacketPtr getHeadPacket() = 0;
241 
243  virtual void stepToNextPacket() = 0;
244 
246  virtual bool sentAllPackets() = 0;
247 
250  virtual bool hasPacketsInMemSystem() = 0;
251 
254  virtual void retireResponse(PacketPtr packet_) = 0;
255 
257  virtual bool isBarrier();
258 
262 
264  void setState(LSQRequestState new_state);
265 
269  bool isComplete() const;
270 
272  void reportData(std::ostream &os) const;
273  };
274 
276 
277  friend std::ostream & operator <<(std::ostream &os,
279 
280  friend std::ostream & operator <<(std::ostream &os,
282 
283  protected:
286  {
287  protected:
289  void finish(const Fault &fault_, const RequestPtr &request_,
291  { }
292 
293  public:
296 
299  { fatal("No packets in a SpecialDataRequest"); }
300 
302  void stepToNextPacket() { }
303 
305  bool sentAllPackets() { return true; }
306 
308  bool hasPacketsInMemSystem() { return false; }
309 
312  void retireResponse(PacketPtr packet_) { }
313 
314  public:
316  /* Say this is a load, not actually relevant */
317  LSQRequest(port_, inst_, true, NULL, 0)
318  { }
319  };
320 
325  {
326  public:
328  SpecialDataRequest(port_, inst_)
329  { state = Failed; }
330  };
331 
335  {
336  public:
337  bool isBarrier() { return true; }
338 
339  public:
341  SpecialDataRequest(port_, inst_)
342  { state = Complete; }
343  };
344 
347  {
348  protected:
350  void finish(const Fault &fault_, const RequestPtr &request_,
352 
356 
359 
360  public:
362  void startAddrTranslation();
363 
366 
368  void stepToNextPacket() { packetInFlight = true; packetSent = true; }
369 
372 
375  bool sentAllPackets() { return packetSent; }
376 
379  void retireResponse(PacketPtr packet_);
380 
381  public:
383  bool isLoad_, PacketDataPtr data_ = NULL, uint64_t *res_ = NULL) :
384  LSQRequest(port_, inst_, isLoad_, data_, res_),
385  packetInFlight(false),
386  packetSent(false)
387  { }
388  };
389 
391  {
392  protected:
395  protected:
397  unsigned int numFragments;
398 
401 
407 
409  unsigned int numIssuedFragments;
410 
412  unsigned int numRetiredFragments;
413 
417 
420 
421  protected:
423  void finish(const Fault &fault_, const RequestPtr &request_,
425 
426  public:
427  SplitDataRequest(LSQ &port_, MinorDynInstPtr inst_,
428  bool isLoad_, PacketDataPtr data_ = NULL,
429  uint64_t *res_ = NULL);
430 
432 
433  public:
436  void makeFragmentRequests();
437 
440  void makeFragmentPackets();
441 
446  void startAddrTranslation();
447 
450 
452  void stepToNextPacket();
453 
456 
460 
463  void retireResponse(PacketPtr packet_);
464 
467  };
468 
472  class StoreBuffer : public Named
473  {
474  public:
477 
479  const unsigned int numSlots;
480 
482  const unsigned int storeLimitPerCycle;
483 
484  public:
487 
490  unsigned int numUnissuedAccesses;
491 
492  public:
493  StoreBuffer(std::string name_, LSQ &lsq_,
494  unsigned int store_buffer_size,
495  unsigned int store_limit_per_cycle);
496 
497  public:
499  bool canInsert() const;
500 
502  void deleteRequest(LSQRequestPtr request);
503 
505  void insert(LSQRequestPtr request);
506 
513  unsigned int &found_slot);
514 
517  void forwardStoreData(LSQRequestPtr load, unsigned int slot_number);
518 
521  unsigned int numUnissuedStores() { return numUnissuedAccesses; }
522 
526  void countIssuedStore(LSQRequestPtr request);
527 
529  bool isDrained() const { return slots.empty(); }
530 
532  void step();
533 
535  void minorTrace() const;
536  };
537 
538  protected:
543 
544  public:
547 
549  const unsigned int inMemorySystemLimit;
550 
552  const unsigned int lineWidth;
553 
554  public:
558  typedef Queue<LSQRequestPtr,
562 
576 
585 
586  /* The store buffer contains committed cacheable stores on
587  * their way to memory decoupled from subsequence instruction execution.
588  * Before trying to issue a cacheable read from 'requests' to memory,
589  * the store buffer is checked to see if a previous store contains the
590  * needed data (StoreBuffer::canForwardDataToLoad) which can be
591  * forwarded in lieu of a memory access. If there are outstanding
592  * stores in the transfers queue, they must be promoted to the store
593  * buffer (and so be commited) before they can be correctly checked
594  * for forwarding. */
596 
597  protected:
605 
607  unsigned int numAccessesInDTLB;
608 
611  unsigned int numStoresInTransfers;
612 
617 
621 
624 
625  protected:
629  void tryToSendToTransfers(LSQRequestPtr request);
630 
634  bool tryToSend(LSQRequestPtr request);
635 
637  void clearMemBarrier(MinorDynInstPtr inst);
638 
641 
643  bool canSendToMemorySystem();
644 
646  void threadSnoop(LSQRequestPtr request);
647 
648  public:
649  LSQ(std::string name_, std::string dcache_port_name_,
650  MinorCPU &cpu_, Execute &execute_,
651  unsigned int max_accesses_in_memory_system, unsigned int line_width,
652  unsigned int requests_queue_size, unsigned int transfers_queue_size,
653  unsigned int store_buffer_size,
654  unsigned int store_buffer_cycle_store_limit);
655 
656  virtual ~LSQ();
657 
658  public:
666  void step();
667 
670  bool canRequest() { return requests.unreservedRemainingSpace() != 0; }
671 
677 
679  void popResponse(LSQRequestPtr response);
680 
682  bool canPushIntoStoreBuffer() const { return storeBuffer.canInsert(); }
683 
686 
690  bool accessesInFlight() const
691  { return numAccessesIssuedToMemory != 0; }
692 
697 
700  { return lastMemBarrier[thread_id]; }
701 
703  bool isDrained();
704 
707  bool needsToTick();
708 
712  bool committed);
713 
716  Fault pushRequest(MinorDynInstPtr inst, bool isLoad, uint8_t *data,
717  unsigned int size, Addr addr, Request::Flags flags,
718  uint64_t *res, AtomicOpFunctorPtr amo_op,
719  const std::vector<bool>& byte_enable =
721 
725 
727  bool recvTimingResp(PacketPtr pkt);
728  void recvReqRetry();
729  void recvTimingSnoopReq(PacketPtr pkt);
730 
733 
734  void minorTrace() const;
735 };
736 
740 PacketPtr makePacketForRequest(const RequestPtr &request, bool isLoad,
741  Packet::SenderState *sender_state = NULL, PacketDataPtr data = NULL);
742 
743 } // namespace minor
744 } // namespace gem5
745 
746 #endif /* __CPU_MINOR_NEW_LSQ_HH__ */
gem5::minor::LSQ
Definition: lsq.hh:68
gem5::minor::LSQ::LSQRequest::sentAllPackets
virtual bool sentAllPackets()=0
Have all packets been sent?
pipe_data.hh
fatal
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:190
gem5::minor::LSQ::requests
LSQQueue requests
requests contains LSQRequests which have been issued to the TLB by calling ExecContext::readMem/write...
Definition: lsq.hh:575
gem5::minor::LSQ::LSQRequest::retireResponse
virtual void retireResponse(PacketPtr packet_)=0
Retire a response packet into the LSQRequest packet possibly completing this transfer.
gem5::minor::LSQ::LSQRequest::tryToSuppressFault
void tryToSuppressFault()
Instructions may want to suppress translation faults (e.g.
Definition: lsq.cc:79
gem5::minor::LSQ::SpecialDataRequest::getHeadPacket
PacketPtr getHeadPacket()
Get the head packet as counted by numIssuedFragments.
Definition: lsq.hh:298
gem5::minor::LSQ::LSQRequest::StoreToStoreBuffer
@ StoreToStoreBuffer
Definition: lsq.hh:178
gem5::minor::LSQ::SingleDataRequest::sentAllPackets
bool sentAllPackets()
packetInFlight can become false again, so need to check packetSent
Definition: lsq.hh:375
gem5::minor::LSQ::MemoryNeedsRetry
@ MemoryNeedsRetry
Definition: lsq.hh:80
gem5::MinorCPU::MinorCPUPort::MinorCPUPort
MinorCPUPort(const std::string &name_, MinorCPU &cpu_)
Definition: cpu.hh:113
gem5::minor::LSQ::StoreBuffer::StoreBuffer
StoreBuffer(std::string name_, LSQ &lsq_, unsigned int store_buffer_size, unsigned int store_limit_per_cycle)
Definition: lsq.cc:1685
gem5::minor::ReportTraitsPtrAdaptor
A similar adaptor but for elements held by pointer ElemType should implement ReportIF.
Definition: buffers.hh:108
gem5::minor::LSQ::DcachePort::DcachePort
DcachePort(std::string name, LSQ &lsq_, MinorCPU &cpu)
Definition: lsq.hh:103
gem5::Port::name
const std::string name() const
Return port name (for DPRINTF).
Definition: port.hh:111
gem5::minor::LSQ::LSQRequest::request
RequestPtr request
The underlying request of this LSQRequest.
Definition: lsq.hh:153
gem5::minor::LSQ::issuedMemBarrierInst
void issuedMemBarrierInst(MinorDynInstPtr inst)
A memory barrier instruction has been issued, remember its execSeqNum that we can avoid issuing memor...
Definition: lsq.cc:1718
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::minor::LSQ::SplitDataRequest::retireResponse
void retireResponse(PacketPtr packet_)
For loads, paste the response data into the main response packet.
Definition: lsq.cc:625
gem5::minor::LSQ::LSQRequest::isLoad
bool isLoad
Load/store indication used for building packet.
Definition: lsq.hh:140
gem5::minor::LSQ::AddrRangeCoverage
AddrRangeCoverage
Coverage of one address range with another.
Definition: lsq.hh:88
gem5::minor::LSQ::LSQRequest::RequestIssuing
@ RequestIssuing
Definition: lsq.hh:176
gem5::minor::LSQ::StoreBuffer::storeLimitPerCycle
const unsigned int storeLimitPerCycle
Maximum number of stores that can be issued per cycle.
Definition: lsq.hh:482
gem5::minor::LSQ::LSQRequest::makePacket
void makePacket()
Make a packet to use with the memory transaction.
Definition: lsq.cc:1730
gem5::minor::LSQ::LSQRequestPtr
LSQRequest * LSQRequestPtr
Definition: lsq.hh:275
gem5::minor::LSQ::threadSnoop
void threadSnoop(LSQRequestPtr request)
Snoop other threads monitors on memory system accesses.
Definition: lsq.cc:1783
gem5::minor::LSQ::LSQRequest::LSQRequestState
LSQRequestState
Definition: lsq.hh:170
gem5::minor::LSQ::PartialAddrRangeCoverage
@ PartialAddrRangeCoverage
Definition: lsq.hh:90
gem5::minor::LSQ::LSQRequest::packet
PacketPtr packet
Definition: lsq.hh:150
gem5::minor::LSQ::state
MemoryState state
Retry state of last issued memory transfer.
Definition: lsq.hh:546
gem5::minor::LSQ::LSQRequest::setSkipped
void setSkipped()
Set this request as having been skipped before a memory transfer was attempt.
Definition: lsq.hh:220
gem5::MinorCPU::MinorCPUPort
Provide a non-protected base class for Minor's Ports as derived classes are created by Fetch1 and Exe...
Definition: cpu.hh:106
gem5::minor::LSQ::StoreBuffer::numUnissuedAccesses
unsigned int numUnissuedAccesses
Number of occupied slots which have not yet issued a memory access.
Definition: lsq.hh:490
gem5::BaseMMU::Mode
Mode
Definition: mmu.hh:56
gem5::minor::LSQ::SplitDataRequest::sendNextFragmentToTranslation
void sendNextFragmentToTranslation()
Part of the address translation loop, see startAddTranslation.
Definition: lsq.cc:702
gem5::minor::LSQ::NoAddrRangeCoverage
@ NoAddrRangeCoverage
Definition: lsq.hh:92
gem5::minor::LSQ::BarrierDataRequest::BarrierDataRequest
BarrierDataRequest(LSQ &port_, MinorDynInstPtr inst_)
Definition: lsq.hh:340
gem5::minor::LSQ::DcachePort
Exposable data port.
Definition: lsq.hh:96
named.hh
gem5::minor::LSQ::StoreBuffer::forwardStoreData
void forwardStoreData(LSQRequestPtr load, unsigned int slot_number)
Fill the given packet with appropriate date from slot slot_number.
Definition: lsq.cc:805
gem5::minor::LSQ::StoreBuffer::numUnissuedStores
unsigned int numUnissuedStores()
Number of stores in the store buffer which have not been completely issued to the memory system.
Definition: lsq.hh:521
gem5::minor::LSQ::LSQRequest::issuedToMemory
bool issuedToMemory
This in an access other than a normal cacheable load that's visited the memory system.
Definition: lsq.hh:165
gem5::minor::LSQ::SpecialDataRequest::finish
void finish(const Fault &fault_, const RequestPtr &request_, ThreadContext *tc, BaseMMU::Mode mode)
TLB interace.
Definition: lsq.hh:289
gem5::minor::LSQ::LSQRequest::needsToBeSentToStoreBuffer
bool needsToBeSentToStoreBuffer()
This request, once processed by the requests/transfers queues, will need to go to the store buffer.
Definition: lsq.cc:165
gem5::minor::Queue
Wrapper for a queue type to act as a pipeline stage input queue.
Definition: buffers.hh:404
gem5::minor::LSQ::FailedDataRequest
FailedDataRequest represents requests from instructions that failed their predicates but need to ride...
Definition: lsq.hh:324
gem5::MinorCPU::MinorCPUPort::cpu
MinorCPU & cpu
The enclosing cpu.
Definition: cpu.hh:110
cpu.hh
minor
gem5::minor::LSQ::DcachePort::recvTimingSnoopReq
void recvTimingSnoopReq(PacketPtr pkt) override
Receive a timing snoop request from the peer.
Definition: lsq.hh:115
gem5::MinorCPU
MinorCPU is an in-order CPU model with four fixed pipeline stages:
Definition: cpu.hh:85
gem5::minor::LSQ::MemoryState
MemoryState
State of memory access for head access.
Definition: lsq.hh:77
gem5::minor::LSQ::SplitDataRequest::finish
void finish(const Fault &fault_, const RequestPtr &request_, ThreadContext *tc, BaseMMU::Mode mode)
TLB response interface.
Definition: lsq.cc:335
gem5::minor::LSQ::cacheBlockMask
Addr cacheBlockMask
Address Mask for a cache block (e.g.
Definition: lsq.hh:623
gem5::minor::LSQ::numAccessesInDTLB
unsigned int numAccessesInDTLB
Number of requests in the DTLB in the requests queue.
Definition: lsq.hh:607
gem5::minor::LSQ::LSQRequest::markDelayed
void markDelayed()
BaseMMU::Translation interface.
Definition: lsq.hh:196
gem5::minor::LSQ::step
void step()
Step checks the queues to see if their are issuable transfers which were not otherwise picked up by t...
Definition: lsq.cc:1476
std::vector< RequestPtr >
gem5::minor::LSQ::SpecialDataRequest::stepToNextPacket
void stepToNextPacket()
Step on numIssuedFragments.
Definition: lsq.hh:302
gem5::minor::LSQ::needsToTick
bool needsToTick()
May need to be ticked next cycle as one of the queues contains an actionable transfers or address tra...
Definition: lsq.cc:1564
gem5::minor::LSQ::lineWidth
const unsigned int lineWidth
Memory system access width (and snap) in bytes.
Definition: lsq.hh:552
gem5::minor::LSQ::pushFailedRequest
void pushFailedRequest(MinorDynInstPtr inst)
Push a predicate failed-representing request into the queues just to maintain commit order.
Definition: lsq.cc:1667
gem5::PacketDataPtr
uint8_t * PacketDataPtr
Definition: packet.hh:71
gem5::minor::LSQ::LSQRequest::Complete
@ Complete
Definition: lsq.hh:189
gem5::minor::LSQ::lastMemBarrier
std::vector< InstSeqNum > lastMemBarrier
Most recent execSeqNum of a memory barrier instruction or 0 if there are no in-flight barriers.
Definition: lsq.hh:542
gem5::minor::LSQ::BarrierDataRequest
Request for doing barrier accounting in the store buffer.
Definition: lsq.hh:334
gem5::minor::LSQ::SplitDataRequest::makeFragmentRequests
void makeFragmentRequests()
Make all the Requests for this transfer's fragments so that those requests can be sent for address tr...
Definition: lsq.cc:420
gem5::minor::LSQ::LSQQueue
Queue< LSQRequestPtr, ReportTraitsPtrAdaptor< LSQRequestPtr >, NoBubbleTraits< LSQRequestPtr > > LSQQueue
The LSQ consists of three queues: requests, transfers and the store buffer storeBuffer.
Definition: lsq.hh:561
gem5::minor::LSQ::BarrierDataRequest::isBarrier
bool isBarrier()
Is this a request a barrier?
Definition: lsq.hh:337
gem5::minor::LSQ::SplitDataRequest::sentAllPackets
bool sentAllPackets()
Have we stepped past the end of fragmentPackets?
Definition: lsq.hh:458
gem5::minor::LSQ::SpecialDataRequest::SpecialDataRequest
SpecialDataRequest(LSQ &port_, MinorDynInstPtr inst_)
Definition: lsq.hh:315
gem5::minor::LSQ::SingleDataRequest::finish
void finish(const Fault &fault_, const RequestPtr &request_, ThreadContext *tc, BaseMMU::Mode mode)
TLB interace.
Definition: lsq.cc:272
gem5::minor::LSQ::SingleDataRequest::startAddrTranslation
void startAddrTranslation()
Send single translation request.
Definition: lsq.cc:302
gem5::minor::LSQ::LSQRequest::Translated
@ Translated
Definition: lsq.hh:174
gem5::minor::LSQ::LSQRequest::skippedMemAccess
bool skippedMemAccess()
Was no memory access attempted for this request?
Definition: lsq.hh:216
gem5::RefCountingPtr< MinorDynInst >
gem5::minor::LSQ::LSQRequest::containsAddrRangeOf
static AddrRangeCoverage containsAddrRangeOf(Addr req1_addr, unsigned int req1_size, Addr req2_addr, unsigned int req2_size)
Does address range req1 (req1_addr to req1_addr + req1_size - 1) fully cover, partially cover or not ...
Definition: lsq.cc:122
packet.hh
gem5::minor::LSQ::SplitDataRequest::numIssuedFragments
unsigned int numIssuedFragments
Number of fragments already issued (<= numFragments)
Definition: lsq.hh:409
gem5::minor::LSQ::LSQRequest::~LSQRequest
virtual ~LSQRequest()
Definition: lsq.cc:1461
gem5::minor::LSQ::LSQRequest
Derived SenderState to carry data access info.
Definition: lsq.hh:127
gem5::minor::LSQ::SpecialDataRequest::sentAllPackets
bool sentAllPackets()
Has no packets to send.
Definition: lsq.hh:305
gem5::Named
Interface for things with names.
Definition: named.hh:38
gem5::minor::LSQ::isDrained
bool isDrained()
Is there nothing left in the LSQ.
Definition: lsq.cc:1557
gem5::minor::LSQ::SplitDataRequest::hasPacketsInMemSystem
bool hasPacketsInMemSystem()
True if this request has any issued packets in the memory system and so can't be interrupted until it...
Definition: lsq.hh:454
gem5::minor::LSQ::SplitDataRequest::numInTranslationFragments
unsigned int numInTranslationFragments
Number of fragments in the address translation mechanism.
Definition: lsq.hh:400
gem5::minor::LSQ::LSQRequest::data
PacketDataPtr data
Dynamically allocated and populated data carried for building write packets.
Definition: lsq.hh:144
gem5::minor::LSQ::~LSQ
virtual ~LSQ()
Definition: lsq.cc:1458
gem5::minor::LSQ::StoreBuffer::canForwardDataToLoad
AddrRangeCoverage canForwardDataToLoad(LSQRequestPtr request, unsigned int &found_slot)
Look for a store which satisfies the given load.
Definition: lsq.cc:764
gem5::Flags< FlagsType >
gem5::minor::LSQ::SingleDataRequest::stepToNextPacket
void stepToNextPacket()
Remember that the packet has been sent.
Definition: lsq.hh:368
gem5::minor::LSQ::execute
Execute & execute
Definition: lsq.hh:73
gem5::minor::LSQ::minorTrace
void minorTrace() const
Definition: lsq.cc:1674
gem5::minor::LSQ::clearMemBarrier
void clearMemBarrier(MinorDynInstPtr inst)
Clear a barrier (if it's the last one marked up in lastMemBarrier)
Definition: lsq.cc:259
gem5::minor::LSQ::SpecialDataRequest::hasPacketsInMemSystem
bool hasPacketsInMemSystem()
Never sends any requests.
Definition: lsq.hh:308
gem5::minor::LSQ::StoreBuffer::insert
void insert(LSQRequestPtr request)
Insert a request at the back of the queue.
Definition: lsq.cc:742
gem5::minor::LSQ::LSQRequest::Failed
@ Failed
Definition: lsq.hh:175
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::minor::LSQ::LSQRequest::disableMemAccess
void disableMemAccess()
Definition: lsq.cc:115
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:248
gem5::minor::LSQ::SpecialDataRequest::retireResponse
void retireResponse(PacketPtr packet_)
Keep the given packet as the response packet LSQRequest::packet.
Definition: lsq.hh:312
gem5::minor::LSQ::getDcachePort
MinorCPU::MinorCPUPort & getDcachePort()
Return the raw-bindable port.
Definition: lsq.hh:732
gem5::minor::LSQ::SingleDataRequest::hasPacketsInMemSystem
bool hasPacketsInMemSystem()
Has packet been sent.
Definition: lsq.hh:371
gem5::minor::LSQ::getLastMemBarrier
InstSeqNum getLastMemBarrier(ThreadID thread_id) const
Get the execSeqNum of the last issued memory barrier.
Definition: lsq.hh:699
gem5::minor::LSQ::StoreBuffer::isDrained
bool isDrained() const
Drained if there is absolutely nothing left in the buffer.
Definition: lsq.hh:529
gem5::minor::LSQ::StoreBuffer
Store buffer.
Definition: lsq.hh:472
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:291
gem5::minor::LSQ::SplitDataRequest::numFragments
unsigned int numFragments
Number of fragments this request is split into.
Definition: lsq.hh:397
gem5::minor::LSQ::LSQRequest::inst
MinorDynInstPtr inst
Instruction which made this request.
Definition: lsq.hh:136
gem5::minor::LSQ::SpecialDataRequest
Special request types that don't actually issue memory requests.
Definition: lsq.hh:285
gem5::minor::LSQ::LSQRequest::stepToNextPacket
virtual void stepToNextPacket()=0
Step to the next packet for the next call to getHeadPacket.
gem5::minor::LSQ::LSQRequest::StoreBufferIssuing
@ StoreBufferIssuing
Definition: lsq.hh:183
gem5::minor::LSQ::canRequest
bool canRequest()
Is their space in the request queue to be able to push a request by issuing an isMemRef instruction.
Definition: lsq.hh:670
gem5::minor::LSQ::DcachePort::isSnooping
bool isSnooping() const override
Determine if this request port is snooping or not.
Definition: lsq.hh:113
gem5::minor::LSQ::SplitDataRequest::getHeadPacket
PacketPtr getHeadPacket()
Get the head packet as counted by numIssuedFragments.
Definition: lsq.cc:609
gem5::minor::LSQ::LSQ
LSQ(std::string name_, std::string dcache_port_name_, MinorCPU &cpu_, Execute &execute_, unsigned int max_accesses_in_memory_system, unsigned int line_width, unsigned int requests_queue_size, unsigned int transfers_queue_size, unsigned int store_buffer_size, unsigned int store_buffer_cycle_store_limit)
Definition: lsq.cc:1403
gem5::minor::LSQ::StoreBuffer::step
void step()
Try to issue more stores to memory.
Definition: lsq.cc:844
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::minor::LSQ::LSQRequest::setState
void setState(LSQRequestState new_state)
Set state and output trace output.
Definition: lsq.cc:171
gem5::minor::LSQ::recvReqRetry
void recvReqRetry()
Definition: lsq.cc:1357
gem5::minor::LSQ::storeBuffer
StoreBuffer storeBuffer
Definition: lsq.hh:595
gem5::minor::LSQ::StoreBuffer::countIssuedStore
void countIssuedStore(LSQRequestPtr request)
Count a store being issued to memory by decrementing numUnissuedAccesses.
Definition: lsq.cc:835
gem5::minor::LSQ::LSQRequest::getHeadPacket
virtual PacketPtr getHeadPacket()=0
Get the next packet to issue for this request.
gem5::minor::LSQ::DcachePort::recvReqRetry
void recvReqRetry() override
Called by the peer if sendTimingReq was called on this peer (causing recvTimingReq to be called on th...
Definition: lsq.hh:111
gem5::minor::LSQ::completeMemBarrierInst
void completeMemBarrierInst(MinorDynInstPtr inst, bool committed)
Complete a barrier instruction.
Definition: lsq.cc:914
gem5::minor::LSQ::SplitDataRequest::SplitDataRequest
SplitDataRequest(LSQ &port_, MinorDynInstPtr inst_, bool isLoad_, PacketDataPtr data_=NULL, uint64_t *res_=NULL)
Definition: lsq.cc:393
gem5::minor::LSQ::tryToSend
bool tryToSend(LSQRequestPtr request)
Try to send (or resend) a memory request's next/only packet to the memory system.
Definition: lsq.cc:1175
gem5::minor::makePacketForRequest
PacketPtr makePacketForRequest(const RequestPtr &request, bool isLoad, Packet::SenderState *sender_state, PacketDataPtr data)
Make a suitable packet for the given request.
Definition: lsq.cc:1697
gem5::minor::LSQ::popResponse
void popResponse(LSQRequestPtr response)
Sanity check and pop the head response.
Definition: lsq.cc:1522
gem5::minor::LSQ::FailedDataRequest::FailedDataRequest
FailedDataRequest(LSQ &port_, MinorDynInstPtr inst_)
Definition: lsq.hh:327
gem5::minor::LSQ::SplitDataRequest::fragmentPackets
std::vector< Packet * > fragmentPackets
Packets matching fragmentRequests to issue fragments to memory.
Definition: lsq.hh:419
gem5::minor::LSQ::LSQRequest::RequestNeedsRetry
@ RequestNeedsRetry
Definition: lsq.hh:180
flags
uint8_t flags
Definition: helpers.cc:66
gem5::minor::Queue::unreservedRemainingSpace
unsigned int unreservedRemainingSpace() const
Like remainingSpace but does not count reserved spaces.
Definition: buffers.hh:493
gem5::minor::LSQ::SingleDataRequest::packetSent
bool packetSent
Has the packet been at least sent to the memory system?
Definition: lsq.hh:358
gem5::Packet::SenderState
A virtual base opaque structure used to hold state associated with the packet (e.g....
Definition: packet.hh:465
gem5::minor::LSQ::SplitDataRequest::translationEvent
EventFunctionWrapper translationEvent
Event to step between translations.
Definition: lsq.hh:394
gem5::minor::LSQ::tryToSendToTransfers
void tryToSendToTransfers(LSQRequestPtr request)
Try and issue a memory access for a translated request at the head of the requests queue.
Definition: lsq.cc:960
gem5::minor::LSQ::SplitDataRequest::makeFragmentPackets
void makeFragmentPackets()
Make the packets to go with the requests so they can be sent to the memory system.
Definition: lsq.cc:534
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::minor::LSQ::LSQRequest::res
uint64_t * res
Res from pushRequest.
Definition: lsq.hh:156
gem5::minor::LSQ::moveFromRequestsToTransfers
void moveFromRequestsToTransfers(LSQRequestPtr request)
Move a request between queues.
Definition: lsq.cc:1273
gem5::GEM5_DEPRECATED_NAMESPACE
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi)
gem5::minor::LSQ::SplitDataRequest::fragmentRequests
std::vector< RequestPtr > fragmentRequests
Fragment Requests corresponding to the address ranges of each fragment.
Definition: lsq.hh:416
gem5::minor::LSQ::DcachePort::recvTimingResp
bool recvTimingResp(PacketPtr pkt) override
Receive a timing response from the peer.
Definition: lsq.hh:108
gem5::minor::LSQ::StoreBuffer::slots
std::deque< LSQRequestPtr > slots
Queue of store requests on their way to memory.
Definition: lsq.hh:486
gem5::minor::LSQ::LSQRequest::InTranslation
@ InTranslation
Definition: lsq.hh:173
gem5::minor::LSQ::numAccessesInMemorySystem
unsigned int numAccessesInMemorySystem
Count of the number of mem.
Definition: lsq.hh:604
gem5::minor::LSQ::canSendToMemorySystem
bool canSendToMemorySystem()
Can a request be sent to the memory system.
Definition: lsq.cc:1290
gem5::minor::LSQ::SplitDataRequest::~SplitDataRequest
~SplitDataRequest()
Definition: lsq.cc:410
gem5::minor::LSQ::SplitDataRequest::stepToNextPacket
void stepToNextPacket()
Step on numIssuedFragments.
Definition: lsq.cc:617
gem5::minor::LSQ::LSQRequest::StoreBufferNeedsRetry
@ StoreBufferNeedsRetry
Definition: lsq.hh:185
gem5::minor::LSQ::SingleDataRequest::getHeadPacket
PacketPtr getHeadPacket()
Get the head packet as counted by numIssuedFragments.
Definition: lsq.hh:365
gem5::EventFunctionWrapper
Definition: eventq.hh:1115
gem5::minor::LSQ::inMemorySystemLimit
const unsigned int inMemorySystemLimit
Maximum number of in-flight accesses issued to the memory system.
Definition: lsq.hh:549
gem5::BaseMMU::Translation
Definition: mmu.hh:58
gem5::minor::LSQ::LSQRequest::startAddrTranslation
virtual void startAddrTranslation()=0
Start the address translation process for this request.
gem5::minor::LSQ::StoreBuffer::canInsert
bool canInsert() const
Can a new request be inserted into the queue?
Definition: lsq.cc:721
gem5::minor::LSQ::dcachePort
DcachePort dcachePort
Definition: lsq.hh:121
gem5::minor::LSQ::LSQRequest::skipped
bool skipped
Was skipped.
Definition: lsq.hh:161
gem5::minor::LSQ::LSQRequest::state
LSQRequestState state
Definition: lsq.hh:192
gem5::X86ISA::os
Bitfield< 17 > os
Definition: misc.hh:803
gem5::minor::LSQ::accessesInFlight
bool accessesInFlight() const
Are there any accesses other than normal cached loads in the memory system or having received respons...
Definition: lsq.hh:690
gem5::minor::LSQ::numAccessesIssuedToMemory
unsigned int numAccessesIssuedToMemory
The number of accesses which have been issued to the memory system but have not been committed/discar...
Definition: lsq.hh:616
gem5::minor::LSQ::LSQRequest::completeDisabledMemAccess
void completeDisabledMemAccess()
Definition: lsq.cc:98
gem5::minor::LSQ::recvTimingSnoopReq
void recvTimingSnoopReq(PacketPtr pkt)
Definition: lsq.cc:1763
gem5::minor::LSQ::operator<<
friend std::ostream & operator<<(std::ostream &os, MemoryState state)
Print MemoryState values as shown in the enum definition.
Definition: lsq.cc:1746
std::deque< LSQRequestPtr >
gem5::minor::Execute
Execute stage.
Definition: execute.hh:68
gem5::minor::LSQ::LSQRequest::isTranslationDelayed
bool isTranslationDelayed
Address translation is delayed due to table walk.
Definition: lsq.hh:168
gem5::minor::LSQ::StoreBuffer::minorTrace
void minorTrace() const
Report queue contents for MinorTrace.
Definition: lsq.cc:931
gem5::minor::LSQ::SplitDataRequest::numRetiredFragments
unsigned int numRetiredFragments
Number of fragments retired back to this request.
Definition: lsq.hh:412
gem5::minor::LSQ::DcachePort::recvFunctionalSnoop
void recvFunctionalSnoop(PacketPtr pkt) override
Receive a functional snoop request packet from the peer.
Definition: lsq.hh:118
gem5::minor::LSQ::SingleDataRequest
SingleDataRequest is used for requests that don't fragment.
Definition: lsq.hh:346
gem5::minor::LSQ::LSQRequest::port
LSQ & port
Owning port.
Definition: lsq.hh:133
gem5::minor::LSQ::MemoryRunning
@ MemoryRunning
Definition: lsq.hh:79
gem5::minor::LSQ::LSQRequest::LSQRequest
LSQRequest(LSQ &port_, MinorDynInstPtr inst_, bool isLoad_, PacketDataPtr data_=NULL, uint64_t *res_=NULL)
Definition: lsq.cc:60
gem5::minor::NoBubbleTraits
...
Definition: buffers.hh:122
gem5::minor::LSQ::LSQRequest::isBarrier
virtual bool isBarrier()
Is this a request a barrier?
Definition: lsq.cc:159
gem5::minor::LSQ::transfers
LSQQueue transfers
Once issued to memory (or, for stores, just had their state changed to StoreToStoreBuffer) LSQRequest...
Definition: lsq.hh:584
gem5::minor::LSQ::LSQRequest::NotIssued
@ NotIssued
Definition: lsq.hh:172
gem5::minor::LSQ::SplitDataRequest
Definition: lsq.hh:390
gem5::minor::LSQ::retryRequest
LSQRequestPtr retryRequest
The request (from either requests or the store buffer) which is currently waiting have its memory acc...
Definition: lsq.hh:620
gem5::InstSeqNum
uint64_t InstSeqNum
Definition: inst_seq.hh:40
buffers.hh
gem5::minor::LSQ::SplitDataRequest::startAddrTranslation
void startAddrTranslation()
Start a loop of do { sendNextFragmentToTranslation ; translateTiming ; finish } while (numTranslatedF...
Definition: lsq.cc:584
gem5::minor::LSQ::numStoresInTransfers
unsigned int numStoresInTransfers
The number of stores in the transfers queue.
Definition: lsq.hh:611
gem5::minor::LSQ::StoreBuffer::deleteRequest
void deleteRequest(LSQRequestPtr request)
Delete the given request and free the slot it occupied.
Definition: lsq.cc:728
gem5::minor::LSQ::SingleDataRequest::retireResponse
void retireResponse(PacketPtr packet_)
Keep the given packet as the response packet LSQRequest::packet.
Definition: lsq.cc:326
gem5::minor::LSQ::recvTimingResp
bool recvTimingResp(PacketPtr pkt)
Memory interface.
Definition: lsq.cc:1297
gem5::minor::LSQ::cpu
MinorCPU & cpu
My owner(s)
Definition: lsq.hh:72
trace.hh
gem5::minor::LSQ::pushRequest
Fault pushRequest(MinorDynInstPtr inst, bool isLoad, uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res, AtomicOpFunctorPtr amo_op, const std::vector< bool > &byte_enable=std::vector< bool >())
Single interface for readMem/writeMem/amoMem to issue requests into the LSQ.
Definition: lsq.cc:1584
gem5::AtomicOpFunctorPtr
std::unique_ptr< AtomicOpFunctor > AtomicOpFunctorPtr
Definition: amo.hh:242
gem5::minor::LSQ::SplitDataRequest::numTranslatedFragments
unsigned int numTranslatedFragments
Number of fragments that have completed address translation, (numTranslatedFragments + numInTranslati...
Definition: lsq.hh:406
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::minor::LSQ::LSQRequest::reportData
void reportData(std::ostream &os) const
MinorTrace report interface.
Definition: lsq.cc:187
gem5::minor::LSQ::LSQRequest::hasPacketsInMemSystem
virtual bool hasPacketsInMemSystem()=0
True if this request has any issued packets in the memory system and so can't be interrupted until it...
gem5::minor::LSQ::LSQRequest::isComplete
bool isComplete() const
Has this request been completed.
Definition: lsq.cc:179
gem5::minor::LSQ::sendStoreToStoreBuffer
void sendStoreToStoreBuffer(LSQRequestPtr request)
A store has been committed, please move it to the store buffer.
Definition: lsq.cc:1544
gem5::minor::LSQ::findResponse
LSQRequestPtr findResponse(MinorDynInstPtr inst)
Returns a response if it's at the head of the transfers queue and it's either complete or can be sent...
Definition: lsq.cc:1487
gem5::minor::LSQ::canPushIntoStoreBuffer
bool canPushIntoStoreBuffer() const
Must check this before trying to insert into the store buffer.
Definition: lsq.hh:682
gem5::minor::LSQ::FullAddrRangeCoverage
@ FullAddrRangeCoverage
Definition: lsq.hh:91
gem5::minor::LSQ::SingleDataRequest::packetInFlight
bool packetInFlight
Has my only packet been sent to the memory system but has not yet been responded to.
Definition: lsq.hh:355
gem5::minor::LSQ::StoreBuffer::lsq
LSQ & lsq
My owner.
Definition: lsq.hh:476
gem5::minor::LSQ::SpecialDataRequest::startAddrTranslation
void startAddrTranslation()
Send single translation request.
Definition: lsq.hh:295
gem5::minor::LSQ::StoreBuffer::numSlots
const unsigned int numSlots
Number of slots, this is a bound on the size of slots.
Definition: lsq.hh:479
gem5::minor::LSQ::LSQRequest::StoreInStoreBuffer
@ StoreInStoreBuffer
Definition: lsq.hh:181
gem5::ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:235
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:74
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::minor::LSQ::DcachePort::lsq
LSQ & lsq
My owner.
Definition: lsq.hh:100
gem5::minor::LSQ::SingleDataRequest::SingleDataRequest
SingleDataRequest(LSQ &port_, MinorDynInstPtr inst_, bool isLoad_, PacketDataPtr data_=NULL, uint64_t *res_=NULL)
Definition: lsq.hh:382

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