gem5  v21.1.0.2
lsq.hh
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37 
45 #ifndef __CPU_MINOR_NEW_LSQ_HH__
46 #define __CPU_MINOR_NEW_LSQ_HH__
47 
48 #include <string>
49 #include <vector>
50 
51 #include "base/named.hh"
52 #include "cpu/minor/buffers.hh"
53 #include "cpu/minor/cpu.hh"
54 #include "cpu/minor/pipe_data.hh"
55 #include "cpu/minor/trace.hh"
56 #include "mem/packet.hh"
57 
58 namespace gem5
59 {
60 
62 namespace minor
63 {
64 
65 /* Forward declaration */
66 class Execute;
67 
68 class LSQ : public Named
69 {
70  protected:
74 
76 
77  protected:
80  {
81  MemoryRunning, /* Default. Step dcache queues when possible. */
82  MemoryNeedsRetry /* Request rejected, will be asked to retry */
83  };
84 
86  friend std::ostream &operator <<(std::ostream &os,
88 
91  {
92  PartialAddrRangeCoverage, /* Two ranges partly overlap */
93  FullAddrRangeCoverage, /* One range fully covers another */
94  NoAddrRangeCoverage /* Two ranges are disjoint */
95  };
96 
99  {
100  protected:
103 
104  public:
105  DcachePort(std::string name, LSQ &lsq_, MinorCPU &cpu) :
106  MinorCPU::MinorCPUPort(name, cpu), lsq(lsq_)
107  { }
108 
109  protected:
110  bool recvTimingResp(PacketPtr pkt) override
111  { return lsq.recvTimingResp(pkt); }
112 
113  void recvReqRetry() override { lsq.recvReqRetry(); }
114 
115  bool isSnooping() const override { return true; }
116 
117  void recvTimingSnoopReq(PacketPtr pkt) override
118  { return lsq.recvTimingSnoopReq(pkt); }
119 
120  void recvFunctionalSnoop(PacketPtr pkt) override { }
121  };
122 
124 
125  public:
129  class LSQRequest :
130  public BaseMMU::Translation, /* For TLB lookups */
131  public Packet::SenderState /* For packing into a Packet */
132  {
133  public:
136 
138 
141 
144  bool isLoad;
145 
149 
150  /* Requests carry packets on their way to the memory system.
151  * When a Packet returns from the memory system, its
152  * request needs to have its packet updated as this
153  * may have changed in flight */
155 
158 
160  uint64_t *res;
161 
165  bool skipped;
166 
170 
173 
175  {
176  NotIssued, /* Newly created */
177  InTranslation, /* TLB accessed, no reply yet */
178  Translated, /* Finished address translation */
179  Failed, /* The starting start of FailedDataRequests */
180  RequestIssuing, /* Load/store issued to memory in the requests
181  queue */
182  StoreToStoreBuffer, /* Store in transfers on its way to the
183  store buffer */
184  RequestNeedsRetry, /* Retry needed for load */
185  StoreInStoreBuffer, /* Store in the store buffer, before issuing
186  a memory transfer */
187  StoreBufferIssuing, /* Store in store buffer and has been
188  issued */
189  StoreBufferNeedsRetry, /* Retry needed for store */
190  /* All completed states. Includes
191  completed loads, TLB faults and skipped requests whose
192  seqNum's no longer match */
194  };
195 
197 
198  protected:
201 
204  void tryToSuppressFault();
205 
206  void disableMemAccess();
208 
209  public:
210  LSQRequest(LSQ &port_, MinorDynInstPtr inst_, bool isLoad_,
211  RegIndex zero_reg, PacketDataPtr data_ = NULL,
212  uint64_t *res_ = NULL);
213 
214  virtual ~LSQRequest();
215 
216  public:
218  void makePacket();
219 
221  bool skippedMemAccess() { return skipped; }
222 
225  void setSkipped() { skipped = true; }
226 
230  Addr req1_addr, unsigned int req1_size,
231  Addr req2_addr, unsigned int req2_size);
232 
236 
239  virtual void startAddrTranslation() = 0;
240 
245  virtual PacketPtr getHeadPacket() = 0;
246 
248  virtual void stepToNextPacket() = 0;
249 
251  virtual bool sentAllPackets() = 0;
252 
255  virtual bool hasPacketsInMemSystem() = 0;
256 
259  virtual void retireResponse(PacketPtr packet_) = 0;
260 
262  virtual bool isBarrier();
263 
267 
269  void setState(LSQRequestState new_state);
270 
274  bool isComplete() const;
275 
277  void reportData(std::ostream &os) const;
278  };
279 
281 
282  friend std::ostream & operator <<(std::ostream &os,
284 
285  friend std::ostream & operator <<(std::ostream &os,
287 
288  protected:
291  {
292  protected:
294  void finish(const Fault &fault_, const RequestPtr &request_,
296  { }
297 
298  public:
301 
304  { fatal("No packets in a SpecialDataRequest"); }
305 
307  void stepToNextPacket() { }
308 
310  bool sentAllPackets() { return true; }
311 
313  bool hasPacketsInMemSystem() { return false; }
314 
317  void retireResponse(PacketPtr packet_) { }
318 
319  public:
321  /* Say this is a load, not actually relevant */
322  LSQRequest(port_, inst_, true, port_.zeroReg, NULL, 0)
323  { }
324  };
325 
330  {
331  public:
333  SpecialDataRequest(port_, inst_)
334  { state = Failed; }
335  };
336 
340  {
341  public:
342  bool isBarrier() { return true; }
343 
344  public:
346  SpecialDataRequest(port_, inst_)
347  { state = Complete; }
348  };
349 
352  {
353  protected:
355  void finish(const Fault &fault_, const RequestPtr &request_,
357 
361 
364 
365  public:
367  void startAddrTranslation();
368 
371 
373  void stepToNextPacket() { packetInFlight = true; packetSent = true; }
374 
377 
380  bool sentAllPackets() { return packetSent; }
381 
384  void retireResponse(PacketPtr packet_);
385 
386  public:
388  bool isLoad_, PacketDataPtr data_ = NULL, uint64_t *res_ = NULL) :
389  LSQRequest(port_, inst_, isLoad_, port_.zeroReg, data_, res_),
390  packetInFlight(false),
391  packetSent(false)
392  { }
393  };
394 
396  {
397  protected:
400  protected:
402  unsigned int numFragments;
403 
406 
412 
414  unsigned int numIssuedFragments;
415 
417  unsigned int numRetiredFragments;
418 
422 
425 
426  protected:
428  void finish(const Fault &fault_, const RequestPtr &request_,
430 
431  public:
432  SplitDataRequest(LSQ &port_, MinorDynInstPtr inst_,
433  bool isLoad_, PacketDataPtr data_ = NULL,
434  uint64_t *res_ = NULL);
435 
437 
438  public:
441  void makeFragmentRequests();
442 
445  void makeFragmentPackets();
446 
451  void startAddrTranslation();
452 
455 
457  void stepToNextPacket();
458 
461 
465 
468  void retireResponse(PacketPtr packet_);
469 
472  };
473 
477  class StoreBuffer : public Named
478  {
479  public:
482 
484  const unsigned int numSlots;
485 
487  const unsigned int storeLimitPerCycle;
488 
489  public:
492 
495  unsigned int numUnissuedAccesses;
496 
497  public:
498  StoreBuffer(std::string name_, LSQ &lsq_,
499  unsigned int store_buffer_size,
500  unsigned int store_limit_per_cycle);
501 
502  public:
504  bool canInsert() const;
505 
507  void deleteRequest(LSQRequestPtr request);
508 
510  void insert(LSQRequestPtr request);
511 
518  unsigned int &found_slot);
519 
522  void forwardStoreData(LSQRequestPtr load, unsigned int slot_number);
523 
526  unsigned int numUnissuedStores() { return numUnissuedAccesses; }
527 
531  void countIssuedStore(LSQRequestPtr request);
532 
534  bool isDrained() const { return slots.empty(); }
535 
537  void step();
538 
540  void minorTrace() const;
541  };
542 
543  protected:
548 
549  public:
552 
554  const unsigned int inMemorySystemLimit;
555 
557  const unsigned int lineWidth;
558 
559  public:
563  typedef Queue<LSQRequestPtr,
567 
581 
590 
591  /* The store buffer contains committed cacheable stores on
592  * their way to memory decoupled from subsequence instruction execution.
593  * Before trying to issue a cacheable read from 'requests' to memory,
594  * the store buffer is checked to see if a previous store contains the
595  * needed data (StoreBuffer::canForwardDataToLoad) which can be
596  * forwarded in lieu of a memory access. If there are outstanding
597  * stores in the transfers queue, they must be promoted to the store
598  * buffer (and so be commited) before they can be correctly checked
599  * for forwarding. */
601 
602  protected:
610 
612  unsigned int numAccessesInDTLB;
613 
616  unsigned int numStoresInTransfers;
617 
622 
626 
629 
630  protected:
634  void tryToSendToTransfers(LSQRequestPtr request);
635 
639  bool tryToSend(LSQRequestPtr request);
640 
642  void clearMemBarrier(MinorDynInstPtr inst);
643 
646 
648  bool canSendToMemorySystem();
649 
651  void threadSnoop(LSQRequestPtr request);
652 
653  public:
654  LSQ(std::string name_, std::string dcache_port_name_,
655  MinorCPU &cpu_, Execute &execute_,
656  unsigned int max_accesses_in_memory_system, unsigned int line_width,
657  unsigned int requests_queue_size, unsigned int transfers_queue_size,
658  unsigned int store_buffer_size,
659  unsigned int store_buffer_cycle_store_limit,
660  RegIndex zero_reg);
661 
662  virtual ~LSQ();
663 
664  public:
672  void step();
673 
676  bool canRequest() { return requests.unreservedRemainingSpace() != 0; }
677 
683 
685  void popResponse(LSQRequestPtr response);
686 
688  bool canPushIntoStoreBuffer() const { return storeBuffer.canInsert(); }
689 
692 
696  bool accessesInFlight() const
697  { return numAccessesIssuedToMemory != 0; }
698 
703 
706  { return lastMemBarrier[thread_id]; }
707 
709  bool isDrained();
710 
713  bool needsToTick();
714 
718  bool committed);
719 
722  Fault pushRequest(MinorDynInstPtr inst, bool isLoad, uint8_t *data,
723  unsigned int size, Addr addr, Request::Flags flags,
724  uint64_t *res, AtomicOpFunctorPtr amo_op,
725  const std::vector<bool>& byte_enable =
727 
731 
733  bool recvTimingResp(PacketPtr pkt);
734  void recvReqRetry();
735  void recvTimingSnoopReq(PacketPtr pkt);
736 
739 
740  void minorTrace() const;
741 };
742 
746 PacketPtr makePacketForRequest(const RequestPtr &request, bool isLoad,
747  Packet::SenderState *sender_state = NULL, PacketDataPtr data = NULL);
748 
749 } // namespace minor
750 } // namespace gem5
751 
752 #endif /* __CPU_MINOR_NEW_LSQ_HH__ */
gem5::minor::LSQ
Definition: lsq.hh:68
gem5::minor::LSQ::LSQRequest::sentAllPackets
virtual bool sentAllPackets()=0
Have all packets been sent?
pipe_data.hh
fatal
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:189
gem5::minor::LSQ::requests
LSQQueue requests
requests contains LSQRequests which have been issued to the TLB by calling ExecContext::readMem/write...
Definition: lsq.hh:580
gem5::minor::LSQ::LSQRequest::retireResponse
virtual void retireResponse(PacketPtr packet_)=0
Retire a response packet into the LSQRequest packet possibly completing this transfer.
gem5::minor::LSQ::LSQRequest::tryToSuppressFault
void tryToSuppressFault()
Instructions may want to suppress translation faults (e.g.
Definition: lsq.cc:81
gem5::minor::LSQ::SpecialDataRequest::getHeadPacket
PacketPtr getHeadPacket()
Get the head packet as counted by numIssuedFragments.
Definition: lsq.hh:303
gem5::minor::LSQ::LSQRequest::StoreToStoreBuffer
@ StoreToStoreBuffer
Definition: lsq.hh:182
gem5::minor::LSQ::SingleDataRequest::sentAllPackets
bool sentAllPackets()
packetInFlight can become false again, so need to check packetSent
Definition: lsq.hh:380
gem5::minor::LSQ::MemoryNeedsRetry
@ MemoryNeedsRetry
Definition: lsq.hh:82
gem5::MinorCPU::MinorCPUPort::MinorCPUPort
MinorCPUPort(const std::string &name_, MinorCPU &cpu_)
Definition: cpu.hh:113
gem5::minor::LSQ::StoreBuffer::StoreBuffer
StoreBuffer(std::string name_, LSQ &lsq_, unsigned int store_buffer_size, unsigned int store_limit_per_cycle)
Definition: lsq.cc:1681
gem5::minor::ReportTraitsPtrAdaptor
A similar adaptor but for elements held by pointer ElemType should implement ReportIF.
Definition: buffers.hh:108
gem5::minor::LSQ::DcachePort::DcachePort
DcachePort(std::string name, LSQ &lsq_, MinorCPU &cpu)
Definition: lsq.hh:105
gem5::Port::name
const std::string name() const
Return port name (for DPRINTF).
Definition: port.hh:111
gem5::minor::LSQ::LSQRequest::request
RequestPtr request
The underlying request of this LSQRequest.
Definition: lsq.hh:157
gem5::minor::LSQ::issuedMemBarrierInst
void issuedMemBarrierInst(MinorDynInstPtr inst)
A memory barrier instruction has been issued, remember its execSeqNum that we can avoid issuing memor...
Definition: lsq.cc:1714
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::minor::LSQ::SplitDataRequest::retireResponse
void retireResponse(PacketPtr packet_)
For loads, paste the response data into the main response packet.
Definition: lsq.cc:627
gem5::minor::LSQ::LSQRequest::isLoad
bool isLoad
Load/store indication used for building packet.
Definition: lsq.hh:144
gem5::minor::LSQ::AddrRangeCoverage
AddrRangeCoverage
Coverage of one address range with another.
Definition: lsq.hh:90
gem5::minor::LSQ::LSQRequest::RequestIssuing
@ RequestIssuing
Definition: lsq.hh:180
gem5::minor::LSQ::StoreBuffer::storeLimitPerCycle
const unsigned int storeLimitPerCycle
Maximum number of stores that can be issued per cycle.
Definition: lsq.hh:487
gem5::minor::LSQ::LSQRequest::makePacket
void makePacket()
Make a packet to use with the memory transaction.
Definition: lsq.cc:1726
gem5::minor::LSQ::LSQRequestPtr
LSQRequest * LSQRequestPtr
Definition: lsq.hh:280
gem5::minor::LSQ::threadSnoop
void threadSnoop(LSQRequestPtr request)
Snoop other threads monitors on memory system accesses.
Definition: lsq.cc:1779
gem5::minor::LSQ::LSQRequest::LSQRequestState
LSQRequestState
Definition: lsq.hh:174
gem5::minor::LSQ::PartialAddrRangeCoverage
@ PartialAddrRangeCoverage
Definition: lsq.hh:92
gem5::minor::LSQ::LSQRequest::packet
PacketPtr packet
Definition: lsq.hh:154
gem5::minor::LSQ::state
MemoryState state
Retry state of last issued memory transfer.
Definition: lsq.hh:551
gem5::minor::LSQ::LSQRequest::setSkipped
void setSkipped()
Set this request as having been skipped before a memory transfer was attempt.
Definition: lsq.hh:225
gem5::MinorCPU::MinorCPUPort
Provide a non-protected base class for Minor's Ports as derived classes are created by Fetch1 and Exe...
Definition: cpu.hh:106
gem5::minor::LSQ::StoreBuffer::numUnissuedAccesses
unsigned int numUnissuedAccesses
Number of occupied slots which have not yet issued a memory access.
Definition: lsq.hh:495
gem5::BaseMMU::Mode
Mode
Definition: mmu.hh:53
gem5::minor::LSQ::SplitDataRequest::sendNextFragmentToTranslation
void sendNextFragmentToTranslation()
Part of the address translation loop, see startAddTranslation.
Definition: lsq.cc:704
gem5::minor::LSQ::NoAddrRangeCoverage
@ NoAddrRangeCoverage
Definition: lsq.hh:94
gem5::minor::LSQ::BarrierDataRequest::BarrierDataRequest
BarrierDataRequest(LSQ &port_, MinorDynInstPtr inst_)
Definition: lsq.hh:345
gem5::minor::LSQ::DcachePort
Exposable data port.
Definition: lsq.hh:98
named.hh
gem5::minor::LSQ::StoreBuffer::forwardStoreData
void forwardStoreData(LSQRequestPtr load, unsigned int slot_number)
Fill the given packet with appropriate date from slot slot_number.
Definition: lsq.cc:807
gem5::minor::LSQ::StoreBuffer::numUnissuedStores
unsigned int numUnissuedStores()
Number of stores in the store buffer which have not been completely issued to the memory system.
Definition: lsq.hh:526
gem5::minor::LSQ::LSQRequest::issuedToMemory
bool issuedToMemory
This in an access other than a normal cacheable load that's visited the memory system.
Definition: lsq.hh:169
gem5::minor::LSQ::SpecialDataRequest::finish
void finish(const Fault &fault_, const RequestPtr &request_, ThreadContext *tc, BaseMMU::Mode mode)
TLB interace.
Definition: lsq.hh:294
gem5::minor::LSQ::LSQRequest::needsToBeSentToStoreBuffer
bool needsToBeSentToStoreBuffer()
This request, once processed by the requests/transfers queues, will need to go to the store buffer.
Definition: lsq.cc:167
gem5::minor::Queue
Wrapper for a queue type to act as a pipeline stage input queue.
Definition: buffers.hh:404
gem5::minor::LSQ::FailedDataRequest
FailedDataRequest represents requests from instructions that failed their predicates but need to ride...
Definition: lsq.hh:329
gem5::MinorCPU::MinorCPUPort::cpu
MinorCPU & cpu
The enclosing cpu.
Definition: cpu.hh:110
cpu.hh
minor
gem5::minor::LSQ::DcachePort::recvTimingSnoopReq
void recvTimingSnoopReq(PacketPtr pkt) override
Receive a timing snoop request from the peer.
Definition: lsq.hh:117
gem5::MinorCPU
MinorCPU is an in-order CPU model with four fixed pipeline stages:
Definition: cpu.hh:85
gem5::minor::LSQ::MemoryState
MemoryState
State of memory access for head access.
Definition: lsq.hh:79
gem5::minor::LSQ::SplitDataRequest::finish
void finish(const Fault &fault_, const RequestPtr &request_, ThreadContext *tc, BaseMMU::Mode mode)
TLB response interface.
Definition: lsq.cc:337
gem5::minor::LSQ::cacheBlockMask
Addr cacheBlockMask
Address Mask for a cache block (e.g.
Definition: lsq.hh:628
gem5::minor::LSQ::numAccessesInDTLB
unsigned int numAccessesInDTLB
Number of requests in the DTLB in the requests queue.
Definition: lsq.hh:612
gem5::minor::LSQ::LSQRequest::markDelayed
void markDelayed()
BaseMMU::Translation interface.
Definition: lsq.hh:200
gem5::minor::LSQ::step
void step()
Step checks the queues to see if their are issuable transfers which were not otherwise picked up by t...
Definition: lsq.cc:1480
std::vector< RequestPtr >
gem5::minor::LSQ::SpecialDataRequest::stepToNextPacket
void stepToNextPacket()
Step on numIssuedFragments.
Definition: lsq.hh:307
gem5::minor::LSQ::needsToTick
bool needsToTick()
May need to be ticked next cycle as one of the queues contains an actionable transfers or address tra...
Definition: lsq.cc:1568
gem5::minor::LSQ::lineWidth
const unsigned int lineWidth
Memory system access width (and snap) in bytes.
Definition: lsq.hh:557
gem5::minor::LSQ::pushFailedRequest
void pushFailedRequest(MinorDynInstPtr inst)
Push a predicate failed-representing request into the queues just to maintain commit order.
Definition: lsq.cc:1663
gem5::PacketDataPtr
uint8_t * PacketDataPtr
Definition: packet.hh:71
gem5::minor::LSQ::zeroReg
const RegIndex zeroReg
Definition: lsq.hh:75
gem5::minor::LSQ::LSQRequest::Complete
@ Complete
Definition: lsq.hh:193
gem5::minor::LSQ::lastMemBarrier
std::vector< InstSeqNum > lastMemBarrier
Most recent execSeqNum of a memory barrier instruction or 0 if there are no in-flight barriers.
Definition: lsq.hh:547
gem5::minor::LSQ::BarrierDataRequest
Request for doing barrier accounting in the store buffer.
Definition: lsq.hh:339
gem5::minor::LSQ::SplitDataRequest::makeFragmentRequests
void makeFragmentRequests()
Make all the Requests for this transfer's fragments so that those requests can be sent for address tr...
Definition: lsq.cc:422
gem5::minor::LSQ::LSQQueue
Queue< LSQRequestPtr, ReportTraitsPtrAdaptor< LSQRequestPtr >, NoBubbleTraits< LSQRequestPtr > > LSQQueue
The LSQ consists of three queues: requests, transfers and the store buffer storeBuffer.
Definition: lsq.hh:566
gem5::minor::LSQ::BarrierDataRequest::isBarrier
bool isBarrier()
Is this a request a barrier?
Definition: lsq.hh:342
gem5::minor::LSQ::SplitDataRequest::sentAllPackets
bool sentAllPackets()
Have we stepped past the end of fragmentPackets?
Definition: lsq.hh:463
gem5::minor::LSQ::SpecialDataRequest::SpecialDataRequest
SpecialDataRequest(LSQ &port_, MinorDynInstPtr inst_)
Definition: lsq.hh:320
gem5::minor::LSQ::SingleDataRequest::finish
void finish(const Fault &fault_, const RequestPtr &request_, ThreadContext *tc, BaseMMU::Mode mode)
TLB interace.
Definition: lsq.cc:274
gem5::minor::LSQ::SingleDataRequest::startAddrTranslation
void startAddrTranslation()
Send single translation request.
Definition: lsq.cc:304
gem5::minor::LSQ::LSQRequest::Translated
@ Translated
Definition: lsq.hh:178
gem5::minor::LSQ::LSQRequest::skippedMemAccess
bool skippedMemAccess()
Was no memory access attempted for this request?
Definition: lsq.hh:221
gem5::RefCountingPtr< MinorDynInst >
gem5::minor::LSQ::LSQRequest::containsAddrRangeOf
static AddrRangeCoverage containsAddrRangeOf(Addr req1_addr, unsigned int req1_size, Addr req2_addr, unsigned int req2_size)
Does address range req1 (req1_addr to req1_addr + req1_size - 1) fully cover, partially cover or not ...
Definition: lsq.cc:124
packet.hh
gem5::minor::LSQ::SplitDataRequest::numIssuedFragments
unsigned int numIssuedFragments
Number of fragments already issued (<= numFragments)
Definition: lsq.hh:414
gem5::minor::LSQ::LSQRequest::~LSQRequest
virtual ~LSQRequest()
Definition: lsq.cc:1465
gem5::minor::LSQ::LSQRequest
Derived SenderState to carry data access info.
Definition: lsq.hh:129
gem5::minor::LSQ::SpecialDataRequest::sentAllPackets
bool sentAllPackets()
Has no packets to send.
Definition: lsq.hh:310
gem5::Named
Interface for things with names.
Definition: named.hh:38
gem5::minor::LSQ::isDrained
bool isDrained()
Is there nothing left in the LSQ.
Definition: lsq.cc:1561
gem5::minor::LSQ::SplitDataRequest::hasPacketsInMemSystem
bool hasPacketsInMemSystem()
True if this request has any issued packets in the memory system and so can't be interrupted until it...
Definition: lsq.hh:459
gem5::minor::LSQ::SplitDataRequest::numInTranslationFragments
unsigned int numInTranslationFragments
Number of fragments in the address translation mechanism.
Definition: lsq.hh:405
gem5::minor::LSQ::LSQRequest::data
PacketDataPtr data
Dynamically allocated and populated data carried for building write packets.
Definition: lsq.hh:148
gem5::minor::LSQ::~LSQ
virtual ~LSQ()
Definition: lsq.cc:1462
gem5::minor::LSQ::StoreBuffer::canForwardDataToLoad
AddrRangeCoverage canForwardDataToLoad(LSQRequestPtr request, unsigned int &found_slot)
Look for a store which satisfies the given load.
Definition: lsq.cc:766
gem5::Flags< FlagsType >
gem5::minor::LSQ::SingleDataRequest::stepToNextPacket
void stepToNextPacket()
Remember that the packet has been sent.
Definition: lsq.hh:373
gem5::minor::LSQ::execute
Execute & execute
Definition: lsq.hh:73
gem5::minor::LSQ::minorTrace
void minorTrace() const
Definition: lsq.cc:1670
gem5::minor::LSQ::LSQ
LSQ(std::string name_, std::string dcache_port_name_, MinorCPU &cpu_, Execute &execute_, unsigned int max_accesses_in_memory_system, unsigned int line_width, unsigned int requests_queue_size, unsigned int transfers_queue_size, unsigned int store_buffer_size, unsigned int store_buffer_cycle_store_limit, RegIndex zero_reg)
Definition: lsq.cc:1405
gem5::minor::LSQ::clearMemBarrier
void clearMemBarrier(MinorDynInstPtr inst)
Clear a barrier (if it's the last one marked up in lastMemBarrier)
Definition: lsq.cc:261
gem5::minor::LSQ::SpecialDataRequest::hasPacketsInMemSystem
bool hasPacketsInMemSystem()
Never sends any requests.
Definition: lsq.hh:313
gem5::minor::LSQ::StoreBuffer::insert
void insert(LSQRequestPtr request)
Insert a request at the back of the queue.
Definition: lsq.cc:744
gem5::minor::LSQ::LSQRequest::Failed
@ Failed
Definition: lsq.hh:179
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::minor::LSQ::LSQRequest::disableMemAccess
void disableMemAccess()
Definition: lsq.cc:117
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::minor::LSQ::SpecialDataRequest::retireResponse
void retireResponse(PacketPtr packet_)
Keep the given packet as the response packet LSQRequest::packet.
Definition: lsq.hh:317
gem5::minor::LSQ::getDcachePort
MinorCPU::MinorCPUPort & getDcachePort()
Return the raw-bindable port.
Definition: lsq.hh:738
gem5::minor::LSQ::SingleDataRequest::hasPacketsInMemSystem
bool hasPacketsInMemSystem()
Has packet been sent.
Definition: lsq.hh:376
gem5::minor::LSQ::getLastMemBarrier
InstSeqNum getLastMemBarrier(ThreadID thread_id) const
Get the execSeqNum of the last issued memory barrier.
Definition: lsq.hh:705
gem5::minor::LSQ::StoreBuffer::isDrained
bool isDrained() const
Drained if there is absolutely nothing left in the buffer.
Definition: lsq.hh:534
gem5::minor::LSQ::StoreBuffer
Store buffer.
Definition: lsq.hh:477
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::minor::LSQ::SplitDataRequest::numFragments
unsigned int numFragments
Number of fragments this request is split into.
Definition: lsq.hh:402
gem5::minor::LSQ::LSQRequest::inst
MinorDynInstPtr inst
Instruction which made this request.
Definition: lsq.hh:140
gem5::minor::LSQ::SpecialDataRequest
Special request types that don't actually issue memory requests.
Definition: lsq.hh:290
gem5::minor::LSQ::LSQRequest::stepToNextPacket
virtual void stepToNextPacket()=0
Step to the next packet for the next call to getHeadPacket.
gem5::minor::LSQ::LSQRequest::StoreBufferIssuing
@ StoreBufferIssuing
Definition: lsq.hh:187
gem5::minor::LSQ::canRequest
bool canRequest()
Is their space in the request queue to be able to push a request by issuing an isMemRef instruction.
Definition: lsq.hh:676
gem5::minor::LSQ::DcachePort::isSnooping
bool isSnooping() const override
Determine if this request port is snooping or not.
Definition: lsq.hh:115
gem5::minor::LSQ::SplitDataRequest::getHeadPacket
PacketPtr getHeadPacket()
Get the head packet as counted by numIssuedFragments.
Definition: lsq.cc:611
gem5::minor::LSQ::StoreBuffer::step
void step()
Try to issue more stores to memory.
Definition: lsq.cc:846
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::minor::LSQ::LSQRequest::setState
void setState(LSQRequestState new_state)
Set state and output trace output.
Definition: lsq.cc:173
gem5::minor::LSQ::recvReqRetry
void recvReqRetry()
Definition: lsq.cc:1359
gem5::minor::LSQ::storeBuffer
StoreBuffer storeBuffer
Definition: lsq.hh:600
gem5::minor::LSQ::StoreBuffer::countIssuedStore
void countIssuedStore(LSQRequestPtr request)
Count a store being issued to memory by decrementing numUnissuedAccesses.
Definition: lsq.cc:837
gem5::minor::LSQ::LSQRequest::getHeadPacket
virtual PacketPtr getHeadPacket()=0
Get the next packet to issue for this request.
gem5::minor::LSQ::DcachePort::recvReqRetry
void recvReqRetry() override
Called by the peer if sendTimingReq was called on this peer (causing recvTimingReq to be called on th...
Definition: lsq.hh:113
gem5::minor::LSQ::completeMemBarrierInst
void completeMemBarrierInst(MinorDynInstPtr inst, bool committed)
Complete a barrier instruction.
Definition: lsq.cc:916
gem5::minor::LSQ::SplitDataRequest::SplitDataRequest
SplitDataRequest(LSQ &port_, MinorDynInstPtr inst_, bool isLoad_, PacketDataPtr data_=NULL, uint64_t *res_=NULL)
Definition: lsq.cc:395
gem5::minor::LSQ::tryToSend
bool tryToSend(LSQRequestPtr request)
Try to send (or resend) a memory request's next/only packet to the memory system.
Definition: lsq.cc:1177
gem5::minor::makePacketForRequest
PacketPtr makePacketForRequest(const RequestPtr &request, bool isLoad, Packet::SenderState *sender_state, PacketDataPtr data)
Make a suitable packet for the given request.
Definition: lsq.cc:1693
gem5::minor::LSQ::popResponse
void popResponse(LSQRequestPtr response)
Sanity check and pop the head response.
Definition: lsq.cc:1526
gem5::minor::LSQ::FailedDataRequest::FailedDataRequest
FailedDataRequest(LSQ &port_, MinorDynInstPtr inst_)
Definition: lsq.hh:332
gem5::minor::LSQ::SplitDataRequest::fragmentPackets
std::vector< Packet * > fragmentPackets
Packets matching fragmentRequests to issue fragments to memory.
Definition: lsq.hh:424
gem5::minor::LSQ::LSQRequest::RequestNeedsRetry
@ RequestNeedsRetry
Definition: lsq.hh:184
gem5::minor::Queue::unreservedRemainingSpace
unsigned int unreservedRemainingSpace() const
Like remainingSpace but does not count reserved spaces.
Definition: buffers.hh:493
gem5::minor::LSQ::SingleDataRequest::packetSent
bool packetSent
Has the packet been at least sent to the memory system?
Definition: lsq.hh:363
gem5::Packet::SenderState
A virtual base opaque structure used to hold state associated with the packet (e.g....
Definition: packet.hh:457
gem5::minor::LSQ::SplitDataRequest::translationEvent
EventFunctionWrapper translationEvent
Event to step between translations.
Definition: lsq.hh:399
gem5::minor::LSQ::tryToSendToTransfers
void tryToSendToTransfers(LSQRequestPtr request)
Try and issue a memory access for a translated request at the head of the requests queue.
Definition: lsq.cc:962
gem5::minor::LSQ::SplitDataRequest::makeFragmentPackets
void makeFragmentPackets()
Make the packets to go with the requests so they can be sent to the memory system.
Definition: lsq.cc:536
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::minor::LSQ::LSQRequest::res
uint64_t * res
Res from pushRequest.
Definition: lsq.hh:160
gem5::minor::LSQ::moveFromRequestsToTransfers
void moveFromRequestsToTransfers(LSQRequestPtr request)
Move a request between queues.
Definition: lsq.cc:1275
gem5::GEM5_DEPRECATED_NAMESPACE
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi)
gem5::minor::LSQ::SplitDataRequest::fragmentRequests
std::vector< RequestPtr > fragmentRequests
Fragment Requests corresponding to the address ranges of each fragment.
Definition: lsq.hh:421
gem5::minor::LSQ::DcachePort::recvTimingResp
bool recvTimingResp(PacketPtr pkt) override
Receive a timing response from the peer.
Definition: lsq.hh:110
gem5::minor::LSQ::StoreBuffer::slots
std::deque< LSQRequestPtr > slots
Queue of store requests on their way to memory.
Definition: lsq.hh:491
gem5::minor::LSQ::LSQRequest::InTranslation
@ InTranslation
Definition: lsq.hh:177
gem5::minor::LSQ::numAccessesInMemorySystem
unsigned int numAccessesInMemorySystem
Count of the number of mem.
Definition: lsq.hh:609
gem5::minor::LSQ::canSendToMemorySystem
bool canSendToMemorySystem()
Can a request be sent to the memory system.
Definition: lsq.cc:1292
gem5::minor::LSQ::LSQRequest::LSQRequest
LSQRequest(LSQ &port_, MinorDynInstPtr inst_, bool isLoad_, RegIndex zero_reg, PacketDataPtr data_=NULL, uint64_t *res_=NULL)
Definition: lsq.cc:61
gem5::minor::LSQ::SplitDataRequest::~SplitDataRequest
~SplitDataRequest()
Definition: lsq.cc:412
gem5::minor::LSQ::SplitDataRequest::stepToNextPacket
void stepToNextPacket()
Step on numIssuedFragments.
Definition: lsq.cc:619
gem5::minor::LSQ::LSQRequest::StoreBufferNeedsRetry
@ StoreBufferNeedsRetry
Definition: lsq.hh:189
gem5::minor::LSQ::SingleDataRequest::getHeadPacket
PacketPtr getHeadPacket()
Get the head packet as counted by numIssuedFragments.
Definition: lsq.hh:370
gem5::EventFunctionWrapper
Definition: eventq.hh:1115
gem5::minor::LSQ::inMemorySystemLimit
const unsigned int inMemorySystemLimit
Maximum number of in-flight accesses issued to the memory system.
Definition: lsq.hh:554
gem5::BaseMMU::Translation
Definition: mmu.hh:55
gem5::minor::LSQ::LSQRequest::startAddrTranslation
virtual void startAddrTranslation()=0
Start the address translation process for this request.
gem5::minor::LSQ::StoreBuffer::canInsert
bool canInsert() const
Can a new request be inserted into the queue?
Definition: lsq.cc:723
gem5::minor::LSQ::dcachePort
DcachePort dcachePort
Definition: lsq.hh:123
gem5::minor::LSQ::LSQRequest::skipped
bool skipped
Was skipped.
Definition: lsq.hh:165
gem5::minor::LSQ::LSQRequest::state
LSQRequestState state
Definition: lsq.hh:196
gem5::X86ISA::os
Bitfield< 17 > os
Definition: misc.hh:809
gem5::minor::LSQ::accessesInFlight
bool accessesInFlight() const
Are there any accesses other than normal cached loads in the memory system or having received respons...
Definition: lsq.hh:696
gem5::minor::LSQ::numAccessesIssuedToMemory
unsigned int numAccessesIssuedToMemory
The number of accesses which have been issued to the memory system but have not been committed/discar...
Definition: lsq.hh:621
gem5::minor::LSQ::LSQRequest::completeDisabledMemAccess
void completeDisabledMemAccess()
Definition: lsq.cc:100
gem5::minor::LSQ::recvTimingSnoopReq
void recvTimingSnoopReq(PacketPtr pkt)
Definition: lsq.cc:1759
gem5::minor::LSQ::operator<<
friend std::ostream & operator<<(std::ostream &os, MemoryState state)
Print MemoryState values as shown in the enum definition.
Definition: lsq.cc:1742
std::deque< LSQRequestPtr >
gem5::minor::Execute
Execute stage.
Definition: execute.hh:68
gem5::minor::LSQ::LSQRequest::isTranslationDelayed
bool isTranslationDelayed
Address translation is delayed due to table walk.
Definition: lsq.hh:172
gem5::minor::LSQ::StoreBuffer::minorTrace
void minorTrace() const
Report queue contents for MinorTrace.
Definition: lsq.cc:933
gem5::minor::LSQ::SplitDataRequest::numRetiredFragments
unsigned int numRetiredFragments
Number of fragments retired back to this request.
Definition: lsq.hh:417
gem5::minor::LSQ::DcachePort::recvFunctionalSnoop
void recvFunctionalSnoop(PacketPtr pkt) override
Receive a functional snoop request packet from the peer.
Definition: lsq.hh:120
gem5::minor::LSQ::SingleDataRequest
SingleDataRequest is used for requests that don't fragment.
Definition: lsq.hh:351
gem5::minor::LSQ::LSQRequest::port
LSQ & port
Owning port.
Definition: lsq.hh:135
gem5::minor::LSQ::MemoryRunning
@ MemoryRunning
Definition: lsq.hh:81
gem5::minor::NoBubbleTraits
...
Definition: buffers.hh:122
gem5::minor::LSQ::LSQRequest::isBarrier
virtual bool isBarrier()
Is this a request a barrier?
Definition: lsq.cc:161
gem5::minor::LSQ::transfers
LSQQueue transfers
Once issued to memory (or, for stores, just had their state changed to StoreToStoreBuffer) LSQRequest...
Definition: lsq.hh:589
gem5::minor::LSQ::LSQRequest::NotIssued
@ NotIssued
Definition: lsq.hh:176
gem5::minor::LSQ::SplitDataRequest
Definition: lsq.hh:395
gem5::minor::LSQ::retryRequest
LSQRequestPtr retryRequest
The request (from either requests or the store buffer) which is currently waiting have its memory acc...
Definition: lsq.hh:625
gem5::InstSeqNum
uint64_t InstSeqNum
Definition: inst_seq.hh:40
buffers.hh
gem5::minor::LSQ::LSQRequest::zeroReg
const RegIndex zeroReg
Definition: lsq.hh:137
gem5::minor::LSQ::SplitDataRequest::startAddrTranslation
void startAddrTranslation()
Start a loop of do { sendNextFragmentToTranslation ; translateTiming ; finish } while (numTranslatedF...
Definition: lsq.cc:586
gem5::minor::LSQ::numStoresInTransfers
unsigned int numStoresInTransfers
The number of stores in the transfers queue.
Definition: lsq.hh:616
gem5::minor::LSQ::StoreBuffer::deleteRequest
void deleteRequest(LSQRequestPtr request)
Delete the given request and free the slot it occupied.
Definition: lsq.cc:730
gem5::minor::LSQ::SingleDataRequest::retireResponse
void retireResponse(PacketPtr packet_)
Keep the given packet as the response packet LSQRequest::packet.
Definition: lsq.cc:328
gem5::minor::LSQ::recvTimingResp
bool recvTimingResp(PacketPtr pkt)
Memory interface.
Definition: lsq.cc:1299
gem5::minor::LSQ::cpu
MinorCPU & cpu
My owner(s)
Definition: lsq.hh:72
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
trace.hh
gem5::minor::LSQ::pushRequest
Fault pushRequest(MinorDynInstPtr inst, bool isLoad, uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res, AtomicOpFunctorPtr amo_op, const std::vector< bool > &byte_enable=std::vector< bool >())
Single interface for readMem/writeMem/amoMem to issue requests into the LSQ.
Definition: lsq.cc:1588
gem5::AtomicOpFunctorPtr
std::unique_ptr< AtomicOpFunctor > AtomicOpFunctorPtr
Definition: amo.hh:242
gem5::minor::LSQ::SplitDataRequest::numTranslatedFragments
unsigned int numTranslatedFragments
Number of fragments that have completed address translation, (numTranslatedFragments + numInTranslati...
Definition: lsq.hh:411
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::minor::LSQ::LSQRequest::reportData
void reportData(std::ostream &os) const
MinorTrace report interface.
Definition: lsq.cc:189
gem5::minor::LSQ::LSQRequest::hasPacketsInMemSystem
virtual bool hasPacketsInMemSystem()=0
True if this request has any issued packets in the memory system and so can't be interrupted until it...
gem5::minor::LSQ::LSQRequest::isComplete
bool isComplete() const
Has this request been completed.
Definition: lsq.cc:181
gem5::minor::LSQ::sendStoreToStoreBuffer
void sendStoreToStoreBuffer(LSQRequestPtr request)
A store has been committed, please move it to the store buffer.
Definition: lsq.cc:1548
gem5::minor::LSQ::findResponse
LSQRequestPtr findResponse(MinorDynInstPtr inst)
Returns a response if it's at the head of the transfers queue and it's either complete or can be sent...
Definition: lsq.cc:1491
gem5::minor::LSQ::canPushIntoStoreBuffer
bool canPushIntoStoreBuffer() const
Must check this before trying to insert into the store buffer.
Definition: lsq.hh:688
gem5::minor::LSQ::FullAddrRangeCoverage
@ FullAddrRangeCoverage
Definition: lsq.hh:93
gem5::minor::LSQ::SingleDataRequest::packetInFlight
bool packetInFlight
Has my only packet been sent to the memory system but has not yet been responded to.
Definition: lsq.hh:360
gem5::minor::LSQ::StoreBuffer::lsq
LSQ & lsq
My owner.
Definition: lsq.hh:481
gem5::minor::LSQ::SpecialDataRequest::startAddrTranslation
void startAddrTranslation()
Send single translation request.
Definition: lsq.hh:300
gem5::minor::LSQ::StoreBuffer::numSlots
const unsigned int numSlots
Number of slots, this is a bound on the size of slots.
Definition: lsq.hh:484
gem5::minor::LSQ::LSQRequest::StoreInStoreBuffer
@ StoreInStoreBuffer
Definition: lsq.hh:185
gem5::ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:242
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:73
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::minor::LSQ::DcachePort::lsq
LSQ & lsq
My owner.
Definition: lsq.hh:102
gem5::minor::LSQ::SingleDataRequest::SingleDataRequest
SingleDataRequest(LSQ &port_, MinorDynInstPtr inst_, bool isLoad_, PacketDataPtr data_=NULL, uint64_t *res_=NULL)
Definition: lsq.hh:387

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