gem5  v21.1.0.2
Classes | Namespaces
gpu_command_processor.hh File Reference
#include <cstdint>
#include <functional>
#include "base/logging.hh"
#include "base/trace.hh"
#include "base/types.hh"
#include "debug/GPUCommandProc.hh"
#include "dev/dma_virt_device.hh"
#include "dev/hsa/hsa_packet_processor.hh"
#include "dev/hsa/hsa_signal.hh"
#include "gpu-compute/dispatcher.hh"
#include "gpu-compute/gpu_compute_driver.hh"
#include "gpu-compute/hsa_queue_entry.hh"
#include "params/GPUCommandProcessor.hh"

Go to the source code of this file.

Classes

class  gem5::GPUCommandProcessor
 

Namespaces

 gem5
 Reference material can be found at the JEDEC website: UFS standard http://www.jedec.org/standards-documents/results/jesd220 UFS HCI specification http://www.jedec.org/standards-documents/results/jesd223.
 

Detailed Description

The GPUCommandProcessor (CP) is responsible for accepting commands, in the form of HSA AQL packets, from the HSA packet processor (HSAPP). The CP works with several components, including the HSAPP and the dispatcher. When the HSAPP sends a ready task to the CP, it will perform the necessary operations to extract relevant data structures from memory, such as the AQL queue descriptor and AQL packet, and initializes register state for the task's wavefronts.

Definition in file gpu_command_processor.hh.


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