gem5 v24.0.0.0
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dispatcher.hh
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1/*
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31
41#ifndef __GPU_COMPUTE_DISPATCHER_HH__
42#define __GPU_COMPUTE_DISPATCHER_HH__
43
44#include <queue>
45#include <unordered_map>
46#include <vector>
47
48#include "base/statistics.hh"
49#include "base/stats/group.hh"
50#include "dev/hsa/hsa_packet.hh"
51#include "params/GPUDispatcher.hh"
52#include "sim/sim_object.hh"
53
54namespace gem5
55{
56
57class GPUCommandProcessor;
58class HSAQueueEntry;
59class Shader;
60class Wavefront;
61
63{
64 public:
65 typedef GPUDispatcherParams Params;
66
67 GPUDispatcher(const Params &p);
69
70 void serialize(CheckpointOut &cp) const override;
71 void unserialize(CheckpointIn &cp) override;
72 void setCommandProcessor(GPUCommandProcessor *gpu_cmd_proc);
73 void setShader(Shader *new_shader);
74 void exec();
76 void updateInvCounter(int kern_id, int val=-1);
77 bool updateWbCounter(int kern_id, int val=-1);
78 int getOutstandingWbs(int kern_id);
79 void notifyWgCompl(Wavefront *wf);
80 void scheduleDispatch();
81 void dispatch(HSAQueueEntry *task);
82 HSAQueueEntry* hsaTask(int disp_id);
83
84 private:
88 std::unordered_map<int, HSAQueueEntry*> hsaQueueEntries;
89 // list of kernel_ids to launch
90 std::queue<int> execIds;
91 // list of kernel_ids that have finished
92 std::queue<int> doneIds;
93 // is there a kernel in execution?
95 // Enable exiting sim loop after each kernel completion
97
98 protected:
106};
107
108} // namespace gem5
109
110#endif // __GPU_COMPUTE_DISPATCHER_HH__
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition dispatcher.cc:84
void dispatch(HSAQueueEntry *task)
After all relevant HSA data structures have been traversed/extracted from memory by the CP,...
void updateInvCounter(int kern_id, int val=-1)
update the counter of oustanding inv requests for the kernel kern_id: kernel id val: +1/-1,...
EventFunctionWrapper tickEvent
Definition dispatcher.hh:87
bool isReachingKernelEnd(Wavefront *wf)
GPUDispatcherParams Params
Definition dispatcher.hh:65
int getOutstandingWbs(int kern_id)
get kernel's outstanding cache writeback requests
std::unordered_map< int, HSAQueueEntry * > hsaQueueEntries
Definition dispatcher.hh:88
gem5::GPUDispatcher::GPUDispatcherStats stats
bool updateWbCounter(int kern_id, int val=-1)
update the counter of oustanding wb requests for the kernel kern_id: kernel id val: +1/-1,...
HSAQueueEntry * hsaTask(int disp_id)
Definition dispatcher.cc:65
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition dispatcher.cc:95
GPUCommandProcessor * gpuCmdProc
Definition dispatcher.hh:86
std::queue< int > execIds
Definition dispatcher.hh:90
GPUDispatcher(const Params &p)
Definition dispatcher.cc:50
void notifyWgCompl(Wavefront *wf)
When an end program instruction detects that the last WF in a WG has completed it will call this meth...
void setCommandProcessor(GPUCommandProcessor *gpu_cmd_proc)
Definition dispatcher.cc:72
void setShader(Shader *new_shader)
Definition dispatcher.cc:78
std::queue< int > doneIds
Definition dispatcher.hh:92
Abstract superclass for simulation objects.
Statistics container.
Definition group.hh:93
This is a simple scalar statistic, like a counter.
Bitfield< 0 > p
Bitfield< 63 > val
Definition misc.hh:804
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
std::ostream CheckpointOut
Definition serialize.hh:66
Declaration of Statistics objects.
GPUDispatcherStats(statistics::Group *parent)

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