gem5  v21.1.0.2
i8259.hh
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are
7  * met: redistributions of source code must retain the above copyright
8  * notice, this list of conditions and the following disclaimer;
9  * redistributions in binary form must reproduce the above copyright
10  * notice, this list of conditions and the following disclaimer in the
11  * documentation and/or other materials provided with the distribution;
12  * neither the name of the copyright holders nor the names of its
13  * contributors may be used to endorse or promote products derived from
14  * this software without specific prior written permission.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27  */
28 
29 #ifndef __DEV_X86_I8259_HH__
30 #define __DEV_X86_I8259_HH__
31 
32 #include "dev/intpin.hh"
33 #include "dev/io_device.hh"
34 #include "enums/X86I8259CascadeMode.hh"
35 #include "params/I8259.hh"
36 
37 namespace gem5
38 {
39 
40 namespace X86ISA
41 {
42 
43 class I8259 : public BasicPioDevice
44 {
45  protected:
46  static const int NumLines = 8;
48 
49  void init() override;
50 
54  enums::X86I8259CascadeMode mode;
56 
57  // Interrupt Request Register
58  uint8_t IRR;
59  // In Service Register
60  uint8_t ISR;
61  // Interrupt Mask Register
62  uint8_t IMR;
63 
64  // The higher order bits of the vector to return
65  uint8_t vectorOffset;
66 
68  // A bit vector of lines with responders attached, or the
69  // responder id, depending
70  // on if this is a requestor or responder PIC.
71  uint8_t cascadeBits;
72 
74  bool readIRR;
75 
76  // State machine information for reading in initialization control words.
77  bool expectICW4;
79 
80  // Whether or not the PIC is in auto EOI mode.
81  bool autoEOI;
82 
83  void requestInterrupt(int line);
84  void handleEOI(int line);
85 
86  public:
87  using Params = I8259Params;
88 
89  I8259(const Params &p);
90 
91  Port &
92  getPort(const std::string &if_name, PortID idx=InvalidPortID) override
93  {
94  if (if_name == "inputs")
95  return *inputs.at(idx);
96  else if (if_name == "output")
97  return *output.at(idx);
98  else
99  return BasicPioDevice::getPort(if_name, idx);
100  }
101 
102  Tick read(PacketPtr pkt) override;
103  Tick write(PacketPtr pkt) override;
104 
105  void
107  {
108  IMR = 0xFF;
109  }
110 
111  void
113  {
114  IMR = 0x00;
115  }
116 
117  void signalInterrupt(int line);
118  void raiseInterruptPin(int number);
119  void lowerInterruptPin(int number);
120  int getVector();
121 
122  void serialize(CheckpointOut &cp) const override;
123  void unserialize(CheckpointIn &cp) override;
124 };
125 
126 } // namespace X86ISA
127 } // namespace gem5
128 
129 #endif //__DEV_X86_I8259_HH__
gem5::PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:252
io_device.hh
gem5::X86ISA::I8259::raiseInterruptPin
void raiseInterruptPin(int number)
Definition: i8259.cc:289
gem5::X86ISA::I8259::ISR
uint8_t ISR
Definition: i8259.hh:60
gem5::X86ISA::I8259::readIRR
bool readIRR
Definition: i8259.hh:74
gem5::X86ISA::I8259::latency
Tick latency
Definition: i8259.hh:51
gem5::X86ISA::I8259::IMR
uint8_t IMR
Definition: i8259.hh:62
gem5::X86ISA::I8259::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: i8259.cc:336
gem5::X86ISA::I8259::initControlWord
int initControlWord
Definition: i8259.hh:78
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::X86ISA::I8259::init
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: i8259.cc:66
gem5::X86ISA::I8259::autoEOI
bool autoEOI
Definition: i8259.hh:81
gem5::X86ISA::I8259::IRR
uint8_t IRR
Definition: i8259.hh:58
std::vector
STL vector class.
Definition: stl.hh:37
gem5::X86ISA::I8259::cascadeMode
bool cascadeMode
Definition: i8259.hh:67
gem5::X86ISA::I8259::mode
enums::X86I8259CascadeMode mode
Definition: i8259.hh:54
gem5::X86ISA::I8259::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: i8259.cc:354
gem5::InvalidPortID
const PortID InvalidPortID
Definition: types.hh:253
gem5::X86ISA::I8259::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: i8259.hh:92
gem5::X86ISA::I8259::inputs
std::vector< IntSinkPin< I8259 > * > inputs
Definition: i8259.hh:53
gem5::X86ISA::I8259::maskAll
void maskAll()
Definition: i8259.hh:106
gem5::X86ISA::I8259::getVector
int getVector()
Definition: i8259.cc:311
gem5::PioDevice::Params
PioDeviceParams Params
Definition: io_device.hh:134
gem5::X86ISA::I8259::read
Tick read(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: i8259.cc:75
gem5::X86ISA::I8259::slave
I8259 * slave
Definition: i8259.hh:55
gem5::X86ISA::I8259::NumLines
static const int NumLines
Definition: i8259.hh:46
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::X86ISA::I8259::output
std::vector< IntSourcePin< I8259 > * > output
Definition: i8259.hh:52
gem5::X86ISA::I8259::expectICW4
bool expectICW4
Definition: i8259.hh:77
gem5::X86ISA::I8259::write
Tick write(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: i8259.cc:99
gem5::X86ISA::I8259::lowerInterruptPin
void lowerInterruptPin(int number)
Definition: i8259.cc:301
gem5::X86ISA::I8259::I8259
I8259(const Params &p)
Definition: i8259.cc:41
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
gem5::X86ISA::I8259::pinStates
bool pinStates[NumLines]
Definition: i8259.hh:47
gem5::X86ISA::I8259::vectorOffset
uint8_t vectorOffset
Definition: i8259.hh:65
gem5::X86ISA::I8259
Definition: i8259.hh:43
gem5::X86ISA::p
Bitfield< 0 > p
Definition: pagetable.hh:151
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::X86ISA::I8259::edgeTriggered
bool edgeTriggered
Definition: i8259.hh:73
intpin.hh
gem5::X86ISA::I8259::unmaskAll
void unmaskAll()
Definition: i8259.hh:112
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::BasicPioDevice
Definition: io_device.hh:147
gem5::X86ISA::I8259::signalInterrupt
void signalInterrupt(int line)
Definition: i8259.cc:274
gem5::X86ISA::I8259::cascadeBits
uint8_t cascadeBits
Definition: i8259.hh:71
gem5::X86ISA::I8259::handleEOI
void handleEOI(int line)
Definition: i8259.cc:246
gem5::X86ISA::I8259::requestInterrupt
void requestInterrupt(int line)
Definition: i8259.cc:256
gem5::PioDevice::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: io_device.cc:67

Generated on Tue Sep 21 2021 12:25:23 for gem5 by doxygen 1.8.17