gem5  v21.1.0.2
i8259.cc
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1 /*
2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are
7  * met: redistributions of source code must retain the above copyright
8  * notice, this list of conditions and the following disclaimer;
9  * redistributions in binary form must reproduce the above copyright
10  * notice, this list of conditions and the following disclaimer in the
11  * documentation and/or other materials provided with the distribution;
12  * neither the name of the copyright holders nor the names of its
13  * contributors may be used to endorse or promote products derived from
14  * this software without specific prior written permission.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27  */
28 
29 #include "dev/x86/i8259.hh"
30 
31 #include "base/bitfield.hh"
32 #include "base/trace.hh"
33 #include "debug/I8259.hh"
34 #include "dev/x86/i82094aa.hh"
35 #include "mem/packet.hh"
36 #include "mem/packet_access.hh"
37 
38 namespace gem5
39 {
40 
42  : BasicPioDevice(p, 2),
43  latency(p.pio_latency),
44  mode(p.mode), slave(p.slave),
45  IRR(0), ISR(0), IMR(0),
46  readIRR(true), initControlWord(0), autoEOI(false)
47 {
48  for (int i = 0; i < p.port_output_connection_count; i++) {
49  output.push_back(new IntSourcePin<I8259>(
50  csprintf("%s.output[%d]", name(), i), i, this));
51  }
52 
53  int in_count = p.port_inputs_connection_count;
54  panic_if(in_count >= NumLines,
55  "I8259 only supports 8 inputs, but there are %d.", in_count);
56  for (int i = 0; i < in_count; i++) {
57  inputs.push_back(new IntSinkPin<I8259>(
58  csprintf("%s.inputs[%d]", name(), i), i, this));
59  }
60 
61  for (bool &state: pinStates)
62  state = false;
63 }
64 
65 void
67 {
69 
70  for (auto *input: inputs)
71  pinStates[input->getId()] = input->state();
72 }
73 
74 Tick
76 {
77  assert(pkt->getSize() == 1);
78  switch(pkt->getAddr() - pioAddr)
79  {
80  case 0x0:
81  if (readIRR) {
82  DPRINTF(I8259, "Reading IRR as %#x.\n", IRR);
83  pkt->setLE(IRR);
84  } else {
85  DPRINTF(I8259, "Reading ISR as %#x.\n", ISR);
86  pkt->setLE(ISR);
87  }
88  break;
89  case 0x1:
90  DPRINTF(I8259, "Reading IMR as %#x.\n", IMR);
91  pkt->setLE(IMR);
92  break;
93  }
94  pkt->makeAtomicResponse();
95  return latency;
96 }
97 
98 Tick
100 {
101  assert(pkt->getSize() == 1);
102  uint8_t val = pkt->getLE<uint8_t>();
103  switch (pkt->getAddr() - pioAddr) {
104  case 0x0:
105  if (bits(val, 4)) {
106  DPRINTF(I8259, "Received initialization command word 1.\n");
107  IMR = 0;
108  edgeTriggered = bits(val, 3);
109  DPRINTF(I8259, "%s triggered mode.\n",
110  edgeTriggered ? "Edge" : "Level");
111  cascadeMode = !bits(val, 1);
112  DPRINTF(I8259, "%s mode.\n",
113  cascadeMode ? "Cascade" : "Single");
114  expectICW4 = bits(val, 0);
115  if (!expectICW4) {
116  autoEOI = false;
117  }
118  initControlWord = 1;
119  DPRINTF(I8259, "Expecting %d more bytes.\n", expectICW4 ? 3 : 2);
120  } else if (bits(val, 4, 3) == 0) {
121  DPRINTF(I8259, "Received operation command word 2.\n");
122  switch (bits(val, 7, 5)) {
123  case 0x0:
124  DPRINTF(I8259,
125  "Subcommand: Rotate in auto-EOI mode (clear).\n");
126  break;
127  case 0x1:
128  {
129  int line = findMsbSet(ISR);
130  DPRINTF(I8259, "Subcommand: Nonspecific EOI on line %d.\n",
131  line);
132  handleEOI(line);
133  }
134  break;
135  case 0x2:
136  DPRINTF(I8259, "Subcommand: No operation.\n");
137  break;
138  case 0x3:
139  {
140  int line = bits(val, 2, 0);
141  DPRINTF(I8259, "Subcommand: Specific EIO on line %d.\n",
142  line);
143  handleEOI(line);
144  }
145  break;
146  case 0x4:
147  DPRINTF(I8259, "Subcommand: Rotate in auto-EOI mode (set).\n");
148  break;
149  case 0x5:
150  DPRINTF(I8259, "Subcommand: Rotate on nonspecific EOI.\n");
151  break;
152  case 0x6:
153  DPRINTF(I8259, "Subcommand: Set priority command.\n");
154  DPRINTF(I8259, "Lowest: IRQ%d Highest IRQ%d.\n",
155  bits(val, 2, 0), (bits(val, 2, 0) + 1) % 8);
156  break;
157  case 0x7:
158  DPRINTF(I8259, "Subcommand: Rotate on specific EOI.\n");
159  DPRINTF(I8259, "Lowest: IRQ%d Highest IRQ%d.\n",
160  bits(val, 2, 0), (bits(val, 2, 0) + 1) % 8);
161  break;
162  }
163  } else if (bits(val, 4, 3) == 1) {
164  DPRINTF(I8259, "Received operation command word 3.\n");
165  if (bits(val, 7)) {
166  DPRINTF(I8259, "%s special mask mode.\n",
167  bits(val, 6) ? "Set" : "Clear");
168  }
169  if (bits(val, 1)) {
170  readIRR = bits(val, 0);
171  DPRINTF(I8259, "Read %s.\n", readIRR ? "IRR" : "ISR");
172  }
173  }
174  break;
175  case 0x1:
176  switch (initControlWord) {
177  case 0x0:
178  DPRINTF(I8259, "Received operation command word 1.\n");
179  DPRINTF(I8259, "Wrote IMR value %#x.\n", val);
180  IMR = val;
181  break;
182  case 0x1:
183  DPRINTF(I8259, "Received initialization command word 2.\n");
184  vectorOffset = val & ~mask(3);
185  DPRINTF(I8259, "Responsible for vectors %#x-%#x.\n",
186  vectorOffset, vectorOffset | mask(3));
187  if (cascadeMode) {
188  initControlWord++;
189  } else {
190  cascadeBits = 0;
191  initControlWord = 0;
192  }
193  break;
194  case 0x2:
195  DPRINTF(I8259, "Received initialization command word 3.\n");
196  if (mode == enums::I8259Master) {
197  DPRINTF(I8259, "Responders attached to "
198  "IRQs:%s%s%s%s%s%s%s%s\n",
199  bits(val, 0) ? " 0" : "",
200  bits(val, 1) ? " 1" : "",
201  bits(val, 2) ? " 2" : "",
202  bits(val, 3) ? " 3" : "",
203  bits(val, 4) ? " 4" : "",
204  bits(val, 5) ? " 5" : "",
205  bits(val, 6) ? " 6" : "",
206  bits(val, 7) ? " 7" : "");
207  cascadeBits = val;
208  } else {
209  DPRINTF(I8259, "Responder ID is %d.\n", val & mask(3));
210  cascadeBits = val & mask(3);
211  }
212  if (expectICW4)
213  initControlWord++;
214  else
215  initControlWord = 0;
216  break;
217  case 0x3:
218  DPRINTF(I8259, "Received initialization command word 4.\n");
219  if (bits(val, 4)) {
220  DPRINTF(I8259, "Special fully nested mode.\n");
221  } else {
222  DPRINTF(I8259, "Not special fully nested mode.\n");
223  }
224  if (bits(val, 3) == 0) {
225  DPRINTF(I8259, "Nonbuffered.\n");
226  } else if (bits(val, 2) == 0) {
227  DPRINTF(I8259, "Buffered.\n");
228  } else {
229  DPRINTF(I8259, "Unrecognized buffer mode.\n");
230  }
231  autoEOI = bits(val, 1);
232  DPRINTF(I8259, "%s End Of Interrupt.\n",
233  autoEOI ? "Automatic" : "Normal");
234 
235  DPRINTF(I8259, "%s mode.\n", bits(val, 0) ? "80x86" : "MCX-80/85");
236  initControlWord = 0;
237  break;
238  }
239  break;
240  }
241  pkt->makeAtomicResponse();
242  return latency;
243 }
244 
245 void
247 {
248  ISR &= ~(1 << line);
249  // There may be an interrupt that was waiting which can
250  // now be sent.
251  if (IRR)
252  requestInterrupt(findMsbSet(IRR));
253 }
254 
255 void
257 {
258  if (bits(ISR, 7, line) == 0) {
259  if (!output.empty()) {
260  DPRINTF(I8259, "Propogating interrupt.\n");
261  for (auto *wire: output) {
262  wire->raise();
263  //XXX This is a hack.
264  wire->lower();
265  }
266  } else {
267  warn("Received interrupt but didn't have "
268  "anyone to tell about it.\n");
269  }
270  }
271 }
272 
273 void
275 {
276  DPRINTF(I8259, "Interrupt requested for line %d.\n", line);
277  if (line >= NumLines)
278  fatal("Line number %d doesn't exist. The max is %d.\n",
279  line, NumLines - 1);
280  if (bits(IMR, line)) {
281  DPRINTF(I8259, "Interrupt %d was masked.\n", line);
282  } else {
283  IRR |= 1 << line;
284  requestInterrupt(line);
285  }
286 }
287 
288 void
290 {
291  DPRINTF(I8259, "Interrupt signal raised for pin %d.\n", number);
292  if (number >= NumLines)
293  fatal("Line number %d doesn't exist. The max is %d.\n",
294  number, NumLines - 1);
295  if (!pinStates[number])
296  signalInterrupt(number);
297  pinStates[number] = true;
298 }
299 
300 void
302 {
303  DPRINTF(I8259, "Interrupt signal lowered for pin %d.\n", number);
304  if (number >= NumLines)
305  fatal("Line number %d doesn't exist. The max is %d.\n",
306  number, NumLines - 1);
307  pinStates[number] = false;
308 }
309 
310 int
312 {
313  /*
314  * This code only handles one responder. Since that's how the PC platform
315  * always uses the 8259 PIC, there shouldn't be any need for more. If
316  * there -is- a need for more for some reason, "responder" can become a
317  * vector of responders.
318  */
319  int line = findMsbSet(IRR);
320  IRR &= ~(1 << line);
321  DPRINTF(I8259, "Interrupt %d was accepted.\n", line);
322  if (autoEOI) {
323  handleEOI(line);
324  } else {
325  ISR |= 1 << line;
326  }
327  if (slave && bits(cascadeBits, line)) {
328  DPRINTF(I8259, "Interrupt was from responder who will "
329  "provide the vector.\n");
330  return slave->getVector();
331  }
332  return line | vectorOffset;
333 }
334 
335 void
337 {
338  SERIALIZE_ARRAY(pinStates, NumLines);
340  SERIALIZE_SCALAR(IRR);
343  SERIALIZE_SCALAR(vectorOffset);
344  SERIALIZE_SCALAR(cascadeMode);
345  SERIALIZE_SCALAR(cascadeBits);
346  SERIALIZE_SCALAR(edgeTriggered);
347  SERIALIZE_SCALAR(readIRR);
348  SERIALIZE_SCALAR(expectICW4);
349  SERIALIZE_SCALAR(initControlWord);
350  SERIALIZE_SCALAR(autoEOI);
351 }
352 
353 void
355 {
356  UNSERIALIZE_ARRAY(pinStates, NumLines);
358  UNSERIALIZE_SCALAR(IRR);
361  UNSERIALIZE_SCALAR(vectorOffset);
362  UNSERIALIZE_SCALAR(cascadeMode);
363  UNSERIALIZE_SCALAR(cascadeBits);
364  UNSERIALIZE_SCALAR(edgeTriggered);
365  UNSERIALIZE_SCALAR(readIRR);
366  UNSERIALIZE_SCALAR(expectICW4);
367  UNSERIALIZE_SCALAR(initControlWord);
368  UNSERIALIZE_SCALAR(autoEOI);
369 }
370 
371 } // namespace gem5
fatal
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:189
gem5::X86ISA::mask
mask
Definition: misc.hh:802
warn
#define warn(...)
Definition: logging.hh:245
gem5::X86ISA::I8259::raiseInterruptPin
void raiseInterruptPin(int number)
Definition: i8259.cc:289
UNSERIALIZE_SCALAR
#define UNSERIALIZE_SCALAR(scalar)
Definition: serialize.hh:575
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@ IMR
Definition: ns_gige_reg.h:48
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static void output(const char *filename)
Definition: debug.cc:66
gem5::X86ISA::I8259::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: i8259.cc:336
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::X86ISA::I8259::init
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: i8259.cc:66
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
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std::string csprintf(const char *format, const Args &...args)
Definition: cprintf.hh:161
gem5::Packet::makeAtomicResponse
void makeAtomicResponse()
Definition: packet.hh:1043
gem5::X86ISA::I8259::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: i8259.cc:354
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::X86ISA::I8259::inputs
std::vector< IntSinkPin< I8259 > * > inputs
Definition: i8259.hh:53
gem5::X86ISA::I8259::getVector
int getVector()
Definition: i8259.cc:311
packet.hh
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void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: io_device.cc:59
gem5::PioDevice::Params
PioDeviceParams Params
Definition: io_device.hh:134
SERIALIZE_ENUM
#define SERIALIZE_ENUM(scalar)
Definition: serialize.hh:591
gem5::X86ISA::I8259::read
Tick read(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: i8259.cc:75
bitfield.hh
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virtual std::string name() const
Definition: named.hh:47
gem5::X86ISA::I8259::NumLines
static const int NumLines
Definition: i8259.hh:46
i82094aa.hh
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::X86ISA::I8259::output
std::vector< IntSourcePin< I8259 > * > output
Definition: i8259.hh:52
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
SERIALIZE_ARRAY
#define SERIALIZE_ARRAY(member, size)
Definition: serialize.hh:610
gem5::ISR
@ ISR
Definition: ns_gige_reg.h:47
gem5::X86ISA::I8259::write
Tick write(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: i8259.cc:99
SERIALIZE_SCALAR
#define SERIALIZE_SCALAR(scalar)
Definition: serialize.hh:568
packet_access.hh
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:203
gem5::X86ISA::I8259::lowerInterruptPin
void lowerInterruptPin(int number)
Definition: i8259.cc:301
gem5::X86ISA::I8259::I8259
I8259(const Params &p)
Definition: i8259.cc:41
UNSERIALIZE_ARRAY
#define UNSERIALIZE_ARRAY(member, size)
Definition: serialize.hh:618
gem5::IntSinkPin
Definition: intpin.hh:78
gem5::X86ISA::I8259::pinStates
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Definition: i8259.hh:47
i8259.hh
gem5::X86ISA::I8259
Definition: i8259.hh:43
gem5::Packet::getLE
T getLE() const
Get the data in the packet byte swapped from little endian to host endian.
Definition: packet_access.hh:78
gem5::X86ISA::p
Bitfield< 0 > p
Definition: pagetable.hh:151
gem5::findMsbSet
constexpr int findMsbSet(uint64_t val)
Returns the bit position of the MSB that is set in the input.
Definition: bitfield.hh:263
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
UNSERIALIZE_ENUM
#define UNSERIALIZE_ENUM(scalar)
Definition: serialize.hh:598
trace.hh
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Definition: intpin.hh:112
gem5::Packet::setLE
void setLE(T v)
Set the value in the data pointer to v as little endian.
Definition: packet_access.hh:108
gem5::Packet::getAddr
Addr getAddr() const
Definition: packet.hh:781
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Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::BasicPioDevice
Definition: io_device.hh:147
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void signalInterrupt(int line)
Definition: i8259.cc:274
gem5::X86ISA::I8259::handleEOI
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Definition: i8259.cc:246
gem5::X86ISA::I8259::requestInterrupt
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Definition: i8259.cc:256
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unsigned getSize() const
Definition: packet.hh:791
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Bitfield< 4, 0 > mode
Definition: misc_types.hh:73

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