gem5 v24.0.0.0
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mat.hh
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1/*
2 * Copyright (c) 2022 Arm Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
38#ifndef __ARCH_ARM_REGS_MAT_HH__
39#define __ARCH_ARM_REGS_MAT_HH__
40
41#include "arch/arm/types.hh"
42#include "arch/arm/matrix.hh"
43#include "cpu/reg_class.hh"
44#include "debug/MatRegs.hh"
45
46namespace gem5
47{
48
49namespace ArmISA
50{
51
52/*
53 * We do the same as is done for vector registers when creating the
54 * matricies. One of the things to note is that this allocates the
55 * largest architecturally possible matrix - this is a bit inefficient
56 * from a memory point of view, but at this point we do not know which
57 * vector length will be chosen (and this can potentially vary during
58 * runtime).
59 */
62
63template<typename ElemType>
64using MatTile = gem5::Tile<ElemType,
66
67template<typename ElemType>
70 true>;
71
72template<typename ElemType>
75 true>;
76
77template<typename ElemType>
80 false>;
81
82template<typename ElemType>
83using MatCol = gem5::VerticalSlice<ElemType,
85 false>;
86
87// SME ZA tile, i.e. matrix
88const int NumMatrixRegs = 1;
89
91
92inline constexpr RegClass matRegClass =
94 ops(matRegClassOps).
95 regType<MatRegContainer>();
96
97/*
98 * Helpers for providing access to the different views of a matrix
99 * register. Intended to be called from the instruction implementations
100 * themselves.
101 */
102template<typename ElemType>
104getTile(MatRegContainer &reg, uint8_t tile_idx)
105{
106 return reg.asTile<ElemType>(tile_idx);
107}
108template<typename ElemType>
110getTileHSlice(MatRegContainer &reg, uint8_t tile_idx, uint8_t row_idx)
111{
112 return reg.asTile<ElemType>(tile_idx).asHSlice(row_idx);
113}
114template<typename ElemType>
116getTileVSlice(MatRegContainer &reg, uint8_t tile_idx, uint8_t col_idx)
117{
118 return reg.asTile<ElemType>(tile_idx).asVSlice(col_idx);
119}
120template<typename ElemType>
122getHSlice(MatRegContainer &reg, uint8_t row_idx)
123{
124 return reg.asHSlice<ElemType>(row_idx);
125}
126template<typename ElemType>
128getVSlice(MatRegContainer &reg, uint8_t col_idx)
129{
130 return reg.asVSlice<ElemType>(col_idx);
131}
132
133} // namespace ArmISA
134} // namespace gem5
135
136#endif
Provides a view of a horizontal slice of either a MatStore or a Tile.
Definition matrix.hh:152
Backing store for matrices.
Definition matrix.hh:381
Provides a view of a matrix that is row-interleaved onto a MatStore.
Definition matrix.hh:296
Provides a view of a vertical slice of either a MatStore or a Tile.
Definition matrix.hh:225
Matrix Register Specification.
constexpr unsigned MaxSmeVecLenInBytes
Definition types.hh:510
constexpr RegClass matRegClass
Definition mat.hh:92
MatTileCol< ElemType > getTileVSlice(MatRegContainer &reg, uint8_t tile_idx, uint8_t col_idx)
Definition mat.hh:116
gem5::MatStore< MaxSmeVecLenInBytes, MaxSmeVecLenInBytes > MatRegContainer
Definition mat.hh:60
const int NumMatrixRegs
Definition mat.hh:88
MatRow< ElemType > getHSlice(MatRegContainer &reg, uint8_t row_idx)
Definition mat.hh:122
static TypedRegClassOps< ArmISA::MatRegContainer > matRegClassOps
Definition mat.hh:90
MatTile< ElemType > getTile(MatRegContainer &reg, uint8_t tile_idx)
Definition mat.hh:104
MatTileRow< ElemType > getTileHSlice(MatRegContainer &reg, uint8_t tile_idx, uint8_t row_idx)
Definition mat.hh:110
MatCol< ElemType > getVSlice(MatRegContainer &reg, uint8_t col_idx)
Definition mat.hh:128
Bitfield< 5, 3 > reg
Definition types.hh:92
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
constexpr char MatRegClassName[]
Definition reg_class.hh:80
@ MatRegClass
Matrix Register.
Definition reg_class.hh:68

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