gem5
v24.0.0.0
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arch
x86
insts
microdebug.hh
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/*
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* Copyright 2021 Google Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __ARCH_X86_INSTS_MICRODEBUG_HH__
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#define __ARCH_X86_INSTS_MICRODEBUG_HH__
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#include "
arch/x86/insts/microop.hh
"
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namespace
gem5
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{
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namespace
X86ISA
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{
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class
MicroDebug
:
public
X86ISA::X86MicroopBase
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{
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protected
:
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std::shared_ptr<GenericISA::M5DebugFault>
fault
;
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public
:
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MicroDebug
(
ExtMachInst
mach_inst,
const
char
*mnem,
const
char
*inst_mnem,
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uint64_t set_flags,
GenericISA::M5DebugFault
*_fault) :
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X86MicroopBase
(mach_inst, mnem, inst_mnem, set_flags, No_OpClass),
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fault
(_fault)
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{}
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Fault
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execute
(
ExecContext
*xc,
trace::InstRecord
*traceData)
const override
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{
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return
fault
;
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}
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std::string
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generateDisassembly
(
Addr
pc
,
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const
loader::SymbolTable
*symtab)
const override
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{
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std::stringstream response;
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printMnemonic
(response,
instMnem
,
mnemonic
);
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response <<
"\""
<<
fault
->message() <<
"\""
;
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return
response.str();
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}
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};
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}
// namespace X86ISA
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}
// namespace gem5
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#endif
//__ARCH_X86_INSTS_MICRODEBUG_HH__
gem5::ExecContext
The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate th...
Definition
exec_context.hh:72
gem5::GenericISA::M5DebugFault
Definition
debugfaults.hh:56
gem5::StaticInst::mnemonic
const char * mnemonic
Base mnemonic (e.g., "add").
Definition
static_inst.hh:268
gem5::X86ISA::MicroDebug
Definition
microdebug.hh:40
gem5::X86ISA::MicroDebug::execute
Fault execute(ExecContext *xc, trace::InstRecord *traceData) const override
Definition
microdebug.hh:52
gem5::X86ISA::MicroDebug::fault
std::shared_ptr< GenericISA::M5DebugFault > fault
Definition
microdebug.hh:42
gem5::X86ISA::MicroDebug::MicroDebug
MicroDebug(ExtMachInst mach_inst, const char *mnem, const char *inst_mnem, uint64_t set_flags, GenericISA::M5DebugFault *_fault)
Definition
microdebug.hh:45
gem5::X86ISA::MicroDebug::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition
microdebug.hh:58
gem5::X86ISA::X86MicroopBase
Definition
microop.hh:98
gem5::X86ISA::X86MicroopBase::instMnem
const char * instMnem
Definition
microop.hh:100
gem5::X86ISA::X86StaticInst::printMnemonic
static void printMnemonic(std::ostream &os, const char *mnemonic)
Definition
static_inst.cc:51
gem5::loader::SymbolTable
Definition
symtab.hh:152
gem5::trace::InstRecord
Definition
insttracer.hh:62
microop.hh
gem5::X86ISA::pc
Bitfield< 19 > pc
Definition
misc.hh:840
gem5
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition
binary32.hh:36
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition
types.hh:249
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition
types.hh:147
gem5::X86ISA::ExtMachInst
Definition
types.hh:213
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