gem5  v22.0.0.2
static_inst.cc
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38 
40 
41 #include "arch/x86/regs/segment.hh"
42 #include "cpu/reg_class.hh"
43 
44 namespace gem5
45 {
46 
47 namespace X86ISA
48 {
49 
50 void
51 X86StaticInst::printMnemonic(std::ostream &os, const char *mnemonic)
52 {
53  ccprintf(os, " %s ", mnemonic);
54 }
55 
56 void
57 X86StaticInst::printMnemonic(std::ostream &os, const char *instMnemonic,
58  const char *mnemonic)
59 {
60  ccprintf(os, " %s : %s ", instMnemonic, mnemonic);
61 }
62 
63 void X86StaticInst::printSegment(std::ostream &os, int segment)
64 {
65  switch (segment)
66  {
67  case segment_idx::Es:
68  ccprintf(os, "ES");
69  break;
70  case segment_idx::Cs:
71  ccprintf(os, "CS");
72  break;
73  case segment_idx::Ss:
74  ccprintf(os, "SS");
75  break;
76  case segment_idx::Ds:
77  ccprintf(os, "DS");
78  break;
79  case segment_idx::Fs:
80  ccprintf(os, "FS");
81  break;
82  case segment_idx::Gs:
83  ccprintf(os, "GS");
84  break;
85  case segment_idx::Hs:
86  ccprintf(os, "HS");
87  break;
88  case segment_idx::Tsl:
89  ccprintf(os, "TSL");
90  break;
91  case segment_idx::Tsg:
92  ccprintf(os, "TSG");
93  break;
94  case segment_idx::Ls:
95  ccprintf(os, "LS");
96  break;
97  case segment_idx::Ms:
98  ccprintf(os, "MS");
99  break;
100  case segment_idx::Tr:
101  ccprintf(os, "TR");
102  break;
103  case segment_idx::Idtr:
104  ccprintf(os, "IDTR");
105  break;
106  default:
107  panic("Unrecognized segment %d\n", segment);
108  }
109 }
110 
111 void
112 X86StaticInst::divideStep(uint64_t dividend, uint64_t divisor,
113  uint64_t &quotient, uint64_t &remainder)
114 {
115  // Check for divide by zero.
116  assert(divisor != 0);
117  // If the divisor is bigger than the dividend, don't do anything.
118  if (divisor <= dividend) {
119  // Shift the divisor so it's msb lines up with the dividend.
120  int dividendMsb = findMsbSet(dividend);
121  int divisorMsb = findMsbSet(divisor);
122  int shift = dividendMsb - divisorMsb;
123  divisor <<= shift;
124  // Compute what we'll add to the quotient if the divisor isn't
125  // now larger than the dividend.
126  uint64_t quotientBit = 1;
127  quotientBit <<= shift;
128  // If we need to step back a bit (no pun intended) because the
129  // divisor got too to large, do that here. This is the "or two"
130  // part of one or two bit division.
131  if (divisor > dividend) {
132  quotientBit >>= 1;
133  divisor >>= 1;
134  }
135  // Decrement the remainder and increment the quotient.
136  quotient += quotientBit;
137  remainder -= divisor;
138  }
139 }
140 
141 void
142 X86StaticInst::printReg(std::ostream &os, RegId reg, int size)
143 {
144  assert(size == 1 || size == 2 || size == 4 || size == 8);
145  static const char * abcdFormats[9] =
146  {"", "%s", "%sx", "", "e%sx", "", "", "", "r%sx"};
147  static const char * piFormats[9] =
148  {"", "%s", "%s", "", "e%s", "", "", "", "r%s"};
149  static const char * longFormats[9] =
150  {"", "r%sb", "r%sw", "", "r%sd", "", "", "", "r%s"};
151  static const char * microFormats[9] =
152  {"", "t%db", "t%dw", "", "t%dd", "", "", "", "t%d"};
153 
154  RegIndex reg_idx = reg.index();
155 
156  switch (reg.classValue()) {
157  case IntRegClass:
158  {
159  const char * suffix = "";
160  bool fold = reg_idx & IntFoldBit;
161  reg_idx &= ~IntFoldBit;
162 
163  if (fold)
164  suffix = "h";
165  else if (reg_idx < 8 && size == 1)
166  suffix = "l";
167 
168  switch (reg_idx) {
169  case int_reg::Rax:
170  ccprintf(os, abcdFormats[size], "a");
171  break;
172  case int_reg::Rbx:
173  ccprintf(os, abcdFormats[size], "b");
174  break;
175  case int_reg::Rcx:
176  ccprintf(os, abcdFormats[size], "c");
177  break;
178  case int_reg::Rdx:
179  ccprintf(os, abcdFormats[size], "d");
180  break;
181  case int_reg::Rsp:
182  ccprintf(os, piFormats[size], "sp");
183  break;
184  case int_reg::Rbp:
185  ccprintf(os, piFormats[size], "bp");
186  break;
187  case int_reg::Rsi:
188  ccprintf(os, piFormats[size], "si");
189  break;
190  case int_reg::Rdi:
191  ccprintf(os, piFormats[size], "di");
192  break;
193  case int_reg::R8:
194  ccprintf(os, longFormats[size], "8");
195  break;
196  case int_reg::R9:
197  ccprintf(os, longFormats[size], "9");
198  break;
199  case int_reg::R10:
200  ccprintf(os, longFormats[size], "10");
201  break;
202  case int_reg::R11:
203  ccprintf(os, longFormats[size], "11");
204  break;
205  case int_reg::R12:
206  ccprintf(os, longFormats[size], "12");
207  break;
208  case int_reg::R13:
209  ccprintf(os, longFormats[size], "13");
210  break;
211  case int_reg::R14:
212  ccprintf(os, longFormats[size], "14");
213  break;
214  case int_reg::R15:
215  ccprintf(os, longFormats[size], "15");
216  break;
217  default:
218  ccprintf(os, microFormats[size],
219  reg_idx - int_reg::MicroBegin);
220  }
221  ccprintf(os, suffix);
222  }
223  break;
224  case FloatRegClass:
225  if (reg_idx < NumMMXRegs) {
226  ccprintf(os, "%%mmx%d", reg_idx);
227  return;
228  }
229  reg_idx -= NumMMXRegs;
230  if (reg_idx < NumXMMRegs * 2) {
231  ccprintf(os, "%%xmm%d_%s", reg_idx / 2,
232  (reg_idx % 2) ? "high": "low");
233  return;
234  }
235  reg_idx -= NumXMMRegs * 2;
236  if (reg_idx < NumMicroFpRegs) {
237  ccprintf(os, "%%ufp%d", reg_idx);
238  return;
239  }
240  reg_idx -= NumMicroFpRegs;
241  ccprintf(os, "%%st(%d)", reg_idx);
242  break;
243  case CCRegClass:
244  ccprintf(os, "%%cc%d", reg_idx);
245  break;
246  case MiscRegClass:
247  switch (reg_idx) {
248  default:
249  ccprintf(os, "%%ctrl%d", reg_idx);
250  }
251  break;
252  default:
253  panic("Unrecognized register class.");
254  }
255 }
256 
257 void
258 X86StaticInst::printMem(std::ostream &os, uint8_t segment,
259  uint8_t scale, RegIndex index, RegIndex base,
260  uint64_t disp, uint8_t addressSize, bool rip)
261 {
262  bool someAddr = false;
263  printSegment(os, segment);
264  os << ":[";
265  if (rip) {
266  os << "rip";
267  someAddr = true;
268  } else {
269  if (scale != 0 && index != int_reg::NumRegs) {
270  if (scale != 1)
271  ccprintf(os, "%d*", scale);
272  printReg(os, RegId(IntRegClass, index), addressSize);
273  someAddr = true;
274  }
275  if (base != int_reg::NumRegs) {
276  if (someAddr)
277  os << " + ";
278  printReg(os, RegId(IntRegClass, base), addressSize);
279  someAddr = true;
280  }
281  }
282  if (disp != 0) {
283  if (someAddr)
284  os << " + ";
285  ccprintf(os, "%#x", disp);
286  someAddr = true;
287  }
288  if (!someAddr)
289  os << "0";
290  os << "]";
291 }
292 
293 std::string
295  Addr pc, const loader::SymbolTable *symtab) const
296 {
297  std::stringstream ss;
298 
300 
301  return ss.str();
302 }
303 
304 } // namespace X86ISA
305 } // namespace gem5
gem5::X86ISA::pc
Bitfield< 19 > pc
Definition: misc.hh:805
gem5::PowerISA::int_reg::R14
constexpr RegId R14(IntRegClass, _R14Idx)
gem5::X86ISA::segment_idx::Ls
@ Ls
Definition: segment.hh:59
gem5::X86ISA::segment_idx::Ds
@ Ds
Definition: segment.hh:53
static_inst.hh
gem5::X86ISA::X86StaticInst::divideStep
static void divideStep(uint64_t divident, uint64_t divisor, uint64_t &quotient, uint64_t &remainder)
Definition: static_inst.cc:112
gem5::X86ISA::scale
scale
Definition: types.hh:97
gem5::CCRegClass
@ CCRegClass
Condition-code register.
Definition: reg_class.hh:65
gem5::X86ISA::segment_idx::Tsl
@ Tsl
Definition: segment.hh:57
gem5::X86ISA::X86StaticInst::printMem
static void printMem(std::ostream &os, uint8_t segment, uint8_t scale, RegIndex index, RegIndex base, uint64_t disp, uint8_t addressSize, bool rip)
Definition: static_inst.cc:258
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::X86ISA::base
Bitfield< 51, 12 > base
Definition: pagetable.hh:141
sc_dt::remainder
return remainder
Definition: scfx_rep.cc:2201
gem5::X86ISA::segment_idx::Cs
@ Cs
Definition: segment.hh:51
gem5::ccprintf
void ccprintf(cp::Print &print)
Definition: cprintf.hh:130
gem5::PowerISA::int_reg::R10
constexpr RegId R10(IntRegClass, _R10Idx)
gem5::ArmISA::shift
Bitfield< 6, 5 > shift
Definition: types.hh:117
gem5::FloatRegClass
@ FloatRegClass
Floating-point register.
Definition: reg_class.hh:59
gem5::ArmISA::cc_reg::NumRegs
@ NumRegs
Definition: cc.hh:60
gem5::PowerISA::int_reg::R8
constexpr RegId R8(IntRegClass, _R8Idx)
segment.hh
gem5::X86ISA::segment_idx::Gs
@ Gs
Definition: segment.hh:55
gem5::X86ISA::segment_idx::Es
@ Es
Definition: segment.hh:50
gem5::X86ISA::NumXMMRegs
const int NumXMMRegs
Definition: x86_traits.hh:53
gem5::PowerISA::int_reg::R11
constexpr RegId R11(IntRegClass, _R11Idx)
gem5::X86ISA::NumMMXRegs
const int NumMMXRegs
Definition: x86_traits.hh:52
gem5::PowerISA::int_reg::R9
constexpr RegId R9(IntRegClass, _R9Idx)
ss
std::stringstream ss
Definition: trace.test.cc:45
gem5::X86ISA::segment_idx::Tr
@ Tr
Definition: segment.hh:64
gem5::X86ISA::segment_idx::Tsg
@ Tsg
Definition: segment.hh:58
gem5::X86ISA::segment_idx::Ss
@ Ss
Definition: segment.hh:52
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::X86ISA::segment_idx::Ms
@ Ms
Definition: segment.hh:60
gem5::X86ISA::X86StaticInst::printReg
static void printReg(std::ostream &os, RegId reg, int size)
Definition: static_inst.cc:142
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:58
gem5::MiscRegClass
@ MiscRegClass
Control (misc) register.
Definition: reg_class.hh:66
gem5::PowerISA::int_reg::R15
constexpr RegId R15(IntRegClass, _R15Idx)
gem5::X86ISA::X86StaticInst::printSegment
static void printSegment(std::ostream &os, int segment)
Definition: static_inst.cc:63
gem5::X86ISA::segment_idx::Fs
@ Fs
Definition: segment.hh:54
gem5::X86ISA::os
Bitfield< 17 > os
Definition: misc.hh:803
gem5::X86ISA::index
Bitfield< 5, 3 > index
Definition: types.hh:98
gem5::X86ISA::X86StaticInst::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: static_inst.cc:294
reg_class.hh
gem5::findMsbSet
constexpr int findMsbSet(uint64_t val)
Returns the bit position of the MSB that is set in the input.
Definition: bitfield.hh:260
gem5::X86ISA::IntFoldBit
constexpr RegIndex IntFoldBit
Definition: int.hh:149
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5::StaticInst::mnemonic
const char * mnemonic
Base mnemonic (e.g., "add").
Definition: static_inst.hh:259
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::X86ISA::segment_idx::Idtr
@ Idtr
Definition: segment.hh:65
gem5::PowerISA::int_reg::R12
constexpr RegId R12(IntRegClass, _R12Idx)
gem5::PowerISA::int_reg::R13
constexpr RegId R13(IntRegClass, _R13Idx)
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:126
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::X86ISA::X86StaticInst::printMnemonic
static void printMnemonic(std::ostream &os, const char *mnemonic)
Definition: static_inst.cc:51
gem5::X86ISA::NumMicroFpRegs
const int NumMicroFpRegs
Definition: x86_traits.hh:54
gem5::X86ISA::segment_idx::Hs
@ Hs
Definition: segment.hh:56

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