gem5 v24.0.0.0
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noncaching.hh
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1/*
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37
38#ifndef __CPU_SIMPLE_NONCACHING_HH__
39#define __CPU_SIMPLE_NONCACHING_HH__
40
42#include "cpu/simple/atomic.hh"
43#include "mem/backdoor.hh"
44#include "params/BaseNonCachingSimpleCPU.hh"
45
46namespace gem5
47{
48
54{
55 public:
56 NonCachingSimpleCPU(const BaseNonCachingSimpleCPUParams &p);
57
58 void verifyMemoryMode() const override;
59
60 protected:
62
63 Tick sendPacket(RequestPort &port, const PacketPtr &pkt) override;
64 Tick fetchInstMem() override;
65};
66
67} // namespace gem5
68
69#endif // __CPU_SIMPLE_NONCACHING_HH__
The AddrRangeMap uses an STL map to implement an interval tree for address decoding.
The NonCachingSimpleCPU is an AtomicSimpleCPU using the 'atomic_noncaching' memory mode instead of ju...
Definition noncaching.hh:54
Tick fetchInstMem() override
Definition noncaching.cc:91
Tick sendPacket(RequestPort &port, const PacketPtr &pkt) override
Definition noncaching.cc:66
NonCachingSimpleCPU(const BaseNonCachingSimpleCPUParams &p)
Definition noncaching.cc:47
void verifyMemoryMode() const override
Verify that the system is in a memory mode supported by the CPU.
Definition noncaching.cc:57
AddrRangeMap< MemBackdoorPtr, 1 > memBackdoors
Definition noncaching.hh:61
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition packet.hh:295
A RequestPort is a specialisation of a Port, which implements the default protocol for the three diff...
Definition port.hh:136
Bitfield< 0 > p
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
uint64_t Tick
Tick count type.
Definition types.hh:58

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