38#ifndef __CPU_SIMPLE_NONCACHING_HH__
39#define __CPU_SIMPLE_NONCACHING_HH__
44#include "params/BaseNonCachingSimpleCPU.hh"
The AddrRangeMap uses an STL map to implement an interval tree for address decoding.
The NonCachingSimpleCPU is an AtomicSimpleCPU using the 'atomic_noncaching' memory mode instead of ju...
Tick fetchInstMem() override
Tick sendPacket(RequestPort &port, const PacketPtr &pkt) override
NonCachingSimpleCPU(const BaseNonCachingSimpleCPUParams &p)
void verifyMemoryMode() const override
Verify that the system is in a memory mode supported by the CPU.
AddrRangeMap< MemBackdoorPtr, 1 > memBackdoors
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
A RequestPort is a specialisation of a Port, which implements the default protocol for the three diff...
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
uint64_t Tick
Tick count type.