atomic.hh

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#ifndef __CPU_SIMPLE_ATOMIC_HH__
#define __CPU_SIMPLE_ATOMIC_HH__
 
#include "cpu/simple/base.hh"
#include "cpu/simple/exec_context.hh"
#include "mem/request.hh"
#include "params/BaseAtomicSimpleCPU.hh"
#include "sim/probe/probe.hh"
 
namespace gem5
{
 
class AtomicSimpleCPU : public BaseSimpleCPU
{
  public:
 
    AtomicSimpleCPU(const BaseAtomicSimpleCPUParams &params);
    virtual ~AtomicSimpleCPU();
 
    void init() override;
 
  protected:
    EventFunctionWrapper tickEvent;
 
    const int width;
    bool locked;
    const bool simulate_data_stalls;
    const bool simulate_inst_stalls;
 
    // main simulation loop (one cycle)
    void tick();
 
    bool
    isCpuDrained() const
    {
        SimpleExecContext &t_info = *threadInfo[curThread];
        return t_info.thread->pcState().microPC() == 0 &&
            !locked && !t_info.stayAtPC;
    }
 
    bool tryCompleteDrain();
 
    virtual Tick sendPacket(RequestPort &port, const PacketPtr &pkt);
    virtual Tick fetchInstMem();
 
    class AtomicCPUPort : public RequestPort
    {
 
      public:
 
        AtomicCPUPort(const std::string &_name)
            : RequestPort(_name)
        { }
 
      protected:
 
        bool
        recvTimingResp(PacketPtr pkt)
        {
            panic("Atomic CPU doesn't expect recvTimingResp!\n");
        }
 
        void
        recvReqRetry()
        {
            panic("Atomic CPU doesn't expect recvRetry!\n");
        }
 
    };
 
    class AtomicCPUDPort : public AtomicCPUPort
    {
 
      public:
        AtomicCPUDPort(const std::string &_name, BaseSimpleCPU *_cpu)
            : AtomicCPUPort(_name), cpu(_cpu)
        {
            cacheBlockMask = ~(cpu->cacheLineSize() - 1);
        }
 
        bool isSnooping() const { return true; }
 
        Addr cacheBlockMask;
      protected:
        BaseSimpleCPU *cpu;
 
        virtual Tick recvAtomicSnoop(PacketPtr pkt);
        virtual void recvFunctionalSnoop(PacketPtr pkt);
    };
 
 
    AtomicCPUPort icachePort;
    AtomicCPUDPort dcachePort;
 
 
    RequestPtr ifetch_req;
    RequestPtr data_read_req;
    RequestPtr data_write_req;
    RequestPtr data_amo_req;
 
    bool dcache_access;
    Tick dcache_latency;
 
    ProbePointArg<std::pair<SimpleThread *, const StaticInstPtr>> *ppCommit;
 
  protected:
 
    Port &getDataPort() override { return dcachePort; }
 
    Port &getInstPort() override { return icachePort; }
 
    void threadSnoop(PacketPtr pkt, ThreadID sender);
 
  public:
 
    DrainState drain() override;
    void drainResume() override;
 
    void switchOut() override;
    void takeOverFrom(BaseCPU *old_cpu) override;
 
    void verifyMemoryMode() const override;
 
    void activateContext(ThreadID thread_num) override;
    void suspendContext(ThreadID thread_num) override;
 
    bool genMemFragmentRequest(const RequestPtr &req, Addr frag_addr,
                               int size, Request::Flags flags,
                               const std::vector<bool> &byte_enable,
                               int &frag_size, int &size_left) const;
 
    Fault readMem(Addr addr, uint8_t *data, unsigned size,
                  Request::Flags flags,
                  const std::vector<bool> &byte_enable=std::vector<bool>())
        override;
 
    Fault
    initiateMemMgmtCmd(Request::Flags flags) override
    {
        panic("initiateMemMgmtCmd() is for timing accesses, and "
              "should never be called on AtomicSimpleCPU.\n");
    }
 
    void
    htmSendAbortSignal(ThreadID tid, uint64_t htm_uid,
                       HtmFailureFaultCause cause) override
    {
        panic("htmSendAbortSignal() is for timing accesses, and should "
              "never be called on AtomicSimpleCPU.");
    }
 
    Fault writeMem(uint8_t *data, unsigned size,
                   Addr addr, Request::Flags flags, uint64_t *res,
                   const std::vector<bool> &byte_enable=std::vector<bool>())
        override;
 
    Fault amoMem(Addr addr, uint8_t *data, unsigned size,
                 Request::Flags flags, AtomicOpFunctorPtr amo_op) override;
 
    void regProbePoints() override;
 
    void printAddr(Addr a);
};
 
} // namespace gem5
 
#endif // __CPU_SIMPLE_ATOMIC_HH__