gem5  v21.1.0.2
atomic.hh
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40 
41 #ifndef __CPU_SIMPLE_ATOMIC_HH__
42 #define __CPU_SIMPLE_ATOMIC_HH__
43 
44 #include "cpu/simple/base.hh"
46 #include "mem/request.hh"
47 #include "params/AtomicSimpleCPU.hh"
48 #include "sim/probe/probe.hh"
49 
50 namespace gem5
51 {
52 
54 {
55  public:
56 
57  AtomicSimpleCPU(const AtomicSimpleCPUParams &params);
58  virtual ~AtomicSimpleCPU();
59 
60  void init() override;
61 
62  protected:
64 
65  const int width;
66  bool locked;
69 
70  // main simulation loop (one cycle)
71  void tick();
72 
91  bool
92  isCpuDrained() const
93  {
95  return t_info.thread->microPC() == 0 &&
96  !locked && !t_info.stayAtPC;
97  }
98 
104  bool tryCompleteDrain();
105 
106  virtual Tick sendPacket(RequestPort &port, const PacketPtr &pkt);
107  virtual Tick fetchInstMem();
108 
115  class AtomicCPUPort : public RequestPort
116  {
117 
118  public:
119 
120  AtomicCPUPort(const std::string &_name, BaseSimpleCPU* _cpu)
121  : RequestPort(_name, _cpu)
122  { }
123 
124  protected:
125 
126  bool
128  {
129  panic("Atomic CPU doesn't expect recvTimingResp!\n");
130  }
131 
132  void
134  {
135  panic("Atomic CPU doesn't expect recvRetry!\n");
136  }
137 
138  };
139 
141  {
142 
143  public:
144  AtomicCPUDPort(const std::string &_name, BaseSimpleCPU *_cpu)
145  : AtomicCPUPort(_name, _cpu), cpu(_cpu)
146  {
147  cacheBlockMask = ~(cpu->cacheLineSize() - 1);
148  }
149 
150  bool isSnooping() const { return true; }
151 
153  protected:
155 
156  virtual Tick recvAtomicSnoop(PacketPtr pkt);
157  virtual void recvFunctionalSnoop(PacketPtr pkt);
158  };
159 
160 
163 
164 
169 
172 
175 
176  protected:
177 
179  Port &getDataPort() override { return dcachePort; }
180 
182  Port &getInstPort() override { return icachePort; }
183 
185  void threadSnoop(PacketPtr pkt, ThreadID sender);
186 
187  public:
188 
189  DrainState drain() override;
190  void drainResume() override;
191 
192  void switchOut() override;
193  void takeOverFrom(BaseCPU *old_cpu) override;
194 
195  void verifyMemoryMode() const override;
196 
197  void activateContext(ThreadID thread_num) override;
198  void suspendContext(ThreadID thread_num) override;
199 
216  bool genMemFragmentRequest(const RequestPtr &req, Addr frag_addr,
217  int size, Request::Flags flags,
218  const std::vector<bool> &byte_enable,
219  int &frag_size, int &size_left) const;
220 
221  Fault readMem(Addr addr, uint8_t *data, unsigned size,
222  Request::Flags flags,
223  const std::vector<bool> &byte_enable=std::vector<bool>())
224  override;
225 
226  Fault
228  {
229  panic("initiateHtmCmd() is for timing accesses, and should "
230  "never be called on AtomicSimpleCPU.\n");
231  }
232 
233  void
235  {
236  panic("htmSendAbortSignal() is for timing accesses, and should "
237  "never be called on AtomicSimpleCPU.\n");
238  }
239 
240  Fault writeMem(uint8_t *data, unsigned size,
241  Addr addr, Request::Flags flags, uint64_t *res,
242  const std::vector<bool> &byte_enable=std::vector<bool>())
243  override;
244 
245  Fault amoMem(Addr addr, uint8_t *data, unsigned size,
246  Request::Flags flags, AtomicOpFunctorPtr amo_op) override;
247 
248  void regProbePoints() override;
249 
254  void printAddr(Addr a);
255 };
256 
257 } // namespace gem5
258 
259 #endif // __CPU_SIMPLE_ATOMIC_HH__
gem5::AtomicSimpleCPU::tryCompleteDrain
bool tryCompleteDrain()
Try to complete a drain request.
Definition: atomic.cc:176
gem5::AtomicSimpleCPU::regProbePoints
void regProbePoints() override
Register probe points for this object.
Definition: atomic.cc:761
gem5::AtomicSimpleCPU::writeMem
Fault writeMem(uint8_t *data, unsigned size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable=std::vector< bool >()) override
Definition: atomic.cc:438
gem5::BaseSimpleCPU::threadInfo
std::vector< SimpleExecContext * > threadInfo
Definition: base.hh:100
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::AtomicSimpleCPU::simulate_data_stalls
const bool simulate_data_stalls
Definition: atomic.hh:67
gem5::AtomicSimpleCPU::getDataPort
Port & getDataPort() override
Return a reference to the data port.
Definition: atomic.hh:179
gem5::HtmFailureFaultCause
HtmFailureFaultCause
Definition: htm.hh:47
gem5::AtomicSimpleCPU::width
const int width
Definition: atomic.hh:65
gem5::AtomicSimpleCPU::sendPacket
virtual Tick sendPacket(RequestPort &port, const PacketPtr &pkt)
Definition: atomic.cc:273
gem5::AtomicSimpleCPU::AtomicCPUPort
An AtomicCPUPort overrides the default behaviour of the recvAtomicSnoop and ignores the packet instea...
Definition: atomic.hh:115
gem5::AtomicSimpleCPU::readMem
Fault readMem(Addr addr, uint8_t *data, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >()) override
Definition: atomic.cc:361
gem5::BaseCPU::cacheLineSize
unsigned int cacheLineSize() const
Get the cache line size of the system.
Definition: base.hh:381
gem5::AtomicSimpleCPU::~AtomicSimpleCPU
virtual ~AtomicSimpleCPU()
Definition: atomic.cc:95
gem5::AtomicSimpleCPU::data_read_req
RequestPtr data_read_req
Definition: atomic.hh:166
gem5::ArmISA::a
Bitfield< 8 > a
Definition: misc_types.hh:65
gem5::AtomicSimpleCPU::dcachePort
AtomicCPUDPort dcachePort
Definition: atomic.hh:162
std::vector< bool >
request.hh
gem5::AtomicSimpleCPU::printAddr
void printAddr(Addr a)
Print state of address in memory system via PrintReq (for debugging).
Definition: atomic.cc:770
gem5::AtomicSimpleCPU::AtomicCPUDPort::cacheBlockMask
Addr cacheBlockMask
Definition: atomic.hh:152
gem5::AtomicSimpleCPU::init
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: atomic.cc:64
gem5::AtomicSimpleCPU::simulate_inst_stalls
const bool simulate_inst_stalls
Definition: atomic.hh:68
gem5::RequestPort
A RequestPort is a specialisation of a Port, which implements the default protocol for the three diff...
Definition: port.hh:77
gem5::SimpleThread::microPC
MicroPC microPC() const override
Definition: simple_thread.hh:441
gem5::AtomicSimpleCPU
Definition: atomic.hh:53
gem5::Flags< FlagsType >
gem5::DrainState
DrainState
Object drain/handover states.
Definition: drain.hh:74
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::AtomicSimpleCPU::suspendContext
void suspendContext(ThreadID thread_num) override
Notify the CPU that the indicated context is now suspended.
Definition: atomic.cc:247
gem5::SimObject::params
const Params & params() const
Definition: sim_object.hh:176
gem5::AtomicSimpleCPU::takeOverFrom
void takeOverFrom(BaseCPU *old_cpu) override
Load the state of a CPU from the previous CPU object, invoked on all new CPUs that are about to be sw...
Definition: atomic.cc:204
gem5::AtomicSimpleCPU::data_amo_req
RequestPtr data_amo_req
Definition: atomic.hh:168
gem5::AtomicSimpleCPU::AtomicCPUPort::AtomicCPUPort
AtomicCPUPort(const std::string &_name, BaseSimpleCPU *_cpu)
Definition: atomic.hh:120
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::AtomicSimpleCPU::AtomicCPUDPort::cpu
BaseSimpleCPU * cpu
Definition: atomic.hh:154
gem5::AtomicSimpleCPU::fetchInstMem
virtual Tick fetchInstMem()
Definition: atomic.cc:744
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::SimpleExecContext::stayAtPC
bool stayAtPC
Definition: exec_context.hh:70
gem5::AtomicSimpleCPU::tickEvent
EventFunctionWrapper tickEvent
Definition: atomic.hh:63
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::AtomicSimpleCPU::AtomicSimpleCPU
AtomicSimpleCPU(const AtomicSimpleCPUParams &params)
Definition: atomic.cc:75
gem5::AtomicSimpleCPU::verifyMemoryMode
void verifyMemoryMode() const override
Verify that the system is in a memory mode supported by the CPU.
Definition: atomic.cc:213
gem5::AtomicSimpleCPU::AtomicCPUDPort::isSnooping
bool isSnooping() const
Determine if this request port is snooping or not.
Definition: atomic.hh:150
gem5::AtomicSimpleCPU::drainResume
void drainResume() override
Resume execution after a successful drain.
Definition: atomic.cc:143
gem5::BaseCPU
Definition: base.hh:107
gem5::BaseSimpleCPU
Definition: base.hh:80
gem5::AtomicSimpleCPU::genMemFragmentRequest
bool genMemFragmentRequest(const RequestPtr &req, Addr frag_addr, int size, Request::Flags flags, const std::vector< bool > &byte_enable, int &frag_size, int &size_left) const
Helper function used to set up the request for a single fragment of a memory access.
Definition: atomic.cc:333
gem5::AtomicSimpleCPU::getInstPort
Port & getInstPort() override
Return a reference to the instruction port.
Definition: atomic.hh:182
gem5::AtomicSimpleCPU::activateContext
void activateContext(ThreadID thread_num) override
Notify the CPU that the indicated context is now active.
Definition: atomic.cc:221
gem5::AtomicSimpleCPU::locked
bool locked
Definition: atomic.hh:66
gem5::AtomicSimpleCPU::isCpuDrained
bool isCpuDrained() const
Check if a system is in a drained state.
Definition: atomic.hh:92
gem5::AtomicSimpleCPU::amoMem
Fault amoMem(Addr addr, uint8_t *data, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op) override
Definition: atomic.cc:548
gem5::AtomicSimpleCPU::drain
DrainState drain() override
Draining is the process of clearing out the states of SimObjects.These are the SimObjects that are pa...
Definition: atomic.cc:103
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::AtomicSimpleCPU::dcache_latency
Tick dcache_latency
Definition: atomic.hh:171
gem5::AtomicSimpleCPU::htmSendAbortSignal
void htmSendAbortSignal(HtmFailureFaultCause cause) override
This function is used to instruct the memory subsystem that a transaction should be aborted and the s...
Definition: atomic.hh:234
gem5::AtomicSimpleCPU::data_write_req
RequestPtr data_write_req
Definition: atomic.hh:167
gem5::ProbePointArg
ProbePointArg generates a point for the class of Arg.
Definition: thermal_domain.hh:54
gem5::EventFunctionWrapper
Definition: eventq.hh:1115
gem5::SimpleExecContext::thread
SimpleThread * thread
Definition: exec_context.hh:64
base.hh
gem5::AtomicSimpleCPU::switchOut
void switchOut() override
Prepare for another CPU to take over execution.
Definition: atomic.cc:193
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
gem5::SimpleExecContext
Definition: exec_context.hh:60
gem5::AtomicSimpleCPU::AtomicCPUPort::recvReqRetry
void recvReqRetry()
Called by the peer if sendTimingReq was called on this peer (causing recvTimingReq to be called on th...
Definition: atomic.hh:133
gem5::AtomicSimpleCPU::ifetch_req
RequestPtr ifetch_req
Definition: atomic.hh:165
gem5::AtomicSimpleCPU::threadSnoop
void threadSnoop(PacketPtr pkt, ThreadID sender)
Perform snoop for other cpu-local thread contexts.
Definition: atomic.cc:125
gem5::AtomicSimpleCPU::icachePort
AtomicCPUPort icachePort
Definition: atomic.hh:161
gem5::AtomicSimpleCPU::AtomicCPUPort::recvTimingResp
bool recvTimingResp(PacketPtr pkt)
Receive a timing response from the peer.
Definition: atomic.hh:127
exec_context.hh
gem5::AtomicSimpleCPU::ppCommit
ProbePointArg< std::pair< SimpleThread *, const StaticInstPtr > > * ppCommit
Probe Points.
Definition: atomic.hh:174
gem5::AtomicSimpleCPU::AtomicCPUDPort::AtomicCPUDPort
AtomicCPUDPort(const std::string &_name, BaseSimpleCPU *_cpu)
Definition: atomic.hh:144
gem5::AtomicSimpleCPU::initiateHtmCmd
Fault initiateHtmCmd(Request::Flags flags) override
Hardware transactional memory commands (HtmCmds), e.g.
Definition: atomic.hh:227
gem5::AtomicSimpleCPU::dcache_access
bool dcache_access
Definition: atomic.hh:170
gem5::AtomicSimpleCPU::AtomicCPUDPort::recvFunctionalSnoop
virtual void recvFunctionalSnoop(PacketPtr pkt)
Receive a functional snoop request packet from the peer.
Definition: atomic.cc:309
gem5::AtomicOpFunctorPtr
std::unique_ptr< AtomicOpFunctor > AtomicOpFunctorPtr
Definition: amo.hh:242
probe.hh
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::AtomicSimpleCPU::AtomicCPUDPort::recvAtomicSnoop
virtual Tick recvAtomicSnoop(PacketPtr pkt)
Receive an atomic snoop request packet from our peer.
Definition: atomic.cc:279
gem5::AtomicSimpleCPU::AtomicCPUDPort
Definition: atomic.hh:140
gem5::AtomicSimpleCPU::tick
void tick()
Definition: atomic.cc:612
gem5::BaseSimpleCPU::curThread
ThreadID curThread
Definition: base.hh:83
gem5::Named::_name
const std::string _name
Definition: named.hh:41
gem5::ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:242
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84

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