gem5  v21.2.1.1
noncaching.cc
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37 
38 #include "cpu/simple/noncaching.hh"
39 
40 #include <cassert>
41 
42 #include "arch/generic/decoder.hh"
43 
44 namespace gem5
45 {
46 
47 NonCachingSimpleCPU::NonCachingSimpleCPU(const NonCachingSimpleCPUParams &p)
49 {
50  assert(p.numThreads == 1);
51  fatal_if(!FullSystem && p.workload.size() != 1,
52  "only one workload allowed");
53 }
54 
55 void
57 {
58  if (!(system->isAtomicMode() && system->bypassCaches())) {
59  fatal("The direct CPU requires the memory system to be in the "
60  "'atomic_noncaching' mode.\n");
61  }
62 }
63 
64 Tick
66 {
67  MemBackdoorPtr bd = nullptr;
68  Tick latency = port.sendAtomicBackdoor(pkt, bd);
69 
70  // If the target gave us a backdoor for next time and we didn't
71  // already have it, record it.
72  if (bd && memBackdoors.insert(bd->range(), bd) != memBackdoors.end()) {
73  // Install a callback to erase this backdoor if it goes away.
74  auto callback = [this](const MemBackdoor &backdoor) {
75  for (auto it = memBackdoors.begin();
76  it != memBackdoors.end(); it++) {
77  if (it->second == &backdoor) {
78  memBackdoors.erase(it);
79  return;
80  }
81  }
82  panic("Got invalidation for unknown memory backdoor.");
83  };
84  bd->addInvalidationCallback(callback);
85  }
86  return latency;
87 }
88 
89 Tick
91 {
92  auto bd_it = memBackdoors.contains(ifetch_req->getPaddr());
93  if (bd_it == memBackdoors.end())
95 
96  auto &decoder = threadInfo[curThread]->thread->decoder;
97 
98  auto *bd = bd_it->second;
99  Addr offset = ifetch_req->getPaddr() - bd->range().start();
100  memcpy(decoder->moreBytesPtr(), bd->ptr() + offset, ifetch_req->getSize());
101  return 0;
102 }
103 
104 } // namespace gem5
fatal
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:190
gem5::BaseSimpleCPU::threadInfo
std::vector< SimpleExecContext * > threadInfo
Definition: base.hh:102
gem5::NonCachingSimpleCPU::fetchInstMem
Tick fetchInstMem() override
Definition: noncaching.cc:90
gem5::X86ISA::system
Bitfield< 15 > system
Definition: misc.hh:1003
gem5::PowerISA::bd
Bitfield< 15, 2 > bd
Definition: types.hh:79
gem5::NonCachingSimpleCPU::verifyMemoryMode
void verifyMemoryMode() const override
Definition: noncaching.cc:56
gem5::RequestPort
A RequestPort is a specialisation of a Port, which implements the default protocol for the three diff...
Definition: port.hh:77
gem5::RequestPort::sendAtomicBackdoor
Tick sendAtomicBackdoor(PacketPtr pkt, MemBackdoorPtr &backdoor)
Send an atomic request packet like above, but also request a backdoor to the data being accessed.
Definition: port.hh:474
gem5::AtomicSimpleCPU
Definition: atomic.hh:53
decoder.hh
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::AtomicSimpleCPU::fetchInstMem
virtual Tick fetchInstMem()
Definition: atomic.cc:744
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::ArmISA::offset
Bitfield< 23, 0 > offset
Definition: types.hh:144
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::NonCachingSimpleCPU::memBackdoors
AddrRangeMap< MemBackdoorPtr, 1 > memBackdoors
Definition: noncaching.hh:61
gem5::MemBackdoor
Definition: backdoor.hh:41
gem5::FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:220
noncaching.hh
gem5::AtomicSimpleCPU::ifetch_req
RequestPtr ifetch_req
Definition: atomic.hh:165
decoder
output decoder
Definition: nop.cc:61
gem5::NonCachingSimpleCPU::NonCachingSimpleCPU
NonCachingSimpleCPU(const NonCachingSimpleCPUParams &p)
Definition: noncaching.cc:47
fatal_if
#define fatal_if(cond,...)
Conditional fatal macro that checks the supplied condition and only causes a fatal error if the condi...
Definition: logging.hh:226
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::BaseSimpleCPU::curThread
ThreadID curThread
Definition: base.hh:86
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::NonCachingSimpleCPU::sendPacket
Tick sendPacket(RequestPort &port, const PacketPtr &pkt) override
Definition: noncaching.cc:65

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