gem5  v21.1.0.2
pred_inst.cc
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40 
42 
43 namespace gem5
44 {
45 
46 namespace ArmISA
47 {
48 std::string
50  Addr pc, const loader::SymbolTable *symtab) const
51 {
52  std::stringstream ss;
53  unsigned rotate = machInst.rotate * 2;
54  uint32_t imm = machInst.imm;
55  imm = (imm << (32 - rotate)) | (imm >> rotate);
56  printDataInst(ss, false, machInst.opcode4 == 0, machInst.sField,
57  (IntRegIndex)(uint32_t)machInst.rd,
58  (IntRegIndex)(uint32_t)machInst.rn,
59  (IntRegIndex)(uint32_t)machInst.rm,
60  (IntRegIndex)(uint32_t)machInst.rs,
61  machInst.shiftSize, (ArmShiftType)(uint32_t)machInst.shift,
62  imm);
63  return ss.str();
64 }
65 
66 std::string
68  Addr pc, const loader::SymbolTable *symtab) const
69 {
70  std::stringstream ss;
71  printDataInst(ss, true, machInst.opcode4 == 0, machInst.sField,
72  (IntRegIndex)(uint32_t)machInst.rd,
73  (IntRegIndex)(uint32_t)machInst.rn,
74  (IntRegIndex)(uint32_t)machInst.rm,
75  (IntRegIndex)(uint32_t)machInst.rs,
76  machInst.shiftSize, (ArmShiftType)(uint32_t)machInst.shift,
77  imm);
78  return ss.str();
79 }
80 
81 std::string
83  Addr pc, const loader::SymbolTable *symtab) const
84 {
85  std::stringstream ss;
86  printDataInst(ss, true, false, /*XXX not really s*/ false, dest, op1,
87  INTREG_ZERO, INTREG_ZERO, 0, LSL, imm);
88  return ss.str();
89 }
90 
91 std::string
93  Addr pc, const loader::SymbolTable *symtab) const
94 {
95  std::stringstream ss;
96  printDataInst(ss, false, true, /*XXX not really s*/ false, dest, op1,
97  op2, INTREG_ZERO, shiftAmt, shiftType, 0);
98  return ss.str();
99 }
100 
101 std::string
103  Addr pc, const loader::SymbolTable *symtab) const
104 {
105  std::stringstream ss;
106  printDataInst(ss, false, false, /*XXX not really s*/ false, dest, op1,
107  op2, shift, 0, shiftType, 0);
108  return ss.str();
109 }
110 
111 std::string
113  Addr pc, const loader::SymbolTable *symtab) const
114 {
115  std::stringstream ss;
116 
117  ccprintf(ss, "%-10s ", mnemonic);
118 
119  return ss.str();
120 }
121 
122 } // namespace ArmISA
123 } // namespace gem5
gem5::ArmISA::DataImmOp::op1
IntRegIndex op1
Definition: pred_inst.hh:284
gem5::ArmISA::DataImmOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: pred_inst.cc:82
gem5::ArmISA::DataRegOp::shiftType
ArmShiftType shiftType
Definition: pred_inst.hh:305
gem5::ArmISA::DataRegOp::dest
IntRegIndex dest
Definition: pred_inst.hh:303
gem5::ArmISA::PredImmOp::imm
uint32_t imm
Definition: pred_inst.hh:240
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::ArmISA::rotate
Bitfield< 11, 8 > rotate
Definition: types.hh:134
gem5::ArmISA::ArmStaticInst::machInst
ExtMachInst machInst
Definition: static_inst.hh:149
gem5::ArmISA::DataRegOp::op1
IntRegIndex op1
Definition: pred_inst.hh:303
gem5::ccprintf
void ccprintf(cp::Print &print)
Definition: cprintf.hh:130
gem5::ArmISA::DataRegRegOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: pred_inst.cc:102
gem5::ArmISA::DataRegOp::op2
IntRegIndex op2
Definition: pred_inst.hh:303
gem5::ArmISA::DataRegOp::shiftAmt
int32_t shiftAmt
Definition: pred_inst.hh:304
gem5::ArmISA::DataRegOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: pred_inst.cc:92
gem5::ArmISA::PredImmOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: pred_inst.cc:67
gem5::ArmISA::DataImmOp::imm
uint32_t imm
Definition: pred_inst.hh:285
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
pred_inst.hh
gem5::ArmISA::DataRegRegOp::dest
IntRegIndex dest
Definition: pred_inst.hh:322
gem5::ArmISA::imm
Bitfield< 7, 0 > imm
Definition: types.hh:132
gem5::ArmISA::DataRegRegOp::shift
IntRegIndex shift
Definition: pred_inst.hh:322
gem5::ArmISA::ArmStaticInst::printDataInst
void printDataInst(std::ostream &os, bool withImm) const
gem5::ArmISA::ss
Bitfield< 21 > ss
Definition: misc_types.hh:59
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::ArmISA::DataImmOp::dest
IntRegIndex dest
Definition: pred_inst.hh:284
gem5::ArmISA::PredMacroOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: pred_inst.cc:112
gem5::ArmISA::PredIntOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: pred_inst.cc:49
gem5::StaticInst::mnemonic
const char * mnemonic
Base mnemonic (e.g., "add").
Definition: static_inst.hh:281
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::ArmISA::DataRegRegOp::op2
IntRegIndex op2
Definition: pred_inst.hh:322
gem5::ArmISA::DataRegRegOp::op1
IntRegIndex op1
Definition: pred_inst.hh:322
gem5::ArmISA::DataRegRegOp::shiftType
ArmShiftType shiftType
Definition: pred_inst.hh:323

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