gem5  v22.0.0.1
regfile.cc
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41 
42 #include "cpu/o3/regfile.hh"
43 
44 #include "cpu/o3/free_list.hh"
45 
46 namespace gem5
47 {
48 
49 namespace o3
50 {
51 
52 PhysRegFile::PhysRegFile(unsigned _numPhysicalIntRegs,
53  unsigned _numPhysicalFloatRegs,
54  unsigned _numPhysicalVecRegs,
55  unsigned _numPhysicalVecPredRegs,
56  unsigned _numPhysicalCCRegs,
57  const BaseISA::RegClasses &reg_classes)
58  : intRegFile(reg_classes.at(IntRegClass), _numPhysicalIntRegs),
59  floatRegFile(reg_classes.at(FloatRegClass), _numPhysicalFloatRegs),
60  vectorRegFile(reg_classes.at(VecRegClass), _numPhysicalVecRegs),
61  vectorElemRegFile(reg_classes.at(VecElemClass), _numPhysicalVecRegs * (
62  reg_classes.at(VecElemClass).numRegs() /
63  reg_classes.at(VecRegClass).numRegs())),
64  vecPredRegFile(reg_classes.at(VecPredRegClass), _numPhysicalVecPredRegs),
65  ccRegFile(reg_classes.at(CCRegClass), _numPhysicalCCRegs),
66  numPhysicalIntRegs(_numPhysicalIntRegs),
67  numPhysicalFloatRegs(_numPhysicalFloatRegs),
68  numPhysicalVecRegs(_numPhysicalVecRegs),
69  numPhysicalVecElemRegs(_numPhysicalVecRegs * (
70  reg_classes.at(VecElemClass).numRegs() /
71  reg_classes.at(VecRegClass).numRegs())),
72  numPhysicalVecPredRegs(_numPhysicalVecPredRegs),
73  numPhysicalCCRegs(_numPhysicalCCRegs),
74  totalNumRegs(_numPhysicalIntRegs
75  + _numPhysicalFloatRegs
76  + _numPhysicalVecRegs
77  + numPhysicalVecElemRegs
78  + _numPhysicalVecPredRegs
79  + _numPhysicalCCRegs)
80 {
81  RegIndex phys_reg;
82  RegIndex flat_reg_idx = 0;
83 
84  // The initial batch of registers are the integer ones
85  for (phys_reg = 0; phys_reg < numPhysicalIntRegs; phys_reg++) {
86  intRegIds.emplace_back(IntRegClass, phys_reg, flat_reg_idx++);
87  }
88 
89  // The next batch of the registers are the floating-point physical
90  // registers; put them onto the floating-point free list.
91  for (phys_reg = 0; phys_reg < numPhysicalFloatRegs; phys_reg++) {
92  floatRegIds.emplace_back(FloatRegClass, phys_reg, flat_reg_idx++);
93  }
94 
95  // The next batch of the registers are the vector physical
96  // registers; put them onto the vector free list.
97  for (phys_reg = 0; phys_reg < numPhysicalVecRegs; phys_reg++) {
98  vecRegIds.emplace_back(VecRegClass, phys_reg, flat_reg_idx++);
99  }
100  // The next batch of the registers are the vector element physical
101  // registers; put them onto the vector free list.
102  for (phys_reg = 0; phys_reg < numPhysicalVecElemRegs; phys_reg++) {
103  vecElemIds.emplace_back(VecElemClass, phys_reg, flat_reg_idx++);
104  }
105 
106  // The next batch of the registers are the predicate physical
107  // registers; put them onto the predicate free list.
108  for (phys_reg = 0; phys_reg < numPhysicalVecPredRegs; phys_reg++) {
109  vecPredRegIds.emplace_back(VecPredRegClass, phys_reg, flat_reg_idx++);
110  }
111 
112  // The rest of the registers are the condition-code physical
113  // registers; put them onto the condition-code free list.
114  for (phys_reg = 0; phys_reg < numPhysicalCCRegs; phys_reg++) {
115  ccRegIds.emplace_back(CCRegClass, phys_reg, flat_reg_idx++);
116  }
117 
118  // Misc regs have a fixed mapping but still need PhysRegIds.
119  for (phys_reg = 0; phys_reg < reg_classes.at(MiscRegClass).numRegs();
120  phys_reg++) {
121  miscRegIds.emplace_back(MiscRegClass, phys_reg, 0);
122  }
123 }
124 
125 
126 void
128 {
129  // Initialize the free lists.
130  int reg_idx = 0;
131 
132  // The initial batch of registers are the integer ones
133  for (reg_idx = 0; reg_idx < numPhysicalIntRegs; reg_idx++) {
134  assert(intRegIds[reg_idx].index() == reg_idx);
135  }
136  freeList->addRegs(intRegIds.begin(), intRegIds.end());
137 
138  // The next batch of the registers are the floating-point physical
139  // registers; put them onto the floating-point free list.
140  for (reg_idx = 0; reg_idx < numPhysicalFloatRegs; reg_idx++) {
141  assert(floatRegIds[reg_idx].index() == reg_idx);
142  }
143  freeList->addRegs(floatRegIds.begin(), floatRegIds.end());
144 
145  /* The next batch of the registers are the vector physical
146  * registers; put them onto the vector free list. */
147  for (reg_idx = 0; reg_idx < numPhysicalVecRegs; reg_idx++) {
148  assert(vecRegIds[reg_idx].index() == reg_idx);
149  }
150  freeList->addRegs(vecRegIds.begin(), vecRegIds.end());
151  for (reg_idx = 0; reg_idx < numPhysicalVecElemRegs; reg_idx++) {
152  assert(vecElemIds[reg_idx].index() == reg_idx);
153  }
154  freeList->addRegs(vecElemIds.begin(), vecElemIds.end());
155 
156  // The next batch of the registers are the predicate physical
157  // registers; put them onto the predicate free list.
158  for (reg_idx = 0; reg_idx < numPhysicalVecPredRegs; reg_idx++) {
159  assert(vecPredRegIds[reg_idx].index() == reg_idx);
160  }
161  freeList->addRegs(vecPredRegIds.begin(), vecPredRegIds.end());
162 
163  // The rest of the registers are the condition-code physical
164  // registers; put them onto the condition-code free list.
165  for (reg_idx = 0; reg_idx < numPhysicalCCRegs; reg_idx++) {
166  assert(ccRegIds[reg_idx].index() == reg_idx);
167  }
168  freeList->addRegs(ccRegIds.begin(), ccRegIds.end());
169 }
170 
173 {
174  switch (cls)
175  {
176  case IntRegClass:
177  return std::make_pair(intRegIds.begin(), intRegIds.end());
178  case FloatRegClass:
179  return std::make_pair(floatRegIds.begin(), floatRegIds.end());
180  case VecRegClass:
181  return std::make_pair(vecRegIds.begin(), vecRegIds.end());
182  case VecElemClass:
183  return std::make_pair(vecElemIds.begin(), vecElemIds.end());
184  case VecPredRegClass:
185  return std::make_pair(vecPredRegIds.begin(), vecPredRegIds.end());
186  case CCRegClass:
187  return std::make_pair(ccRegIds.begin(), ccRegIds.end());
188  case MiscRegClass:
189  return std::make_pair(miscRegIds.begin(), miscRegIds.end());
190  case InvalidRegClass:
191  panic("Tried to get register IDs for the invalid class.");
192  }
193  /* There is no way to make an empty iterator */
194  return std::make_pair(PhysIds::iterator(),
195  PhysIds::iterator());
196 }
197 
200 {
201  switch (reg->classValue()) {
202  case VecRegClass:
203  return &vecRegIds[reg->index()];
204  case VecElemClass:
205  return &vecElemIds[reg->index()];
206  default:
207  panic_if(!reg->is(VecElemClass),
208  "Trying to get the register of a %s register", reg->className());
209  }
210  return nullptr;
211 }
212 
213 } // namespace o3
214 } // namespace gem5
gem5::o3::PhysRegFile::numPhysicalVecElemRegs
unsigned numPhysicalVecElemRegs
Number of physical vector element registers.
Definition: regfile.hh:121
gem5::VecElemClass
@ VecElemClass
Vector Register Native Elem lane.
Definition: reg_class.hh:63
gem5::MipsISA::index
Bitfield< 30, 0 > index
Definition: pra_constants.hh:47
gem5::InvalidRegClass
@ InvalidRegClass
Definition: reg_class.hh:67
gem5::o3::PhysRegFile::getRegIds
IdRange getRegIds(RegClassType cls)
Get the PhysRegIds of the elems of all vector registers.
Definition: regfile.cc:172
gem5::CCRegClass
@ CCRegClass
Condition-code register.
Definition: reg_class.hh:65
gem5::o3::UnifiedFreeList
FreeList class that simply holds the list of free integer and floating point registers.
Definition: free_list.hh:124
gem5::o3::PhysRegFile::ccRegIds
std::vector< PhysRegId > ccRegIds
Definition: regfile.hh:98
std::vector< RegClass >
regfile.hh
gem5::o3::PhysRegFile::PhysRegFile
PhysRegFile(unsigned _numPhysicalIntRegs, unsigned _numPhysicalFloatRegs, unsigned _numPhysicalVecRegs, unsigned _numPhysicalVecPredRegs, unsigned _numPhysicalCCRegs, const BaseISA::RegClasses &classes)
Constructs a physical register file with the specified amount of integer and floating point registers...
Definition: regfile.cc:52
gem5::VecPredRegClass
@ VecPredRegClass
Definition: reg_class.hh:64
gem5::o3::PhysRegFile::getTrueId
PhysRegIdPtr getTrueId(PhysRegIdPtr reg)
Get the true physical register id.
Definition: regfile.cc:199
gem5::o3::PhysRegFile::numPhysicalVecRegs
unsigned numPhysicalVecRegs
Number of physical vector registers.
Definition: regfile.hh:116
gem5::ArmISA::at
Bitfield< 35, 32 > at
Definition: misc_types.hh:155
gem5::o3::PhysRegFile::floatRegIds
std::vector< PhysRegId > floatRegIds
Definition: regfile.hh:82
gem5::FloatRegClass
@ FloatRegClass
Floating-point register.
Definition: reg_class.hh:59
gem5::o3::PhysRegFile::miscRegIds
std::vector< PhysRegId > miscRegIds
Misc Reg Ids.
Definition: regfile.hh:101
gem5::o3::PhysRegFile::vecElemIds
std::vector< PhysRegId > vecElemIds
Definition: regfile.hh:90
gem5::o3::PhysRegFile::vecRegIds
std::vector< PhysRegId > vecRegIds
Definition: regfile.hh:86
gem5::o3::UnifiedFreeList::addRegs
void addRegs(InputIt first, InputIt last)
Adds a register back to the free list.
Definition: free_list.hh:167
std::pair
STL pair class.
Definition: stl.hh:58
gem5::o3::PhysRegFile::intRegIds
std::vector< PhysRegId > intRegIds
Definition: regfile.hh:78
gem5::o3::PhysRegFile::numPhysicalIntRegs
unsigned numPhysicalIntRegs
Number of physical general purpose registers.
Definition: regfile.hh:106
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::o3::PhysRegFile::numPhysicalVecPredRegs
unsigned numPhysicalVecPredRegs
Number of physical predicate registers.
Definition: regfile.hh:126
gem5::IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:58
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:204
gem5::RegClassType
RegClassType
Enumerate the classes of registers.
Definition: reg_class.hh:56
gem5::MiscRegClass
@ MiscRegClass
Control (misc) register.
Definition: reg_class.hh:66
gem5::o3::PhysRegFile::numPhysicalCCRegs
unsigned numPhysicalCCRegs
Number of physical CC registers.
Definition: regfile.hh:131
gem5::o3::PhysRegFile::initFreeList
void initFreeList(UnifiedFreeList *freeList)
Initialize the free list.
Definition: regfile.cc:127
gem5::o3::PhysRegFile::vecPredRegIds
std::vector< PhysRegId > vecPredRegIds
Definition: regfile.hh:94
free_list.hh
gem5::PhysRegId
Physical register ID.
Definition: reg_class.hh:245
gem5::o3::PhysRegFile::numPhysicalFloatRegs
unsigned numPhysicalFloatRegs
Number of physical floating point registers.
Definition: regfile.hh:111
gem5::VecRegClass
@ VecRegClass
Vector Register.
Definition: reg_class.hh:61
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178

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