gem5  v21.2.0.0
regfile.cc
Go to the documentation of this file.
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41 
42 #include "cpu/o3/regfile.hh"
43 
44 #include "cpu/o3/free_list.hh"
45 
46 namespace gem5
47 {
48 
49 namespace o3
50 {
51 
52 PhysRegFile::PhysRegFile(unsigned _numPhysicalIntRegs,
53  unsigned _numPhysicalFloatRegs,
54  unsigned _numPhysicalVecRegs,
55  unsigned _numPhysicalVecPredRegs,
56  unsigned _numPhysicalCCRegs,
57  const BaseISA::RegClasses &regClasses)
58  : intRegFile(_numPhysicalIntRegs),
59  floatRegFile(_numPhysicalFloatRegs),
60  vectorRegFile(_numPhysicalVecRegs),
61  vectorElemRegFile(_numPhysicalVecRegs * TheISA::NumVecElemPerVecReg),
62  vecPredRegFile(_numPhysicalVecPredRegs),
63  ccRegFile(_numPhysicalCCRegs),
64  numPhysicalIntRegs(_numPhysicalIntRegs),
65  numPhysicalFloatRegs(_numPhysicalFloatRegs),
66  numPhysicalVecRegs(_numPhysicalVecRegs),
67  numPhysicalVecElemRegs(_numPhysicalVecRegs *
68  TheISA::NumVecElemPerVecReg),
69  numPhysicalVecPredRegs(_numPhysicalVecPredRegs),
70  numPhysicalCCRegs(_numPhysicalCCRegs),
71  totalNumRegs(_numPhysicalIntRegs
72  + _numPhysicalFloatRegs
73  + _numPhysicalVecRegs
74  + _numPhysicalVecRegs * TheISA::NumVecElemPerVecReg
75  + _numPhysicalVecPredRegs
76  + _numPhysicalCCRegs)
77 {
78  RegIndex phys_reg;
79  RegIndex flat_reg_idx = 0;
80 
81  // The initial batch of registers are the integer ones
82  for (phys_reg = 0; phys_reg < numPhysicalIntRegs; phys_reg++) {
83  intRegIds.emplace_back(IntRegClass, phys_reg, flat_reg_idx++);
84  }
85 
86  zeroReg = RegId(IntRegClass, regClasses.at(IntRegClass).zeroReg());
87 
88  // The next batch of the registers are the floating-point physical
89  // registers; put them onto the floating-point free list.
90  for (phys_reg = 0; phys_reg < numPhysicalFloatRegs; phys_reg++) {
91  floatRegIds.emplace_back(FloatRegClass, phys_reg, flat_reg_idx++);
92  }
93 
94  // The next batch of the registers are the vector physical
95  // registers; put them onto the vector free list.
96  for (phys_reg = 0; phys_reg < numPhysicalVecRegs; phys_reg++) {
97  vectorRegFile[phys_reg].zero();
98  vecRegIds.emplace_back(VecRegClass, phys_reg, flat_reg_idx++);
99  }
100  // The next batch of the registers are the vector element physical
101  // registers; they refer to the same containers as the vector
102  // registers, just a different (and incompatible) way to access
103  // them; put them onto the vector free list.
104  for (phys_reg = 0; phys_reg < numPhysicalVecRegs; phys_reg++) {
105  for (ElemIndex eIdx = 0; eIdx < TheISA::NumVecElemPerVecReg; eIdx++) {
106  vecElemIds.emplace_back(VecElemClass, phys_reg,
107  eIdx, flat_reg_idx++);
108  }
109  }
110 
111  // The next batch of the registers are the predicate physical
112  // registers; put them onto the predicate free list.
113  for (phys_reg = 0; phys_reg < numPhysicalVecPredRegs; phys_reg++) {
114  vecPredRegIds.emplace_back(VecPredRegClass, phys_reg, flat_reg_idx++);
115  }
116 
117  // The rest of the registers are the condition-code physical
118  // registers; put them onto the condition-code free list.
119  for (phys_reg = 0; phys_reg < numPhysicalCCRegs; phys_reg++) {
120  ccRegIds.emplace_back(CCRegClass, phys_reg, flat_reg_idx++);
121  }
122 
123  // Misc regs have a fixed mapping but still need PhysRegIds.
124  for (phys_reg = 0; phys_reg < regClasses.at(MiscRegClass).size();
125  phys_reg++) {
126  miscRegIds.emplace_back(MiscRegClass, phys_reg, 0);
127  }
128 }
129 
130 
131 void
133 {
134  // Initialize the free lists.
135  int reg_idx = 0;
136 
137  // The initial batch of registers are the integer ones
138  for (reg_idx = 0; reg_idx < numPhysicalIntRegs; reg_idx++) {
139  assert(intRegIds[reg_idx].index() == reg_idx);
140  }
141  freeList->addRegs(intRegIds.begin(), intRegIds.end());
142 
143  // The next batch of the registers are the floating-point physical
144  // registers; put them onto the floating-point free list.
145  for (reg_idx = 0; reg_idx < numPhysicalFloatRegs; reg_idx++) {
146  assert(floatRegIds[reg_idx].index() == reg_idx);
147  }
148  freeList->addRegs(floatRegIds.begin(), floatRegIds.end());
149 
150  /* The next batch of the registers are the vector physical
151  * registers; put them onto the vector free list. */
152  for (reg_idx = 0; reg_idx < numPhysicalVecRegs; reg_idx++) {
153  assert(vecRegIds[reg_idx].index() == reg_idx);
154  for (ElemIndex elemIdx = 0; elemIdx < TheISA::NumVecElemPerVecReg;
155  elemIdx++) {
156  assert(vecElemIds[reg_idx * TheISA::NumVecElemPerVecReg +
157  elemIdx].index() == reg_idx);
158  assert(vecElemIds[reg_idx * TheISA::NumVecElemPerVecReg +
159  elemIdx].elemIndex() == elemIdx);
160  }
161  }
162  freeList->addRegs(vecRegIds.begin(), vecRegIds.end());
163  freeList->addRegs(vecElemIds.begin(), vecElemIds.end());
164 
165  // The next batch of the registers are the predicate physical
166  // registers; put them onto the predicate free list.
167  for (reg_idx = 0; reg_idx < numPhysicalVecPredRegs; reg_idx++) {
168  assert(vecPredRegIds[reg_idx].index() == reg_idx);
169  }
170  freeList->addRegs(vecPredRegIds.begin(), vecPredRegIds.end());
171 
172  // The rest of the registers are the condition-code physical
173  // registers; put them onto the condition-code free list.
174  for (reg_idx = 0; reg_idx < numPhysicalCCRegs; reg_idx++) {
175  assert(ccRegIds[reg_idx].index() == reg_idx);
176  }
177  freeList->addRegs(ccRegIds.begin(), ccRegIds.end());
178 }
179 
182 {
183  switch (cls)
184  {
185  case IntRegClass:
186  return std::make_pair(intRegIds.begin(), intRegIds.end());
187  case FloatRegClass:
188  return std::make_pair(floatRegIds.begin(), floatRegIds.end());
189  case VecRegClass:
190  return std::make_pair(vecRegIds.begin(), vecRegIds.end());
191  case VecElemClass:
192  return std::make_pair(vecElemIds.begin(), vecElemIds.end());
193  case VecPredRegClass:
194  return std::make_pair(vecPredRegIds.begin(), vecPredRegIds.end());
195  case CCRegClass:
196  return std::make_pair(ccRegIds.begin(), ccRegIds.end());
197  case MiscRegClass:
198  return std::make_pair(miscRegIds.begin(), miscRegIds.end());
199  }
200  /* There is no way to make an empty iterator */
201  return std::make_pair(PhysIds::iterator(),
202  PhysIds::iterator());
203 }
204 
207 {
208  switch (reg->classValue()) {
209  case VecRegClass:
210  return &vecRegIds[reg->index()];
211  case VecElemClass:
212  return &vecElemIds[reg->index() * TheISA::NumVecElemPerVecReg +
213  reg->elemIndex()];
214  default:
215  panic_if(!reg->is(VecElemClass),
216  "Trying to get the register of a %s register", reg->className());
217  }
218  return nullptr;
219 }
220 
221 } // namespace o3
222 } // namespace gem5
gem5::ArmISA::NumVecElemPerVecReg
constexpr unsigned NumVecElemPerVecReg
Definition: vec.hh:58
gem5::o3::PhysRegFile::zeroReg
RegId zeroReg
Definition: regfile.hh:77
gem5::VecElemClass
@ VecElemClass
Vector Register Native Elem lane.
Definition: reg_class.hh:63
gem5::MipsISA::index
Bitfield< 30, 0 > index
Definition: pra_constants.hh:47
gem5::o3::PhysRegFile::getRegIds
IdRange getRegIds(RegClassType cls)
Get the PhysRegIds of the elems of all vector registers.
Definition: regfile.cc:181
gem5::CCRegClass
@ CCRegClass
Condition-code register.
Definition: reg_class.hh:65
gem5::o3::UnifiedFreeList
FreeList class that simply holds the list of free integer and floating point registers.
Definition: free_list.hh:122
gem5::o3::PhysRegFile::ccRegIds
std::vector< PhysRegId > ccRegIds
Definition: regfile.hh:97
std::vector< RegClass >
gem5::VecPredRegClass
@ VecPredRegClass
Definition: reg_class.hh:64
gem5::o3::PhysRegFile::getTrueId
PhysRegIdPtr getTrueId(PhysRegIdPtr reg)
Get the true physical register id.
Definition: regfile.cc:206
gem5::o3::PhysRegFile::numPhysicalVecRegs
unsigned numPhysicalVecRegs
Number of physical vector registers.
Definition: regfile.hh:115
gem5::o3::PhysRegFile::floatRegIds
std::vector< PhysRegId > floatRegIds
Definition: regfile.hh:81
gem5::FloatRegClass
@ FloatRegClass
Floating-point register.
Definition: reg_class.hh:59
gem5::o3::PhysRegFile::miscRegIds
std::vector< PhysRegId > miscRegIds
Misc Reg Ids.
Definition: regfile.hh:100
gem5::o3::PhysRegFile::vecElemIds
std::vector< PhysRegId > vecElemIds
Definition: regfile.hh:89
gem5::o3::PhysRegFile::vecRegIds
std::vector< PhysRegId > vecRegIds
Definition: regfile.hh:85
gem5::o3::UnifiedFreeList::addRegs
void addRegs(InputIt first, InputIt last)
Adds a register back to the free list.
Definition: free_list.hh:265
std::pair
STL pair class.
Definition: stl.hh:58
gem5::o3::PhysRegFile::intRegIds
std::vector< PhysRegId > intRegIds
Definition: regfile.hh:76
regfile.hh
gem5::ElemIndex
uint16_t ElemIndex
Logical vector register elem index type.
Definition: types.hh:179
gem5::o3::PhysRegFile::vectorRegFile
std::vector< TheISA::VecRegContainer > vectorRegFile
Vector register file.
Definition: regfile.hh:84
gem5::o3::PhysRegFile::numPhysicalIntRegs
unsigned numPhysicalIntRegs
Number of physical general purpose registers.
Definition: regfile.hh:105
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::o3::PhysRegFile::numPhysicalVecPredRegs
unsigned numPhysicalVecPredRegs
Number of physical predicate registers.
Definition: regfile.hh:125
gem5::IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:58
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:204
gem5::RegClassType
RegClassType
Enumerate the classes of registers.
Definition: reg_class.hh:56
gem5::o3::PhysRegFile::PhysRegFile
PhysRegFile(unsigned _numPhysicalIntRegs, unsigned _numPhysicalFloatRegs, unsigned _numPhysicalVecRegs, unsigned _numPhysicalVecPredRegs, unsigned _numPhysicalCCRegs, const BaseISA::RegClasses &regClasses)
Constructs a physical register file with the specified amount of integer and floating point registers...
Definition: regfile.cc:52
gem5::MiscRegClass
@ MiscRegClass
Control (misc) register.
Definition: reg_class.hh:66
gem5::o3::PhysRegFile::numPhysicalCCRegs
unsigned numPhysicalCCRegs
Number of physical CC registers.
Definition: regfile.hh:130
gem5::o3::PhysRegFile::initFreeList
void initFreeList(UnifiedFreeList *freeList)
Initialize the free list.
Definition: regfile.cc:132
gem5::o3::PhysRegFile::vecPredRegIds
std::vector< PhysRegId > vecPredRegIds
Definition: regfile.hh:93
free_list.hh
gem5::PhysRegId
Physical register ID.
Definition: reg_class.hh:224
gem5::o3::PhysRegFile::numPhysicalFloatRegs
unsigned numPhysicalFloatRegs
Number of physical floating point registers.
Definition: regfile.hh:110
gem5::VecRegClass
@ VecRegClass
Vector Register.
Definition: reg_class.hh:61
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:113

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