gem5 v24.0.0.0
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regfile.cc
Go to the documentation of this file.
1/*
2 * Copyright (c) 2016-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2005 The Regents of The University of Michigan
15 * Copyright (c) 2013 Advanced Micro Devices, Inc.
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 */
41
42#include "cpu/o3/regfile.hh"
43
44#include "cpu/o3/free_list.hh"
45
46namespace gem5
47{
48
49namespace o3
50{
51
52PhysRegFile::PhysRegFile(unsigned _numPhysicalIntRegs,
53 unsigned _numPhysicalFloatRegs,
54 unsigned _numPhysicalVecRegs,
55 unsigned _numPhysicalVecPredRegs,
56 unsigned _numPhysicalMatRegs,
57 unsigned _numPhysicalCCRegs,
58 const BaseISA::RegClasses &reg_classes)
59 : intRegFile(*reg_classes.at(IntRegClass), _numPhysicalIntRegs),
60 floatRegFile(*reg_classes.at(FloatRegClass), _numPhysicalFloatRegs),
61 vectorRegFile(*reg_classes.at(VecRegClass), _numPhysicalVecRegs),
62 vectorElemRegFile(*reg_classes.at(VecElemClass), _numPhysicalVecRegs * (
63 reg_classes.at(VecElemClass)->numRegs() /
64 reg_classes.at(VecRegClass)->numRegs())),
65 vecPredRegFile(*reg_classes.at(VecPredRegClass),
66 _numPhysicalVecPredRegs),
67 matRegFile(*reg_classes.at(MatRegClass), _numPhysicalMatRegs),
68 ccRegFile(*reg_classes.at(CCRegClass), _numPhysicalCCRegs),
69 numPhysicalIntRegs(_numPhysicalIntRegs),
70 numPhysicalFloatRegs(_numPhysicalFloatRegs),
71 numPhysicalVecRegs(_numPhysicalVecRegs),
72 numPhysicalVecElemRegs(_numPhysicalVecRegs * (
73 reg_classes.at(VecElemClass)->numRegs() /
74 reg_classes.at(VecRegClass)->numRegs())),
75 numPhysicalVecPredRegs(_numPhysicalVecPredRegs),
76 numPhysicalMatRegs(_numPhysicalMatRegs),
77 numPhysicalCCRegs(_numPhysicalCCRegs),
78 totalNumRegs(_numPhysicalIntRegs
79 + _numPhysicalFloatRegs
80 + _numPhysicalVecRegs
81 + numPhysicalVecElemRegs
82 + _numPhysicalVecPredRegs
83 + _numPhysicalMatRegs
84 + _numPhysicalCCRegs)
85{
86 RegIndex phys_reg;
87 RegIndex flat_reg_idx = 0;
88
89 // The initial batch of registers are the integer ones
90 for (phys_reg = 0; phys_reg < numPhysicalIntRegs; phys_reg++) {
91 intRegIds.emplace_back(*reg_classes.at(IntRegClass),
92 phys_reg, flat_reg_idx++);
93 }
94
95 // The next batch of the registers are the floating-point physical
96 // registers; put them onto the floating-point free list.
97 for (phys_reg = 0; phys_reg < numPhysicalFloatRegs; phys_reg++) {
98 floatRegIds.emplace_back(*reg_classes.at(FloatRegClass),
99 phys_reg, flat_reg_idx++);
100 }
101
102 // The next batch of the registers are the vector physical
103 // registers; put them onto the vector free list.
104 for (phys_reg = 0; phys_reg < numPhysicalVecRegs; phys_reg++) {
105 vecRegIds.emplace_back(*reg_classes.at(VecRegClass), phys_reg,
106 flat_reg_idx++);
107 }
108 // The next batch of the registers are the vector element physical
109 // registers; put them onto the vector free list.
110 for (phys_reg = 0; phys_reg < numPhysicalVecElemRegs; phys_reg++) {
111 vecElemIds.emplace_back(*reg_classes.at(VecElemClass), phys_reg,
112 flat_reg_idx++);
113 }
114
115 // The next batch of the registers are the predicate physical
116 // registers; put them onto the predicate free list.
117 for (phys_reg = 0; phys_reg < numPhysicalVecPredRegs; phys_reg++) {
118 vecPredRegIds.emplace_back(*reg_classes.at(VecPredRegClass), phys_reg,
119 flat_reg_idx++);
120 }
121
122 // The next batch of the registers are the matrix physical
123 // registers; put them onto the matrix free list.
124 for (phys_reg = 0; phys_reg < numPhysicalMatRegs; phys_reg++) {
125 matRegIds.emplace_back(*reg_classes.at(MatRegClass), phys_reg,
126 flat_reg_idx++);
127 }
128
129 // The rest of the registers are the condition-code physical
130 // registers; put them onto the condition-code free list.
131 for (phys_reg = 0; phys_reg < numPhysicalCCRegs; phys_reg++) {
132 ccRegIds.emplace_back(*reg_classes.at(CCRegClass), phys_reg,
133 flat_reg_idx++);
134 }
135
136 // Misc regs have a fixed mapping but still need PhysRegIds.
137 for (phys_reg = 0; phys_reg < reg_classes.at(MiscRegClass)->numRegs();
138 phys_reg++) {
139 miscRegIds.emplace_back(*reg_classes.at(MiscRegClass), phys_reg, 0);
140 }
141}
142
143
144void
146{
147 // Initialize the free lists.
148 int reg_idx = 0;
149
150 // The initial batch of registers are the integer ones
151 for (reg_idx = 0; reg_idx < numPhysicalIntRegs; reg_idx++) {
152 assert(intRegIds[reg_idx].index() == reg_idx);
153 }
154 freeList->addRegs(intRegIds.begin(), intRegIds.end());
155
156 // The next batch of the registers are the floating-point physical
157 // registers; put them onto the floating-point free list.
158 for (reg_idx = 0; reg_idx < numPhysicalFloatRegs; reg_idx++) {
159 assert(floatRegIds[reg_idx].index() == reg_idx);
160 }
161 freeList->addRegs(floatRegIds.begin(), floatRegIds.end());
162
163 /* The next batch of the registers are the vector physical
164 * registers; put them onto the vector free list. */
165 for (reg_idx = 0; reg_idx < numPhysicalVecRegs; reg_idx++) {
166 assert(vecRegIds[reg_idx].index() == reg_idx);
167 }
168 freeList->addRegs(vecRegIds.begin(), vecRegIds.end());
169 for (reg_idx = 0; reg_idx < numPhysicalVecElemRegs; reg_idx++) {
170 assert(vecElemIds[reg_idx].index() == reg_idx);
171 }
172 freeList->addRegs(vecElemIds.begin(), vecElemIds.end());
173
174 // The next batch of the registers are the predicate physical
175 // registers; put them onto the predicate free list.
176 for (reg_idx = 0; reg_idx < numPhysicalVecPredRegs; reg_idx++) {
177 assert(vecPredRegIds[reg_idx].index() == reg_idx);
178 }
179 freeList->addRegs(vecPredRegIds.begin(), vecPredRegIds.end());
180
181 /* The next batch of the registers are the matrix physical
182 * registers; put them onto the matrix free list. */
183 for (reg_idx = 0; reg_idx < numPhysicalMatRegs; reg_idx++) {
184 assert(matRegIds[reg_idx].index() == reg_idx);
185 }
186 freeList->addRegs(matRegIds.begin(), matRegIds.end());
187
188 // The rest of the registers are the condition-code physical
189 // registers; put them onto the condition-code free list.
190 for (reg_idx = 0; reg_idx < numPhysicalCCRegs; reg_idx++) {
191 assert(ccRegIds[reg_idx].index() == reg_idx);
192 }
193 freeList->addRegs(ccRegIds.begin(), ccRegIds.end());
194}
195
196} // namespace o3
197} // namespace gem5
std::vector< PhysRegId > vecElemIds
Definition regfile.hh:88
std::vector< PhysRegId > ccRegIds
Definition regfile.hh:100
std::vector< PhysRegId > miscRegIds
Misc Reg Ids.
Definition regfile.hh:103
unsigned numPhysicalVecRegs
Number of physical vector registers.
Definition regfile.hh:118
unsigned numPhysicalCCRegs
Number of physical CC registers.
Definition regfile.hh:138
unsigned numPhysicalMatRegs
Number of physical matrix registers.
Definition regfile.hh:133
unsigned numPhysicalVecPredRegs
Number of physical predicate registers.
Definition regfile.hh:128
PhysRegFile(unsigned _numPhysicalIntRegs, unsigned _numPhysicalFloatRegs, unsigned _numPhysicalVecRegs, unsigned _numPhysicalVecPredRegs, unsigned _numPhysicalMatRegs, unsigned _numPhysicalCCRegs, const BaseISA::RegClasses &classes)
Constructs a physical register file with the specified amount of integer and floating point registers...
Definition regfile.cc:52
std::vector< PhysRegId > floatRegIds
Definition regfile.hh:80
std::vector< PhysRegId > vecRegIds
Definition regfile.hh:84
unsigned numPhysicalVecElemRegs
Number of physical vector element registers.
Definition regfile.hh:123
unsigned numPhysicalFloatRegs
Number of physical floating point registers.
Definition regfile.hh:113
std::vector< PhysRegId > matRegIds
Definition regfile.hh:96
std::vector< PhysRegId > intRegIds
Definition regfile.hh:76
std::vector< PhysRegId > vecPredRegIds
Definition regfile.hh:92
unsigned numPhysicalIntRegs
Number of physical general purpose registers.
Definition regfile.hh:108
void initFreeList(UnifiedFreeList *freeList)
Initialize the free list.
Definition regfile.cc:145
FreeList class that simply holds the list of free integer and floating point registers.
Definition free_list.hh:125
void addRegs(InputIt first, InputIt last)
Adds a register back to the free list.
Definition free_list.hh:167
Bitfield< 35, 32 > at
Bitfield< 30, 0 > index
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
uint16_t RegIndex
Definition types.hh:176
@ VecPredRegClass
Definition reg_class.hh:67
@ MatRegClass
Matrix Register.
Definition reg_class.hh:68
@ FloatRegClass
Floating-point register.
Definition reg_class.hh:62
@ CCRegClass
Condition-code register.
Definition reg_class.hh:69
@ VecRegClass
Vector Register.
Definition reg_class.hh:64
@ IntRegClass
Integer register.
Definition reg_class.hh:61
@ MiscRegClass
Control (misc) register.
Definition reg_class.hh:70
@ VecElemClass
Vector Register Native Elem lane.
Definition reg_class.hh:66

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