29 #ifndef __DEV_NET_SINIC_HH__
30 #define __DEV_NET_SINIC_HH__
42 #include "params/Sinic.hh"
263 void devIntrClear(uint32_t interrupts = registers::Intr_All);
Dummy class to keep the Python class hierarchy in sync with the C++ object hierarchy.
EtherDevBaseParams Params
const std::string & name() const
Return port name (for DPRINTF).
fifo_list::iterator iterator
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Ports are used to interface objects to each other.
void cpuIntrPost(Tick when)
EventFunctionWrapper * intrEvent
void serialize(CheckpointOut &cp) const override
Serialization stuff.
void unserialize(CheckpointIn &cp) override
Unserialize an object.
bool cpuIntrPending() const
PARAMS(Sinic)
Construction/Destruction/Parameters.
EventFunctionWrapper txEvent
void transmit()
Retransmit event.
bool rxFilter(const EthPacketPtr &packet)
receive address filter
void prepareRead(ContextID cpu, int index)
Tick write(PacketPtr pkt) override
IPR read of device register.
PacketFifo::iterator rxFifoPtr
uint32_t & regData32(Addr daddr)
struct gem5::sinic::Device::@314 regs
device register file
void changeConfig(uint32_t newconfig)
device configuration
bool recvPacket(EthPacketPtr packet)
device ethernet interface
void devIntrPost(uint32_t interrupts)
Interrupt management.
EventFunctionWrapper txDmaEvent
void devIntrChangeMask(uint32_t newmask)
void prepareWrite(ContextID cpu, int index)
void rxDmaDone()
DMA parameters.
RxState
Receive State Machine States.
Tick read(PacketPtr pkt) override
Memory Interface.
TxState
Transmit State Machine states.
EventFunctionWrapper rxDmaEvent
void unserialize(CheckpointIn &cp) override
Unserialize an object.
void serialize(CheckpointOut &cp) const override
Serialization stuff.
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
void command(uint32_t command)
void resetStats() override
Callback to reset stats.
std::list< unsigned > VirtualList
uint64_t & regData64(Addr daddr)
virtual void drainResume() override
Resume execution after a successful drain.
gem5::sinic::Device::DeviceStats sinicDeviceStats
std::vector< VirtualReg > VirtualRegs
void prepareIO(ContextID cpu, int index)
uint8_t & regData8(Addr daddr)
void devIntrClear(uint32_t interrupts=registers::Intr_All)
virtual bool recvPacket(EthPacketPtr pkt)
Interface(const std::string &name, Device *d)
This is a simple scalar statistic, like a counter.
Base Ethernet Device declaration.
double Counter
All counters are of 64-bit values.
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
const PortID InvalidPortID
std::ostream CheckpointOut
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
uint64_t Tick
Tick count type.
int ContextID
Globally unique thread context ID.
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi)
std::shared_ptr< EthPacketData > EthPacketPtr
Declaration of Statistics objects.
statistics::Scalar totalVnicDistance
statistics::Scalar maxVnicDistance
statistics::Scalar numVnicDistance
DeviceStats(statistics::Group *parent)
statistics::Formula avgVnicDistance
PacketFifo::iterator rxIndex