gem5  v22.0.0.2
sinic.hh
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1 /*
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3  * All rights reserved.
4  *
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26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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28 
29 #ifndef __DEV_NET_SINIC_HH__
30 #define __DEV_NET_SINIC_HH__
31 
32 #include "base/compiler.hh"
33 #include "base/inet.hh"
34 #include "base/statistics.hh"
35 #include "dev/io_device.hh"
36 #include "dev/net/etherdevice.hh"
37 #include "dev/net/etherint.hh"
38 #include "dev/net/etherpkt.hh"
39 #include "dev/net/pktfifo.hh"
40 #include "dev/net/sinicreg.hh"
41 #include "dev/pci/device.hh"
42 #include "params/Sinic.hh"
43 #include "sim/eventq.hh"
44 
45 namespace gem5
46 {
47 
48 GEM5_DEPRECATED_NAMESPACE(Sinic, sinic);
49 namespace sinic
50 {
51 
52 class Interface;
53 class Base : public EtherDevBase
54 {
55  protected:
56  bool rxEnable;
57  bool txEnable;
58 
59  protected:
64  void cpuIntrPost(Tick when);
65  void cpuInterrupt();
66  void cpuIntrClear();
67 
70 
71  bool cpuIntrPending() const;
72  void cpuIntrAck() { cpuIntrClear(); }
73 
77  public:
78  void serialize(CheckpointOut &cp) const override;
79  void unserialize(CheckpointIn &cp) override;
80 
84  public:
85  PARAMS(Sinic);
86  Base(const Params &p);
87 };
88 
89 class Device : public Base
90 {
91  protected:
93  enum RxState
94  {
100  };
101 
103  enum TxState
104  {
110  };
111 
113  struct
114  {
115  uint32_t Config; // 0x00
116  uint32_t Command; // 0x04
117  uint32_t IntrStatus; // 0x08
118  uint32_t IntrMask; // 0x0c
119  uint32_t RxMaxCopy; // 0x10
120  uint32_t TxMaxCopy; // 0x14
121  uint32_t ZeroCopySize; // 0x18
122  uint32_t ZeroCopyMark; // 0x1c
123  uint32_t VirtualCount; // 0x20
124  uint32_t RxMaxIntr; // 0x24
125  uint32_t RxFifoSize; // 0x28
126  uint32_t TxFifoSize; // 0x2c
127  uint32_t RxFifoLow; // 0x30
128  uint32_t TxFifoLow; // 0x34
129  uint32_t RxFifoHigh; // 0x38
130  uint32_t TxFifoHigh; // 0x3c
131  uint64_t RxData; // 0x40
132  uint64_t RxDone; // 0x48
133  uint64_t RxWait; // 0x50
134  uint64_t TxData; // 0x58
135  uint64_t TxDone; // 0x60
136  uint64_t TxWait; // 0x68
137  uint64_t HwAddr; // 0x70
138  uint64_t RxStatus; // 0x78
139  } regs;
140 
141  struct VirtualReg
142  {
143  uint64_t RxData;
144  uint64_t RxDone;
145  uint64_t TxData;
146  uint64_t TxDone;
147 
149  unsigned rxPacketOffset;
150  unsigned rxPacketBytes;
151  uint64_t rxDoneData;
152 
155 
157  : RxData(0), RxDone(0), TxData(0), TxDone(0),
159  { }
160  };
168  int rxActive;
170 
174 
175  uint8_t &regData8(Addr daddr) { return *((uint8_t *)&regs + daddr); }
176  uint32_t &regData32(Addr daddr) { return *(uint32_t *)&regData8(daddr); }
177  uint64_t &regData64(Addr daddr) { return *(uint64_t *)&regData8(daddr); }
178 
179  protected:
183  bool rxEmpty;
184  bool rxLow;
186  uint8_t *rxDmaData;
187  unsigned rxDmaLen;
188 
191  bool txFull;
196  uint8_t *txDmaData;
197  int txDmaLen;
198 
199  protected:
200  void reset();
201 
202  void rxKick();
204 
205  void txKick();
207 
211  void transmit();
213  {
214  transmit();
215  if (txState == txFifoBlock)
216  txKick();
217  }
219 
220  void txDump() const;
221  void rxDump() const;
222 
226  bool rxFilter(const EthPacketPtr &packet);
227 
231  void changeConfig(uint32_t newconfig);
232  void command(uint32_t command);
233 
237  public:
238  bool recvPacket(EthPacketPtr packet);
239  void transferDone();
240  Port &getPort(const std::string &if_name,
241  PortID idx=InvalidPortID) override;
242 
246  protected:
247  void rxDmaDone();
249 
250  void txDmaDone();
252 
257 
261  protected:
262  void devIntrPost(uint32_t interrupts);
263  void devIntrClear(uint32_t interrupts = registers::Intr_All);
264  void devIntrChangeMask(uint32_t newmask);
265 
269  public:
270  Tick read(PacketPtr pkt) override;
271  Tick write(PacketPtr pkt) override;
272  virtual void drainResume() override;
273 
274  void prepareIO(ContextID cpu, int index);
275  void prepareRead(ContextID cpu, int index);
276  void prepareWrite(ContextID cpu, int index);
277  // Fault iprRead(Addr daddr, ContextID cpu, uint64_t &result);
278 
282  private:
284  {
286 
291 
294 
295 
296  public:
297  void resetStats() override;
298 
302  public:
303  void serialize(CheckpointOut &cp) const override;
304  void unserialize(CheckpointIn &cp) override;
305 
306  public:
307  Device(const Params &p);
308  ~Device();
309 };
310 
311 /*
312  * Ethernet Interface for an Ethernet Device
313  */
314 class Interface : public EtherInt
315 {
316  private:
318 
319  public:
320  Interface(const std::string &name, Device *d)
321  : EtherInt(name), dev(d)
322  { }
323 
324  virtual bool recvPacket(EthPacketPtr pkt) { return dev->recvPacket(pkt); }
325  virtual void sendDone() { dev->transferDone(); }
326 };
327 
328 } // namespace sinic
329 } // namespace gem5
330 
331 #endif // __DEV_NET_SINIC_HH__
gem5::statistics::Scalar
This is a simple scalar statistic, like a counter.
Definition: statistics.hh:1930
gem5::sinic::Device::RxFifoLow
uint32_t RxFifoLow
Definition: sinic.hh:127
gem5::sinic::Device::IntrMask
uint32_t IntrMask
Definition: sinic.hh:118
gem5::PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:245
gem5::EtherDevBase
Dummy class to keep the Python class hierarchy in sync with the C++ object hierarchy.
Definition: etherdevice.hh:143
gem5::sinic::Device::regs
struct gem5::sinic::Device::@309 regs
device register file
gem5::sinic::Device::txEvent
EventFunctionWrapper txEvent
Definition: sinic.hh:218
gem5::sinic::Base::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: sinic.cc:1224
gem5::sinic::Device::rxBeginCopy
@ rxBeginCopy
Definition: sinic.hh:97
gem5::sinic::Base::txEnable
bool txEnable
Definition: sinic.hh:57
io_device.hh
gem5::sinic::Base::cpuIntrPost
void cpuIntrPost(Tick when)
Definition: sinic.cc:475
gem5::sinic::Device::RxStatus
uint64_t RxStatus
Definition: sinic.hh:138
gem5::sinic::Base::PARAMS
PARAMS(Sinic)
Construction/Destruction/Parameters.
gem5::sinic::Device::rxFifo
PacketFifo rxFifo
Definition: sinic.hh:181
gem5::sinic::Device::recvPacket
bool recvPacket(EthPacketPtr packet)
device ethernet interface
Definition: sinic.cc:1150
gem5::sinic::Device::changeConfig
void changeConfig(uint32_t newconfig)
device configuration
Definition: sinic.cc:563
gem5::sinic::Base::cpuPendingIntr
bool cpuPendingIntr
Definition: sinic.hh:63
gem5::sinic::Base::serialize
void serialize(CheckpointOut &cp) const override
Serialization stuff.
Definition: sinic.cc:1203
gem5::sinic::Device::rxCopy
@ rxCopy
Definition: sinic.hh:98
gem5::sinic::Device
Definition: sinic.hh:89
gem5::MipsISA::index
Bitfield< 30, 0 > index
Definition: pra_constants.hh:47
gem5::sinic::Device::TxDone
uint64_t TxDone
Definition: sinic.hh:135
gem5::sinic::Device::DeviceStats::_maxVnicDistance
int _maxVnicDistance
Definition: sinic.hh:292
gem5::sinic::Device::IntrStatus
uint32_t IntrStatus
Definition: sinic.hh:117
gem5::sinic::Device::DeviceStats::DeviceStats
DeviceStats(statistics::Group *parent)
Definition: sinic.cc:104
gem5::sinic::Device::transferDone
void transferDone()
Definition: sinic.cc:1126
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::sinic::Device::VirtualCount
uint32_t VirtualCount
Definition: sinic.hh:123
gem5::sinic::Device::virtualRegs
VirtualRegs virtualRegs
Definition: sinic.hh:165
gem5::sinic::Device::RxMaxCopy
uint32_t RxMaxCopy
Definition: sinic.hh:119
gem5::sinic::Device::TxMaxCopy
uint32_t TxMaxCopy
Definition: sinic.hh:120
etherint.hh
gem5::sinic::Base::cpuIntrClear
void cpuIntrClear()
Definition: sinic.cc:540
gem5::sinic::Interface::recvPacket
virtual bool recvPacket(EthPacketPtr pkt)
Definition: sinic.hh:324
gem5::sinic::Device::reset
void reset()
Definition: sinic.cc:605
gem5::sinic::Device::Device
Device(const Params &p)
Definition: sinic.cc:85
gem5::sinic::Base::cpuIntrEnable
bool cpuIntrEnable
Definition: sinic.hh:62
gem5::sinic::Device::txUnique
Counter txUnique
Definition: sinic.hh:164
gem5::EtherInt::name
const std::string & name() const
Return port name (for DPRINTF).
Definition: etherint.hh:62
gem5::sinic::Device::VirtualReg::txUnique
Counter txUnique
Definition: sinic.hh:154
gem5::sinic::Device::rxEmpty
bool rxEmpty
Definition: sinic.hh:183
gem5::sinic::Device::txCopy
@ txCopy
Definition: sinic.hh:108
gem5::sinic::Device::txPacketOffset
int txPacketOffset
Definition: sinic.hh:193
gem5::sinic::Device::resetStats
void resetStats() override
Callback to reset stats.
Definition: sinic.cc:120
gem5::sinic::Device::dmaReadFactor
Tick dmaReadFactor
Definition: sinic.hh:254
gem5::statistics::Formula
A formula for statistics that is calculated when printed.
Definition: statistics.hh:2539
std::vector< VirtualReg >
gem5::sinic::Device::dmaReadDelay
Tick dmaReadDelay
Definition: sinic.hh:253
gem5::sinic::Device::ZeroCopySize
uint32_t ZeroCopySize
Definition: sinic.hh:121
gem5::sinic::Device::txDmaEvent
EventFunctionWrapper txDmaEvent
Definition: sinic.hh:251
gem5::sinic::Device::HwAddr
uint64_t HwAddr
Definition: sinic.hh:137
gem5::sinic::Device::VirtualRegs
std::vector< VirtualReg > VirtualRegs
Definition: sinic.hh:161
gem5::EtherInt
Definition: etherint.hh:50
gem5::InvalidPortID
const PortID InvalidPortID
Definition: types.hh:246
gem5::sinic::Base::cpuIntrAck
void cpuIntrAck()
Definition: sinic.hh:72
device.hh
gem5::sinic::Device::devIntrClear
void devIntrClear(uint32_t interrupts=registers::Intr_All)
Definition: sinic.cc:441
gem5::sinic::Interface::Interface
Interface(const std::string &name, Device *d)
Definition: sinic.hh:320
gem5::sinic::Device::txDump
void txDump() const
gem5::sinic::Device::DeviceStats::numVnicDistance
statistics::Scalar numVnicDistance
Definition: sinic.hh:288
gem5::sinic::Device::VirtualReg::rxPacketOffset
unsigned rxPacketOffset
Definition: sinic.hh:149
gem5::sinic::Device::TxFifoSize
uint32_t TxFifoSize
Definition: sinic.hh:126
gem5::sinic::Device::TxData
uint64_t TxData
Definition: sinic.hh:134
gem5::sinic::Device::txState
TxState txState
Definition: sinic.hh:189
gem5::sinic::Device::txDmaData
uint8_t * txDmaData
Definition: sinic.hh:196
gem5::sinic::Device::txDmaAddr
Addr txDmaAddr
Definition: sinic.hh:195
gem5::sinic::Device::regData32
uint32_t & regData32(Addr daddr)
Definition: sinic.hh:176
gem5::sinic::Device::rxKickTick
Tick rxKickTick
Definition: sinic.hh:203
gem5::sinic::Device::rxFilter
bool rxFilter(const EthPacketPtr &packet)
receive address filter
Definition: sinic.cc:1139
gem5::sinic::Device::txDmaLen
int txDmaLen
Definition: sinic.hh:197
gem5::sinic::Base::cpuIntrPending
bool cpuIntrPending() const
Definition: sinic.cc:559
gem5::sinic::Device::txIdle
@ txIdle
Definition: sinic.hh:105
gem5::sinic::Device::VirtualReg::rxIndex
PacketFifo::iterator rxIndex
Definition: sinic.hh:148
gem5::sinic::Device::txDmaDone
void txDmaDone()
Definition: sinic.cc:946
gem5::sinic::Device::prepareIO
void prepareIO(ContextID cpu, int index)
Definition: sinic.cc:137
gem5::sinic::Device::TxState
TxState
Transmit State Machine states.
Definition: sinic.hh:103
sinicreg.hh
gem5::sinic::Device::dmaWriteFactor
Tick dmaWriteFactor
Definition: sinic.hh:256
gem5::sinic::Device::drainResume
virtual void drainResume() override
Resume execution after a successful drain.
Definition: sinic.cc:1188
gem5::VegaISA::p
Bitfield< 54 > p
Definition: pagetable.hh:70
gem5::sinic::Device::txBeginCopy
@ txBeginCopy
Definition: sinic.hh:107
gem5::EthPacketPtr
std::shared_ptr< EthPacketData > EthPacketPtr
Definition: etherpkt.hh:90
gem5::sinic::Device::VirtualReg::RxData
uint64_t RxData
Definition: sinic.hh:143
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:291
gem5::ArmISA::d
Bitfield< 9 > d
Definition: misc_types.hh:64
gem5::sinic::Device::RxState
RxState
Receive State Machine States.
Definition: sinic.hh:93
gem5::sinic::Device::sinicDeviceStats
gem5::sinic::Device::DeviceStats sinicDeviceStats
gem5::sinic::Device::rxUnique
Counter rxUnique
Definition: sinic.hh:163
statistics.hh
gem5::sinic::Device::txKick
void txKick()
Definition: sinic.cc:1008
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::sinic::Device::txFifoBlock
@ txFifoBlock
Definition: sinic.hh:106
gem5::sinic::Device::RxFifoHigh
uint32_t RxFifoHigh
Definition: sinic.hh:129
gem5::sinic::Device::VirtualReg
Definition: sinic.hh:141
gem5::sinic::Device::DeviceStats::maxVnicDistance
statistics::Scalar maxVnicDistance
Definition: sinic.hh:289
gem5::sinic::Device::VirtualList
std::list< unsigned > VirtualList
Definition: sinic.hh:162
gem5::sinic::Device::txList
VirtualList txList
Definition: sinic.hh:169
gem5::sinic::Device::rxDump
void rxDump() const
gem5::sinic::Device::~Device
~Device()
Definition: sinic.cc:101
gem5::DmaDevice::Params
DmaDeviceParams Params
Definition: dma_device.hh:209
compiler.hh
gem5::sinic::Device::txPacket
EthPacketPtr txPacket
Definition: sinic.hh:192
gem5::sinic::Device::rxCopyDone
@ rxCopyDone
Definition: sinic.hh:99
gem5::sinic::Device::rxList
VirtualList rxList
Definition: sinic.hh:166
gem5::sinic::Device::TxFifoHigh
uint32_t TxFifoHigh
Definition: sinic.hh:130
gem5::sinic::Base::interface
Interface * interface
Definition: sinic.hh:69
gem5::sinic::Device::rxDmaDone
void rxDmaDone()
DMA parameters.
Definition: sinic.cc:675
gem5::sinic::Device::rxDmaData
uint8_t * rxDmaData
Definition: sinic.hh:186
gem5::sinic::Device::Command
uint32_t Command
Definition: sinic.hh:116
gem5::sinic::Device::Config
uint32_t Config
Definition: sinic.hh:115
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::sinic::Device::devIntrPost
void devIntrPost(uint32_t interrupts)
Interrupt management.
Definition: sinic.cc:405
gem5::sinic::Device::rxKick
void rxKick()
Definition: sinic.cc:691
gem5::sinic::Device::write
Tick write(PacketPtr pkt) override
IPR read of device register.
Definition: sinic.cc:291
gem5::sinic::Device::txFull
bool txFull
Definition: sinic.hh:191
gem5::GEM5_DEPRECATED_NAMESPACE
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi)
gem5::PacketFifo::iterator
fifo_list::iterator iterator
Definition: pktfifo.hh:85
gem5::sinic::Base
Definition: sinic.hh:53
gem5::sinic::Device::rxDmaAddr
Addr rxDmaAddr
Definition: sinic.hh:185
gem5::sinic::Device::TxWait
uint64_t TxWait
Definition: sinic.hh:136
gem5::sinic::Interface::dev
Device * dev
Definition: sinic.hh:317
gem5::sinic::Device::regData8
uint8_t & regData8(Addr daddr)
Definition: sinic.hh:175
gem5::sinic::Device::rxMappedCount
int rxMappedCount
Definition: sinic.hh:172
gem5::sinic::Device::devIntrChangeMask
void devIntrChangeMask(uint32_t newmask)
Definition: sinic.cc:457
gem5::EventFunctionWrapper
Definition: eventq.hh:1115
gem5::sinic::Device::txKickTick
Tick txKickTick
Definition: sinic.hh:206
gem5::sinic::Base::cpuInterrupt
void cpuInterrupt()
Definition: sinic.cc:517
gem5::sinic::Device::rxActive
int rxActive
Definition: sinic.hh:168
gem5::sinic::Device::txCopyDone
@ txCopyDone
Definition: sinic.hh:109
gem5::sinic::Device::rxBusy
VirtualList rxBusy
Definition: sinic.hh:167
gem5::sinic::Device::RxWait
uint64_t RxWait
Definition: sinic.hh:133
gem5::sinic::Device::VirtualReg::TxDone
uint64_t TxDone
Definition: sinic.hh:146
gem5::sinic::Interface
Definition: sinic.hh:314
gem5::sinic::Device::regData64
uint64_t & regData64(Addr daddr)
Definition: sinic.hh:177
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
gem5::sinic::Device::rxLow
bool rxLow
Definition: sinic.hh:184
gem5::sinic::Device::rxState
RxState rxState
Definition: sinic.hh:180
gem5::sinic::Device::read
Tick read(PacketPtr pkt) override
Memory Interface.
Definition: sinic.cc:200
gem5::sinic::Device::TxFifoLow
uint32_t TxFifoLow
Definition: sinic.hh:128
gem5::sinic::Interface::sendDone
virtual void sendDone()
Definition: sinic.hh:325
gem5::ContextID
int ContextID
Globally unique thread context ID.
Definition: types.hh:239
gem5::sinic::Device::ZeroCopyMark
uint32_t ZeroCopyMark
Definition: sinic.hh:122
gem5::sinic::Device::prepareRead
void prepareRead(ContextID cpu, int index)
Definition: sinic.cc:150
gem5::sinic::Device::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: sinic.cc:1363
gem5::sinic::Device::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: sinic.cc:128
gem5::statistics::Counter
double Counter
All counters are of 64-bit values.
Definition: types.hh:47
gem5::sinic::Device::VirtualReg::rxUnique
Counter rxUnique
Definition: sinic.hh:153
gem5::sinic::Device::dmaWriteDelay
Tick dmaWriteDelay
Definition: sinic.hh:255
gem5::sinic::Device::RxData
uint64_t RxData
Definition: sinic.hh:131
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::sinic::Device::rxFifoPtr
PacketFifo::iterator rxFifoPtr
Definition: sinic.hh:182
pktfifo.hh
gem5::sinic::Base::intrTick
Tick intrTick
Definition: sinic.hh:61
etherpkt.hh
gem5::sinic::Device::VirtualReg::RxDone
uint64_t RxDone
Definition: sinic.hh:144
gem5::sinic::Device::prepareWrite
void prepareWrite(ContextID cpu, int index)
Definition: sinic.cc:191
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::sinic::Device::serialize
void serialize(CheckpointOut &cp) const override
Serialization stuff.
Definition: sinic.cc:1248
gem5::sinic::Device::rxFifoBlock
@ rxFifoBlock
Definition: sinic.hh:96
gem5::sinic::Base::intrEvent
EventFunctionWrapper * intrEvent
Definition: sinic.hh:68
etherdevice.hh
gem5::sinic::Device::rxDmaLen
unsigned rxDmaLen
Definition: sinic.hh:187
gem5::sinic::Device::RxDone
uint64_t RxDone
Definition: sinic.hh:132
gem5::sinic::Device::txEventTransmit
void txEventTransmit()
Definition: sinic.hh:212
std::list< unsigned >
gem5::PacketFifo
Definition: pktfifo.hh:80
gem5::sinic::Device::DeviceStats::totalVnicDistance
statistics::Scalar totalVnicDistance
Definition: sinic.hh:287
gem5::sinic::Device::VirtualReg::rxDoneData
uint64_t rxDoneData
Definition: sinic.hh:151
gem5::EtherDevBase::Params
EtherDevBaseParams Params
Definition: etherdevice.hh:146
gem5::sinic::Device::transmit
void transmit()
Retransmit event.
Definition: sinic.cc:962
inet.hh
gem5::sinic::Device::rxBusyCount
int rxBusyCount
Definition: sinic.hh:171
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::sinic::Device::RxFifoSize
uint32_t RxFifoSize
Definition: sinic.hh:125
gem5::sinic::Base::intrDelay
Tick intrDelay
Definition: sinic.hh:60
gem5::sinic::Device::RxMaxIntr
uint32_t RxMaxIntr
Definition: sinic.hh:124
gem5::sinic::Device::rxIdle
@ rxIdle
Definition: sinic.hh:95
gem5::sinic::Device::rxDirtyCount
int rxDirtyCount
Definition: sinic.hh:173
gem5::sinic::Base::Base
Base(const Params &p)
Definition: sinic.cc:78
gem5::sinic::Device::command
void command(uint32_t command)
Definition: sinic.cc:595
gem5::sinic::Device::txPacketBytes
int txPacketBytes
Definition: sinic.hh:194
gem5::sinic::Device::VirtualReg::rxPacketBytes
unsigned rxPacketBytes
Definition: sinic.hh:150
gem5::sinic::Device::VirtualReg::TxData
uint64_t TxData
Definition: sinic.hh:145
gem5::sinic::Device::DeviceStats
Statistics.
Definition: sinic.hh:283
gem5::sinic::Device::rxDmaEvent
EventFunctionWrapper rxDmaEvent
Definition: sinic.hh:248
gem5::sinic::Device::VirtualReg::VirtualReg
VirtualReg()
Definition: sinic.hh:156
gem5::sinic::Device::DeviceStats::avgVnicDistance
statistics::Formula avgVnicDistance
Definition: sinic.hh:290
gem5::sinic::Base::rxEnable
bool rxEnable
Definition: sinic.hh:56
gem5::sinic::Device::txFifo
PacketFifo txFifo
Definition: sinic.hh:190
eventq.hh

Generated on Thu Jul 28 2022 13:32:32 for gem5 by doxygen 1.8.17