#include <sinic.hh>

Inheritance diagram for gem5::sinic::Device:

Classes
struct	DeviceStats
	Statistics. More...

struct	VirtualReg

Public Member Functions
bool	recvPacket (EthPacketPtr packet)
	device ethernet interface More...

void	transferDone ()

Port &	getPort (const std::string &if_name, PortID idx=InvalidPortID) override
	Get a port with a given name and index. More...

Tick	read (PacketPtr pkt) override
	Memory Interface. More...

Tick	write (PacketPtr pkt) override
	IPR read of device register. More...

virtual void	drainResume () override
	Resume execution after a successful drain. More...

void	prepareIO (ContextID cpu, int index)

void	prepareRead (ContextID cpu, int index)

void	prepareWrite (ContextID cpu, int index)

void	resetStats () override
	Callback to reset stats. More...

void	serialize (CheckpointOut &cp) const override
	Serialization stuff. More...

void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...

	Device (const Params &p)

	~Device ()

Public Member Functions inherited from gem5::sinic::Base
	PARAMS (Sinic)
	Construction/Destruction/Parameters. More...

	Base (const Params &p)

Public Member Functions inherited from gem5::EtherDevBase
	EtherDevBase (const Params &params)

Public Member Functions inherited from gem5::EtherDevice
	EtherDevice (const Params &params)

Public Member Functions inherited from gem5::PciDevice
virtual Tick	writeConfig (PacketPtr pkt)
	Write to the PCI config space data that is stored locally. More...

virtual Tick	readConfig (PacketPtr pkt)
	Read from the PCI config space data that is stored locally. More...

Addr	pciToDma (Addr pci_addr) const

void	intrPost ()

void	intrClear ()

uint8_t	interruptLine () const

AddrRangeList	getAddrRanges () const override
	Determine the address ranges that this device responds to. More...

	PciDevice (const PciDeviceParams &params)
	Constructor for PCI Dev. More...

void	serialize (CheckpointOut &cp) const override
	Serialize this object to the given output stream. More...

void	unserialize (CheckpointIn &cp) override
	Reconstruct the state of this object from a checkpoint. More...

const PciBusAddr &	busAddr () const

Public Member Functions inherited from gem5::DmaDevice
	DmaDevice (const Params &p)

virtual	~DmaDevice ()=default

void	dmaWrite (Addr addr, int size, Event event, uint8_t data, uint32_t sid, uint32_t ssid, Tick delay=0)

void	dmaWrite (Addr addr, int size, Event event, uint8_t data, Tick delay=0)

void	dmaRead (Addr addr, int size, Event event, uint8_t data, uint32_t sid, uint32_t ssid, Tick delay=0)

void	dmaRead (Addr addr, int size, Event event, uint8_t data, Tick delay=0)

bool	dmaPending () const

void	init () override
	init() is called after all C++ SimObjects have been created and all ports are connected. More...

unsigned int	cacheBlockSize () const

Public Member Functions inherited from gem5::PioDevice
	PioDevice (const Params &p)

virtual	~PioDevice ()

void	init () override
	init() is called after all C++ SimObjects have been created and all ports are connected. More...

Public Member Functions inherited from gem5::ClockedObject
	ClockedObject (const ClockedObjectParams &p)

void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...

void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...

Public Member Functions inherited from gem5::SimObject
const Params &	params () const

	SimObject (const Params &p)

virtual	~SimObject ()

virtual void	loadState (CheckpointIn &cp)
	loadState() is called on each SimObject when restoring from a checkpoint. More...

virtual void	initState ()
	initState() is called on each SimObject when not restoring from a checkpoint. More...

virtual void	regProbePoints ()
	Register probe points for this object. More...

virtual void	regProbeListeners ()
	Register probe listeners for this object. More...

ProbeManager *	getProbeManager ()
	Get the probe manager for this object. More...

virtual void	startup ()
	startup() is the final initialization call before simulation. More...

DrainState	drain () override
	Provide a default implementation of the drain interface for objects that don't need draining. More...

virtual void	memWriteback ()
	Write back dirty buffers to memory using functional writes. More...

virtual void	memInvalidate ()
	Invalidate the contents of memory buffers. More...

void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...

void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...

Public Member Functions inherited from gem5::EventManager
EventQueue *	eventQueue () const

void	schedule (Event &event, Tick when)

void	deschedule (Event &event)

void	reschedule (Event &event, Tick when, bool always=false)

void	schedule (Event *event, Tick when)

void	deschedule (Event *event)

void	reschedule (Event *event, Tick when, bool always=false)

void	wakeupEventQueue (Tick when=(Tick) -1)
	This function is not needed by the usual gem5 event loop but may be necessary in derived EventQueues which host gem5 on other schedulers. More...

void	setCurTick (Tick newVal)

	EventManager (EventManager &em)
	Event manger manages events in the event queue. More...

	EventManager (EventManager *em)

	EventManager (EventQueue *eq)

Public Member Functions inherited from gem5::Serializable
	Serializable ()

virtual	~Serializable ()

void	serializeSection (CheckpointOut &cp, const char *name) const
	Serialize an object into a new section. More...

void	serializeSection (CheckpointOut &cp, const std::string &name) const

void	unserializeSection (CheckpointIn &cp, const char *name)
	Unserialize an a child object. More...

void	unserializeSection (CheckpointIn &cp, const std::string &name)

Public Member Functions inherited from gem5::Drainable
DrainState	drainState () const
	Return the current drain state of an object. More...

virtual void	notifyFork ()
	Notify a child process of a fork. More...

Public Member Functions inherited from gem5::statistics::Group
	Group (Group parent, const char name=nullptr)
	Construct a new statistics group. More...

virtual	~Group ()

virtual void	regStats ()
	Callback to set stat parameters. More...

virtual void	preDumpStats ()
	Callback before stats are dumped. More...

void	addStat (statistics::Info *info)
	Register a stat with this group. More...

const std::map< std::string, Group * > &	getStatGroups () const
	Get all child groups associated with this object. More...

const std::vector< Info * > &	getStats () const
	Get all stats associated with this object. More...

void	addStatGroup (const char name, Group block)
	Add a stat block as a child of this block. More...

const Info *	resolveStat (std::string name) const
	Resolve a stat by its name within this group. More...

void	mergeStatGroup (Group *block)
	Merge the contents (stats & children) of a block to this block. More...

	Group ()=delete

	Group (const Group &)=delete

Group &	operator= (const Group &)=delete

Public Member Functions inherited from gem5::Named
	Named (const std::string &name_)

virtual	~Named ()=default

virtual std::string	name () const

Public Member Functions inherited from gem5::Clocked
void	updateClockPeriod ()
	Update the tick to the current tick. More...

Tick	clockEdge (Cycles cycles=Cycles(0)) const
	Determine the tick when a cycle begins, by default the current one, but the argument also enables the caller to determine a future cycle. More...

Cycles	curCycle () const
	Determine the current cycle, corresponding to a tick aligned to a clock edge. More...

Tick	nextCycle () const
	Based on the clock of the object, determine the start tick of the first cycle that is at least one cycle in the future. More...

uint64_t	frequency () const

Tick	clockPeriod () const

double	voltage () const

Cycles	ticksToCycles (Tick t) const

Tick	cyclesToTicks (Cycles c) const

Protected Types
enum	RxState { rxIdle , rxFifoBlock , rxBeginCopy , rxCopy , rxCopyDone }
	Receive State Machine States. More...

enum	TxState { txIdle , txFifoBlock , txBeginCopy , txCopy , txCopyDone }
	Transmit State Machine states. More...

typedef std::vector< VirtualReg >	VirtualRegs

typedef std::list< unsigned >	VirtualList

Protected Member Functions
uint8_t &	regData8 (Addr daddr)

uint32_t &	regData32 (Addr daddr)

uint64_t &	regData64 (Addr daddr)

void	reset ()

void	rxKick ()

void	txKick ()

void	transmit ()
	Retransmit event. More...

void	txEventTransmit ()

void	txDump () const

void	rxDump () const

bool	rxFilter (const EthPacketPtr &packet)
	receive address filter More...

void	changeConfig (uint32_t newconfig)
	device configuration More...

void	command (uint32_t command)

void	rxDmaDone ()
	DMA parameters. More...

void	txDmaDone ()

void	devIntrPost (uint32_t interrupts)
	Interrupt management. More...

void	devIntrClear (uint32_t interrupts=registers::Intr_All)

void	devIntrChangeMask (uint32_t newmask)

Protected Member Functions inherited from gem5::sinic::Base
void	cpuIntrPost (Tick when)

void	cpuInterrupt ()

void	cpuIntrClear ()

bool	cpuIntrPending () const

void	cpuIntrAck ()

Protected Member Functions inherited from gem5::PciDevice
bool	getBAR (Addr addr, int &num, Addr &offs)
	Which base address register (if any) maps the given address? More...

Protected Member Functions inherited from gem5::Drainable
	Drainable ()

virtual	~Drainable ()

void	signalDrainDone () const
	Signal that an object is drained. More...

Protected Member Functions inherited from gem5::Clocked
	Clocked (ClockDomain &clk_domain)
	Create a clocked object and set the clock domain based on the parameters. More...

	Clocked (Clocked &)=delete

Clocked &	operator= (Clocked &)=delete

virtual	~Clocked ()
	Virtual destructor due to inheritance. More...

void	resetClock () const
	Reset the object's clock using the current global tick value. More...

virtual void	clockPeriodUpdated ()
	A hook subclasses can implement so they can do any extra work that's needed when the clock rate is changed. More...

Protected Attributes
struct {
uint32_t Config

uint32_t Command

uint32_t IntrStatus

uint32_t IntrMask

uint32_t RxMaxCopy

uint32_t TxMaxCopy

uint32_t ZeroCopySize

uint32_t ZeroCopyMark

uint32_t VirtualCount

uint32_t RxMaxIntr

uint32_t RxFifoSize

uint32_t TxFifoSize

uint32_t RxFifoLow

uint32_t TxFifoLow

uint32_t RxFifoHigh

uint32_t TxFifoHigh

uint64_t RxData

uint64_t RxDone

uint64_t RxWait

uint64_t TxData

uint64_t TxDone

uint64_t TxWait

uint64_t HwAddr

uint64_t RxStatus

}	regs
	device register file More...

Counter	rxUnique

Counter	txUnique

VirtualRegs	virtualRegs

VirtualList	rxList

VirtualList	rxBusy

int	rxActive

VirtualList	txList

int	rxBusyCount

int	rxMappedCount

int	rxDirtyCount

RxState	rxState

PacketFifo	rxFifo

PacketFifo::iterator	rxFifoPtr

bool	rxEmpty

bool	rxLow

Addr	rxDmaAddr

uint8_t *	rxDmaData

unsigned	rxDmaLen

TxState	txState

PacketFifo	txFifo

bool	txFull

EthPacketPtr	txPacket

int	txPacketOffset

int	txPacketBytes

Addr	txDmaAddr

uint8_t *	txDmaData

int	txDmaLen

Tick	rxKickTick

Tick	txKickTick

EventFunctionWrapper	txEvent

EventFunctionWrapper	rxDmaEvent

EventFunctionWrapper	txDmaEvent

Tick	dmaReadDelay

Tick	dmaReadFactor

Tick	dmaWriteDelay

Tick	dmaWriteFactor

Protected Attributes inherited from gem5::sinic::Base
bool	rxEnable

bool	txEnable

Tick	intrDelay

Tick	intrTick

bool	cpuIntrEnable

bool	cpuPendingIntr

EventFunctionWrapper *	intrEvent

Interface *	interface

Protected Attributes inherited from gem5::EtherDevice
gem5::EtherDevice::EtherDeviceStats	etherDeviceStats

Protected Attributes inherited from gem5::PciDevice
const PciBusAddr	_busAddr

PCIConfig	config
	The current config space. More...

std::vector< MSIXTable >	msix_table
	MSIX Table and PBA Structures. More...

std::vector< MSIXPbaEntry >	msix_pba

std::array< PciBar *, 6 >	BARs {}

PciHost::DeviceInterface	hostInterface

Tick	pioDelay

Tick	configDelay

const int	PMCAP_BASE
	The capability list structures and base addresses. More...

const int	PMCAP_ID_OFFSET

const int	PMCAP_PC_OFFSET

const int	PMCAP_PMCS_OFFSET

PMCAP	pmcap

const int	MSICAP_BASE

MSICAP	msicap

const int	MSIXCAP_BASE

const int	MSIXCAP_ID_OFFSET

const int	MSIXCAP_MXC_OFFSET

const int	MSIXCAP_MTAB_OFFSET

const int	MSIXCAP_MPBA_OFFSET

int	MSIX_TABLE_OFFSET

int	MSIX_TABLE_END

int	MSIX_PBA_OFFSET

int	MSIX_PBA_END

MSIXCAP	msixcap

const int	PXCAP_BASE

PXCAP	pxcap

Protected Attributes inherited from gem5::DmaDevice
DmaPort	dmaPort

Protected Attributes inherited from gem5::PioDevice
System *	sys

PioPort< PioDevice >	pioPort
	The pioPort that handles the requests for us and provides us requests that it sees. More...

Protected Attributes inherited from gem5::SimObject
const SimObjectParams &	_params
	Cached copy of the object parameters. More...

Protected Attributes inherited from gem5::EventManager
EventQueue *	eventq
	A pointer to this object's event queue. More...

Private Attributes
gem5::sinic::Device::DeviceStats	sinicDeviceStats

Additional Inherited Members
Public Types inherited from gem5::EtherDevBase
using	Params = EtherDevBaseParams

Public Types inherited from gem5::EtherDevice
using	Params = EtherDeviceParams

Public Types inherited from gem5::DmaDevice
typedef DmaDeviceParams	Params

Public Types inherited from gem5::PioDevice
using	Params = PioDeviceParams

Public Types inherited from gem5::ClockedObject
using	Params = ClockedObjectParams
	Parameters of ClockedObject. More...

Public Types inherited from gem5::SimObject
typedef SimObjectParams	Params

Static Public Member Functions inherited from gem5::SimObject
static void	serializeAll (const std::string &cpt_dir)
	Create a checkpoint by serializing all SimObjects in the system. More...

static SimObject *	find (const char *name)
	Find the SimObject with the given name and return a pointer to it. More...

static void	setSimObjectResolver (SimObjectResolver *resolver)
	There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. More...

static SimObjectResolver *	getSimObjectResolver ()
	There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. More...

Static Public Member Functions inherited from gem5::Serializable
static const std::string &	currentSection ()
	Gets the fully-qualified name of the active section. More...

static void	generateCheckpointOut (const std::string &cpt_dir, std::ofstream &outstream)
	Generate a checkpoint file so that the serialization can be routed to it. More...

Public Attributes inherited from gem5::ClockedObject
PowerState *	powerState

Detailed Description

Definition at line 89 of file sinic.hh.

Member Typedef Documentation

◆ VirtualList

typedef std::list<unsigned> gem5::sinic::Device::VirtualList

protected

Definition at line 162 of file sinic.hh.

◆ VirtualRegs

typedef std::vector<VirtualReg> gem5::sinic::Device::VirtualRegs

protected

Definition at line 161 of file sinic.hh.

Member Enumeration Documentation

◆ RxState

enum gem5::sinic::Device::RxState

protected

Receive State Machine States.

Enumerator
rxIdle
rxFifoBlock
rxBeginCopy
rxCopy
rxCopyDone

Definition at line 93 of file sinic.hh.

◆ TxState

enum gem5::sinic::Device::TxState

protected

Transmit State Machine states.

Enumerator
txIdle
txFifoBlock
txBeginCopy
txCopy
txCopyDone

Definition at line 103 of file sinic.hh.

Constructor & Destructor Documentation

◆ Device()

gem5::sinic::Device::Device ( const Params & p )

Definition at line 85 of file sinic.cc.

References txEventTransmit().

◆ ~Device()

gem5::sinic::Device::~Device ( )

Definition at line 101 of file sinic.cc.

Member Function Documentation

◆ changeConfig()

void gem5::sinic::Device::changeConfig ( uint32_t newconfig )

protected

device configuration

Definition at line 563 of file sinic.cc.

References gem5::sinic::Base::cpuIntrClear(), gem5::sinic::Base::cpuIntrEnable, gem5::sinic::Base::cpuIntrPost(), gem5::curTick(), regs, gem5::sinic::Base::rxEnable, rxKick(), gem5::sinic::Base::txEnable, and txKick().

Referenced by write().

◆ command()

void gem5::sinic::Device::command ( uint32_t command )

protected

Definition at line 595 of file sinic.cc.

References devIntrPost(), and reset().

Referenced by write().

◆ devIntrChangeMask()

void gem5::sinic::Device::devIntrChangeMask ( uint32_t newmask )

protected

Definition at line 457 of file sinic.cc.

References gem5::sinic::Base::cpuIntrClear(), gem5::sinic::Base::cpuIntrPost(), gem5::curTick(), DPRINTF, and regs.

Referenced by write().

◆ devIntrClear()

void gem5::sinic::Device::devIntrClear ( uint32_t interrupts = registers::Intr_All )

protected

Definition at line 441 of file sinic.cc.

References gem5::sinic::Base::cpuIntrClear(), DPRINTF, panic, and regs.

Referenced by read(), and write().

◆ devIntrPost()

void gem5::sinic::Device::devIntrPost ( uint32_t interrupts )

protected

Interrupt management.

Definition at line 405 of file sinic.cc.

References gem5::sinic::Base::cpuIntrPost(), gem5::curTick(), DPRINTF, gem5::sinic::Base::intrDelay, panic, regs, rxEmpty, and txFull.

Referenced by command(), recvPacket(), rxKick(), transmit(), and txKick().

◆ drainResume()

void gem5::sinic::Device::drainResume ( )

overridevirtual

Resume execution after a successful drain.

Reimplemented from gem5::Drainable.

Definition at line 1188 of file sinic.cc.

References gem5::Drainable::drainResume(), rxKick(), and txKick().

◆ getPort()

Port & gem5::sinic::Device::getPort	(	const std::string &	if_name,
		PortID	idx = `InvalidPortID`
	)

overridevirtual

Get a port with a given name and index.

This is used at binding time and returns a reference to a protocol-agnostic port.

gem5 has a request and response port interface. All memory objects are connected together via ports. These ports provide a rigid interface between these memory objects. These ports implement three different memory system modes: timing, atomic, and functional. The most important mode is the timing mode and here timing mode is used for conducting cycle-level timing experiments. The other modes are only used in special circumstances and should not be used to conduct cycle-level timing experiments. The other modes are only used in special circumstances. These ports allow SimObjects to communicate with each other.

Parameters

if_name	Port name
idx	Index in the case of a VectorPort

Returns: A reference to the given port

Reimplemented from gem5::DmaDevice.

Definition at line 128 of file sinic.cc.

References gem5::DmaDevice::getPort(), and gem5::sinic::Base::interface.

◆ prepareIO()

void gem5::sinic::Device::prepareIO	(	ContextID	cpu,
		int	index
	)

Definition at line 137 of file sinic.cc.

References gem5::MipsISA::index, panic, and virtualRegs.

Referenced by prepareRead(), and prepareWrite().

◆ prepareRead()

void gem5::sinic::Device::prepareRead	(	ContextID	cpu,
		int	index
	)

◆ prepareWrite()

void gem5::sinic::Device::prepareWrite	(	ContextID	cpu,
		int	index
	)

Definition at line 191 of file sinic.cc.

References gem5::MipsISA::index, and prepareIO().

Referenced by write().

◆ read()

Tick gem5::sinic::Device::read ( PacketPtr pkt )

overridevirtual

Memory Interface.

I/O read of device register.

Implements gem5::PioDevice.

Definition at line 200 of file sinic.cc.

References gem5::PciDevice::BARs, gem5::PciDevice::config, devIntrClear(), DPRINTF, gem5::Packet::getAddr(), gem5::Packet::getSize(), gem5::MipsISA::index, gem5::sinic::registers::Info::name, panic, PCI_CMD_MSE, gem5::PciDevice::pioDelay, prepareRead(), gem5::sinic::registers::Info::read, gem5::X86ISA::reg, regData32(), regData64(), gem5::sinic::regInfo(), gem5::sinic::regValid(), gem5::Packet::req, gem5::Packet::setLE(), gem5::sinic::registers::Info::size, gem5::sinic::registers::VirtualMask, and gem5::sinic::registers::VirtualShift.

◆ recvPacket()

bool gem5::sinic::Device::recvPacket ( EthPacketPtr packet )

device ethernet interface

Definition at line 1150 of file sinic.cc.

References gem5::PacketFifo::avail(), devIntrPost(), DPRINTF, gem5::PacketFifo::end(), gem5::EtherDevice::etherDeviceStats, gem5::PacketFifo::push(), regs, gem5::EtherDevice::EtherDeviceStats::rxBytes, gem5::sinic::Base::rxEnable, rxFifo, rxFifoPtr, rxFilter(), rxKick(), gem5::EtherDevice::EtherDeviceStats::rxPackets, and gem5::PacketFifo::size().

Referenced by gem5::sinic::Interface::recvPacket().

◆ regData32()

uint32_t& gem5::sinic::Device::regData32 ( Addr daddr )

inlineprotected

Definition at line 176 of file sinic.hh.

References regData8().

Referenced by read().

◆ regData64()

uint64_t& gem5::sinic::Device::regData64 ( Addr daddr )

inlineprotected

Definition at line 177 of file sinic.hh.

References regData8().

Referenced by read().

◆ regData8()

uint8_t& gem5::sinic::Device::regData8 ( Addr daddr )

inlineprotected

Definition at line 175 of file sinic.hh.

References regs.

Referenced by regData32(), and regData64().

◆ reset()

void gem5::sinic::Device::reset ( )

protected

Definition at line 605 of file sinic.cc.

References gem5::PacketFifo::clear(), gem5::PacketFifo::end(), gem5::ArmISA::i, panic, gem5::SimObject::params(), regs, rxActive, rxBusy, rxBusyCount, rxDirtyCount, rxEmpty, rxFifo, rxFifoPtr, rxIdle, rxList, rxLow, rxMappedCount, rxState, txFifo, txFull, txIdle, txList, txState, and virtualRegs.

Referenced by command().

◆ resetStats()

void gem5::sinic::Device::resetStats ( )

overridevirtual

Callback to reset stats.

Reimplemented from gem5::statistics::Group.

Definition at line 120 of file sinic.cc.

References gem5::sinic::Device::DeviceStats::_maxVnicDistance, gem5::statistics::Group::resetStats(), and sinicDeviceStats.

◆ rxDmaDone()

void gem5::sinic::Device::rxDmaDone ( )

protected

DMA parameters.

Definition at line 675 of file sinic.cc.

References DDUMP, DPRINTF, rxCopy, rxCopyDone, rxDmaAddr, rxDmaData, rxDmaLen, rxKick(), rxState, txBeginCopy, txKick(), and txState.

◆ rxDump()

void gem5::sinic::Device::rxDump ( ) const

protected

◆ rxFilter()

bool gem5::sinic::Device::rxFilter ( const EthPacketPtr & packet )

protected

receive address filter

Definition at line 1139 of file sinic.cc.

References panic, and regs.

Referenced by recvPacket().

◆ rxKick()

void gem5::sinic::Device::rxKick ( )

protected

Todo:: do we want to schedule a future kick?

Definition at line 691 of file sinic.cc.

Referenced by changeConfig(), drainResume(), recvPacket(), rxDmaDone(), txDmaDone(), and write().

◆ serialize()

void gem5::sinic::Device::serialize ( CheckpointOut & cp ) const

overridevirtual

Serialization stuff.

Reimplemented from gem5::sinic::Base.

Definition at line 1248 of file sinic.cc.

◆ transferDone()

void gem5::sinic::Device::transferDone ( )

Definition at line 1126 of file sinic.cc.

References gem5::Clocked::clockEdge(), DPRINTF, gem5::PacketFifo::empty(), gem5::EventManager::reschedule(), txEvent, and txFifo.

Referenced by gem5::sinic::Interface::sendDone().

◆ transmit()

void gem5::sinic::Device::transmit ( )

protected

Retransmit event.

Definition at line 962 of file sinic.cc.

References gem5::PacketFifo::avail(), DDUMP, devIntrPost(), DPRINTF, gem5::PacketFifo::empty(), gem5::EtherDevice::etherDeviceStats, gem5::PacketFifo::front(), gem5::sinic::Base::interface, gem5::igbreg::txd_op::ip(), gem5::PacketFifo::pop(), regs, gem5::EtherInt::sendPacket(), gem5::PacketFifo::size(), gem5::igbreg::txd_op::tcp(), gem5::EtherDevice::EtherDeviceStats::txBytes, txFifo, and gem5::EtherDevice::EtherDeviceStats::txPackets.

Referenced by txEventTransmit(), and txKick().

◆ txDmaDone()

void gem5::sinic::Device::txDmaDone ( )

protected

Definition at line 946 of file sinic.cc.

References DDUMP, DPRINTF, rxBeginCopy, rxKick(), rxState, txCopy, txCopyDone, txDmaAddr, txDmaData, txDmaLen, txKick(), and txState.

◆ txDump()

void gem5::sinic::Device::txDump ( ) const

protected

◆ txEventTransmit()

void gem5::sinic::Device::txEventTransmit ( )

inlineprotected

Definition at line 212 of file sinic.hh.

References transmit(), txFifoBlock, txKick(), and txState.

Referenced by Device().

◆ txKick()

void gem5::sinic::Device::txKick ( )

protected

Todo:: do we want to schedule a future kick?

Definition at line 1008 of file sinic.cc.

References gem5::PacketFifo::avail(), gem5::networking::cksum(), gem5::curTick(), devIntrPost(), gem5::DmaDevice::dmaPending(), gem5::DmaDevice::dmaRead(), DPRINTF, gem5::Drainable::drainState(), gem5::EtherDevice::etherDeviceStats, gem5::X86ISA::exit, gem5::igbreg::txd_op::ip(), panic, gem5::PciDevice::pciToDma(), gem5::PacketFifo::push(), regs, gem5::Running, gem5::PacketFifo::size(), gem5::networking::UdpHdr::sum(), gem5::igbreg::txd_op::tcp(), transmit(), txBeginCopy, txCopy, txCopyDone, gem5::sinic::Device::VirtualReg::TxData, txDmaAddr, txDmaData, txDmaEvent, txDmaLen, gem5::sinic::Device::VirtualReg::TxDone, txFifo, txFifoBlock, txFull, txIdle, gem5::EtherDevice::EtherDeviceStats::txIpChecksums, txKickTick, txList, txPacket, txPacketOffset, txState, gem5::sinic::TxStateStrings, gem5::EtherDevice::EtherDeviceStats::txTcpChecksums, gem5::EtherDevice::EtherDeviceStats::txUdpChecksums, and virtualRegs.

Referenced by changeConfig(), drainResume(), rxDmaDone(), txDmaDone(), txEventTransmit(), and write().

◆ unserialize()

void gem5::sinic::Device::unserialize ( CheckpointIn & cp )

overridevirtual

Unserialize an object.

Read an object's state from the current checkpoint section.

Parameters

cp	Checkpoint state

Reimplemented from gem5::sinic::Base.

Definition at line 1363 of file sinic.cc.

◆ write()

Tick gem5::sinic::Device::write ( PacketPtr pkt )

overridevirtual

IPR read of device register.

Fault Device::iprRead(Addr daddr, ContextID cpu, uint64_t &result) { if (!regValid(daddr)) panic("invalid address: da=%#x", daddr);

const registers::Info &info = regInfo(daddr); if (!info.read) panic("reading %s (write only): cpu=%d da=%#x", info.name, cpu, daddr);

DPRINTF(EthernetPIO, "IPR read %s: cpu=%d da=%#x\n", info.name, cpu, daddr);

prepareRead(cpu, 0);

if (info.size == 4) result = regData32(daddr);

if (info.size == 8) result = regData64(daddr);

DPRINTF(EthernetPIO, "IPR read %s: cpu=%s da=%#x val=%#x\n", info.name, cpu, result);

return NoFault; } I/O write of device register

Implements gem5::PioDevice.

Definition at line 291 of file sinic.cc.

References gem5::PciDevice::BARs, changeConfig(), command(), gem5::MipsISA::misc_reg::Config, gem5::PciDevice::config, devIntrChangeMask(), devIntrClear(), DPRINTF, gem5::PacketFifo::end(), gem5::Packet::getAddr(), gem5::Packet::getLE(), gem5::Packet::getSize(), gem5::MipsISA::index, gem5::sinic::registers::Info::name, panic, PCI_CMD_MSE, gem5::PciDevice::pioDelay, prepareWrite(), gem5::sinic::regInfo(), regs, gem5::sinic::regValid(), gem5::Packet::req, rxBusy, rxBusyCount, gem5::sinic::Device::VirtualReg::RxData, gem5::sinic::Device::VirtualReg::RxDone, gem5::sinic::Base::rxEnable, rxFifo, rxFifoBlock, rxIdle, gem5::sinic::Device::VirtualReg::rxIndex, rxKick(), rxList, rxState, gem5::sinic::RxStateStrings, gem5::sinic::Device::VirtualReg::rxUnique, rxUnique, gem5::sinic::registers::Info::size, gem5::sinic::Device::VirtualReg::TxDone, gem5::sinic::Base::txEnable, txFifoBlock, txIdle, txKick(), txList, txState, gem5::sinic::TxStateStrings, gem5::sinic::Device::VirtualReg::txUnique, txUnique, gem5::sinic::registers::VirtualMask, virtualRegs, gem5::sinic::registers::VirtualShift, and gem5::sinic::registers::Info::write.

Member Data Documentation

◆ Command

uint32_t gem5::sinic::Device::Command

Definition at line 116 of file sinic.hh.

◆ Config

uint32_t gem5::sinic::Device::Config

Definition at line 115 of file sinic.hh.

◆ dmaReadDelay

Tick gem5::sinic::Device::dmaReadDelay

protected

Definition at line 253 of file sinic.hh.

◆ dmaReadFactor

Tick gem5::sinic::Device::dmaReadFactor

protected

Definition at line 254 of file sinic.hh.

◆ dmaWriteDelay

Tick gem5::sinic::Device::dmaWriteDelay

protected

Definition at line 255 of file sinic.hh.

◆ dmaWriteFactor

Tick gem5::sinic::Device::dmaWriteFactor

protected

Definition at line 256 of file sinic.hh.

◆ HwAddr

uint64_t gem5::sinic::Device::HwAddr

Definition at line 137 of file sinic.hh.

◆ IntrMask

uint32_t gem5::sinic::Device::IntrMask

Definition at line 118 of file sinic.hh.

◆ IntrStatus

uint32_t gem5::sinic::Device::IntrStatus

Definition at line 117 of file sinic.hh.

◆

struct { ... } gem5::sinic::Device::regs

device register file

Referenced by changeConfig(), devIntrChangeMask(), devIntrClear(), devIntrPost(), prepareRead(), recvPacket(), regData8(), reset(), rxFilter(), rxKick(), serialize(), transmit(), txKick(), unserialize(), and write().

◆ rxActive

int gem5::sinic::Device::rxActive

protected

Definition at line 168 of file sinic.hh.

Referenced by reset(), rxKick(), serialize(), and unserialize().

◆ rxBusy

VirtualList gem5::sinic::Device::rxBusy

protected

Definition at line 167 of file sinic.hh.

Referenced by reset(), rxKick(), serialize(), unserialize(), and write().

◆ rxBusyCount

int gem5::sinic::Device::rxBusyCount

protected

Definition at line 171 of file sinic.hh.

Referenced by prepareRead(), reset(), rxKick(), serialize(), unserialize(), and write().

◆ RxData

uint64_t gem5::sinic::Device::RxData

Definition at line 131 of file sinic.hh.

◆ rxDirtyCount

int gem5::sinic::Device::rxDirtyCount

protected

Definition at line 173 of file sinic.hh.

Referenced by prepareRead(), reset(), rxKick(), serialize(), and unserialize().

◆ rxDmaAddr

Addr gem5::sinic::Device::rxDmaAddr

protected

Definition at line 185 of file sinic.hh.

Referenced by rxDmaDone(), and rxKick().

◆ rxDmaData

uint8_t* gem5::sinic::Device::rxDmaData

protected

Definition at line 186 of file sinic.hh.

Referenced by rxDmaDone(), and rxKick().

◆ rxDmaEvent

EventFunctionWrapper gem5::sinic::Device::rxDmaEvent

protected

Definition at line 248 of file sinic.hh.

Referenced by rxKick().

◆ rxDmaLen

unsigned gem5::sinic::Device::rxDmaLen

protected

Definition at line 187 of file sinic.hh.

Referenced by rxDmaDone(), and rxKick().

◆ RxDone

uint64_t gem5::sinic::Device::RxDone

Definition at line 132 of file sinic.hh.

◆ rxEmpty

bool gem5::sinic::Device::rxEmpty

protected

Definition at line 183 of file sinic.hh.

Referenced by devIntrPost(), reset(), rxKick(), serialize(), and unserialize().

◆ rxFifo

PacketFifo gem5::sinic::Device::rxFifo

protected

Definition at line 181 of file sinic.hh.

Referenced by prepareRead(), recvPacket(), reset(), rxKick(), serialize(), unserialize(), and write().

◆ RxFifoHigh

uint32_t gem5::sinic::Device::RxFifoHigh

Definition at line 129 of file sinic.hh.

◆ RxFifoLow

uint32_t gem5::sinic::Device::RxFifoLow

Definition at line 127 of file sinic.hh.

◆ rxFifoPtr

PacketFifo::iterator gem5::sinic::Device::rxFifoPtr

protected

Definition at line 182 of file sinic.hh.

Referenced by prepareRead(), recvPacket(), reset(), rxKick(), serialize(), and unserialize().

◆ RxFifoSize

uint32_t gem5::sinic::Device::RxFifoSize

Definition at line 125 of file sinic.hh.

◆ rxKickTick

Tick gem5::sinic::Device::rxKickTick

protected

Definition at line 203 of file sinic.hh.

Referenced by rxKick().

◆ rxList

VirtualList gem5::sinic::Device::rxList

protected

Definition at line 166 of file sinic.hh.

Referenced by reset(), rxKick(), serialize(), unserialize(), and write().

◆ rxLow

bool gem5::sinic::Device::rxLow

protected

Definition at line 184 of file sinic.hh.

Referenced by prepareRead(), reset(), rxKick(), serialize(), and unserialize().

◆ rxMappedCount

int gem5::sinic::Device::rxMappedCount

protected

Definition at line 172 of file sinic.hh.

Referenced by prepareRead(), reset(), rxKick(), serialize(), and unserialize().

◆ RxMaxCopy

uint32_t gem5::sinic::Device::RxMaxCopy

Definition at line 119 of file sinic.hh.

◆ RxMaxIntr

uint32_t gem5::sinic::Device::RxMaxIntr

Definition at line 124 of file sinic.hh.

◆ rxState

RxState gem5::sinic::Device::rxState

protected

Definition at line 180 of file sinic.hh.

Referenced by reset(), rxDmaDone(), rxKick(), serialize(), txDmaDone(), unserialize(), and write().

◆ RxStatus

uint64_t gem5::sinic::Device::RxStatus

Definition at line 138 of file sinic.hh.

◆ rxUnique

Counter gem5::sinic::Device::rxUnique

protected

Definition at line 163 of file sinic.hh.

Referenced by unserialize(), and write().

◆ RxWait

uint64_t gem5::sinic::Device::RxWait

Definition at line 133 of file sinic.hh.

◆ sinicDeviceStats

gem5::sinic::Device::DeviceStats gem5::sinic::Device::sinicDeviceStats

private

Referenced by resetStats(), and rxKick().

◆ TxData

uint64_t gem5::sinic::Device::TxData

Definition at line 134 of file sinic.hh.

◆ txDmaAddr

Addr gem5::sinic::Device::txDmaAddr

protected

Definition at line 195 of file sinic.hh.

Referenced by txDmaDone(), and txKick().

◆ txDmaData

uint8_t* gem5::sinic::Device::txDmaData

protected

Definition at line 196 of file sinic.hh.

Referenced by txDmaDone(), and txKick().

◆ txDmaEvent

EventFunctionWrapper gem5::sinic::Device::txDmaEvent

protected

Definition at line 251 of file sinic.hh.

Referenced by txKick().

◆ txDmaLen

int gem5::sinic::Device::txDmaLen

protected

Definition at line 197 of file sinic.hh.

Referenced by txDmaDone(), and txKick().

◆ TxDone

uint64_t gem5::sinic::Device::TxDone

Definition at line 135 of file sinic.hh.

◆ txEvent

EventFunctionWrapper gem5::sinic::Device::txEvent

protected

Definition at line 218 of file sinic.hh.

Referenced by serialize(), transferDone(), and unserialize().

◆ txFifo

PacketFifo gem5::sinic::Device::txFifo

protected

Definition at line 190 of file sinic.hh.

Referenced by prepareRead(), reset(), serialize(), transferDone(), transmit(), txKick(), and unserialize().

◆ TxFifoHigh

uint32_t gem5::sinic::Device::TxFifoHigh

Definition at line 130 of file sinic.hh.

◆ TxFifoLow

uint32_t gem5::sinic::Device::TxFifoLow

Definition at line 128 of file sinic.hh.

◆ TxFifoSize

uint32_t gem5::sinic::Device::TxFifoSize

Definition at line 126 of file sinic.hh.

◆ txFull

bool gem5::sinic::Device::txFull

protected

Definition at line 191 of file sinic.hh.

Referenced by devIntrPost(), reset(), serialize(), txKick(), and unserialize().

◆ txKickTick

Tick gem5::sinic::Device::txKickTick

protected

Definition at line 206 of file sinic.hh.

Referenced by txKick().

◆ txList

VirtualList gem5::sinic::Device::txList

protected

Definition at line 169 of file sinic.hh.

Referenced by reset(), serialize(), txKick(), unserialize(), and write().

◆ TxMaxCopy

uint32_t gem5::sinic::Device::TxMaxCopy

Definition at line 120 of file sinic.hh.

◆ txPacket

EthPacketPtr gem5::sinic::Device::txPacket

protected

Definition at line 192 of file sinic.hh.

Referenced by serialize(), txKick(), and unserialize().

◆ txPacketBytes

int gem5::sinic::Device::txPacketBytes

protected

Definition at line 194 of file sinic.hh.

Referenced by serialize(), and unserialize().

◆ txPacketOffset

int gem5::sinic::Device::txPacketOffset

protected

Definition at line 193 of file sinic.hh.

Referenced by serialize(), txKick(), and unserialize().

◆ txState

TxState gem5::sinic::Device::txState

protected

Definition at line 189 of file sinic.hh.

Referenced by reset(), rxDmaDone(), serialize(), txDmaDone(), txEventTransmit(), txKick(), unserialize(), and write().

◆ txUnique

Counter gem5::sinic::Device::txUnique

protected

Definition at line 164 of file sinic.hh.

Referenced by unserialize(), and write().

◆ TxWait

uint64_t gem5::sinic::Device::TxWait

Definition at line 136 of file sinic.hh.

◆ VirtualCount

uint32_t gem5::sinic::Device::VirtualCount

Definition at line 123 of file sinic.hh.

◆ virtualRegs

VirtualRegs gem5::sinic::Device::virtualRegs

protected

Definition at line 165 of file sinic.hh.

Referenced by prepareIO(), prepareRead(), reset(), rxKick(), serialize(), txKick(), unserialize(), and write().

◆ ZeroCopyMark

uint32_t gem5::sinic::Device::ZeroCopyMark

Definition at line 122 of file sinic.hh.

◆ ZeroCopySize

uint32_t gem5::sinic::Device::ZeroCopySize

Definition at line 121 of file sinic.hh.

The documentation for this class was generated from the following files:

dev/net/sinic.hh
dev/net/sinic.cc

Classes

Public Member Functions

Protected Types

Protected Member Functions

Protected Attributes

Private Attributes

Additional Inherited Members

Detailed Description

Member Typedef Documentation

◆ VirtualList

◆ VirtualRegs

Member Enumeration Documentation

◆ RxState

◆ TxState

Constructor & Destructor Documentation

◆ Device()

◆ ~Device()

Member Function Documentation

◆ changeConfig()

◆ command()

◆ devIntrChangeMask()

◆ devIntrClear()

◆ devIntrPost()

◆ drainResume()

◆ getPort()

◆ prepareIO()

◆ prepareRead()

◆ prepareWrite()

◆ read()

◆ recvPacket()

◆ regData32()

◆ regData64()

◆ regData8()

◆ reset()

◆ resetStats()

◆ rxDmaDone()

◆ rxDump()

◆ rxFilter()

◆ rxKick()

◆ serialize()

◆ transferDone()

◆ transmit()

◆ txDmaDone()

◆ txDump()

◆ txEventTransmit()

◆ txKick()

◆ unserialize()

◆ write()

Member Data Documentation

◆ Command

◆ Config

◆ dmaReadDelay

◆ dmaReadFactor

◆ dmaWriteDelay

◆ dmaWriteFactor

◆ HwAddr

◆ IntrMask

◆ IntrStatus

◆

◆ rxActive

◆ rxBusy

◆ rxBusyCount

◆ RxData

◆ rxDirtyCount

◆ rxDmaAddr

◆ rxDmaData

◆ rxDmaEvent

◆ rxDmaLen

◆ RxDone

◆ rxEmpty

◆ rxFifo

◆ RxFifoHigh

◆ RxFifoLow

◆ rxFifoPtr

◆ RxFifoSize

◆ rxKickTick

◆ rxList

◆ rxLow

◆ rxMappedCount

◆ RxMaxCopy