gem5  v21.1.0.2
standard.hh
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30 
31 #ifndef __ARCH_RISCV_STANDARD_INST_HH__
32 #define __ARCH_RISCV_STANDARD_INST_HH__
33 
34 #include <string>
35 
38 #include "arch/riscv/regs/misc.hh"
39 #include "cpu/exec_context.hh"
40 #include "cpu/static_inst.hh"
41 
42 namespace gem5
43 {
44 
45 namespace RiscvISA
46 {
47 
51 class RegOp : public RiscvStaticInst
52 {
53  protected:
55 
56  std::string generateDisassembly(
57  Addr pc, const loader::SymbolTable *symtab) const override;
58 };
59 
63 template<typename I>
64 class ImmOp : public RiscvStaticInst
65 {
66  protected:
67  I imm;
68 
69  ImmOp(const char *mnem, MachInst _machInst, OpClass __opClass)
70  : RiscvStaticInst(mnem, _machInst, __opClass), imm(0)
71  {}
72 };
73 
77 class SystemOp : public RiscvStaticInst
78 {
79  protected:
81 
82  std::string generateDisassembly(
83  Addr pc, const loader::SymbolTable *symtab) const override;
84 };
85 
89 class CSROp : public RiscvStaticInst
90 {
91  protected:
92  uint64_t csr;
93  uint64_t uimm;
94 
95  bool valid = false;
97  std::string csrName;
98  uint64_t maskVal = 0;
99 
101  CSROp(const char *mnem, MachInst _machInst, OpClass __opClass)
102  : RiscvStaticInst(mnem, _machInst, __opClass),
104  {
105  auto csr_data_it = CSRData.find(csr);
106  if (csr_data_it == CSRData.end()) {
107  valid = false;
108  } else {
109  valid = true;
110  midx = csr_data_it->second.physIndex;
111  csrName = csr_data_it->second.name;
112  auto mask_it = CSRMasks.find(csr);
113  if (mask_it == CSRMasks.end())
114  maskVal = mask(64);
115  else
116  maskVal = mask_it->second;
117  }
118 
119  if (csr == CSR_SATP) {
120  flags[IsSquashAfter] = true;
121  }
122  }
123 
124  std::string generateDisassembly(
125  Addr pc, const loader::SymbolTable *symtab) const override;
126 };
127 
128 } // namespace RiscvISA
129 } // namespace gem5
130 
131 #endif // __ARCH_RISCV_STANDARD_INST_HH__
gem5::RiscvISA::CSROp::midx
RegIndex midx
Definition: standard.hh:96
CSRIMM
#define CSRIMM
Definition: bitfields.hh:6
gem5::RiscvISA::CSRData
const std::map< int, CSRMetadata > CSRData
Definition: misc.hh:366
gem5::RiscvISA::CSROp::csrName
std::string csrName
Definition: standard.hh:97
gem5::RiscvISA::MachInst
uint32_t MachInst
Definition: types.hh:53
gem5::RiscvISA::SystemOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: standard.cc:78
FUNCT12
#define FUNCT12
Definition: bitfields.hh:7
gem5::RiscvISA::RiscvStaticInst
Base class for all RISC-V static instructions.
Definition: static_inst.hh:49
gem5::RiscvISA::RiscvStaticInst::RiscvStaticInst
RiscvStaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
Definition: static_inst.hh:52
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::RiscvISA::CSROp::uimm
uint64_t uimm
Definition: standard.hh:93
gem5::RiscvISA::SystemOp
Base class for system operations.
Definition: standard.hh:77
misc.hh
gem5::RiscvISA::CSROp
Base class for CSR operations.
Definition: standard.hh:89
gem5::RiscvISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::StaticInst::flags
std::bitset< Num_Flags > flags
Flag values for this instruction.
Definition: static_inst.hh:103
static_inst.hh
gem5::RiscvISA::ImmOp
Base class for operations with immediates (I is the type of immediate)
Definition: standard.hh:64
gem5::RiscvISA::mask
mask
Definition: pra_constants.hh:73
gem5::RiscvISA::CSR_SATP
@ CSR_SATP
Definition: misc.hh:251
static_inst.hh
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::RiscvISA::CSROp::valid
bool valid
Definition: standard.hh:95
gem5::RiscvISA::ImmOp::ImmOp
ImmOp(const char *mnem, MachInst _machInst, OpClass __opClass)
Definition: standard.hh:69
gem5::RiscvISA::RegOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: standard.cc:48
gem5::RiscvISA::CSROp::CSROp
CSROp(const char *mnem, MachInst _machInst, OpClass __opClass)
Constructor.
Definition: standard.hh:101
exec_context.hh
gem5::RiscvISA::CSROp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: standard.cc:61
gem5::RiscvISA::CSRMasks
const std::map< int, RegVal > CSRMasks
Definition: misc.hh:647
bitfields.hh
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::RiscvISA::RegOp
Base class for operations that work only on registers.
Definition: standard.hh:51
gem5::RiscvISA::CSROp::csr
uint64_t csr
Definition: standard.hh:92
gem5::RiscvISA::ImmOp::imm
I imm
Definition: standard.hh:67
gem5::RiscvISA::CSROp::maskVal
uint64_t maskVal
Definition: standard.hh:98

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