gem5  v21.1.0.2
standard.cc
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1 /*
2  * Copyright (c) 2015 RISC-V Foundation
3  * Copyright (c) 2017 The University of Virginia
4  * Copyright (c) 2020 Barkhausen Institut
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30 
32 
33 #include <sstream>
34 #include <string>
35 
37 #include "arch/riscv/regs/misc.hh"
38 #include "arch/riscv/utility.hh"
39 #include "cpu/static_inst.hh"
40 
41 namespace gem5
42 {
43 
44 namespace RiscvISA
45 {
46 
47 std::string
49 {
50  std::stringstream ss;
51  ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ", " <<
53  if (_numSrcRegs >= 2)
54  ss << ", " << registerName(srcRegIdx(1));
55  if (_numSrcRegs >= 3)
56  ss << ", " << registerName(srcRegIdx(2));
57  return ss.str();
58 }
59 
60 std::string
62 {
63  std::stringstream ss;
64  ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ", ";
65  auto data = CSRData.find(csr);
66  if (data != CSRData.end())
67  ss << data->second.name;
68  else
69  ss << "?? (" << std::hex << "0x" << csr << std::dec << ")";
70  if (_numSrcRegs > 0)
71  ss << ", " << registerName(srcRegIdx(0));
72  else
73  ss << uimm;
74  return ss.str();
75 }
76 
77 std::string
79 {
80  if (strcmp(mnemonic, "fence_vma") == 0) {
81  std::stringstream ss;
82  ss << mnemonic << ' ' << registerName(srcRegIdx(0)) << ", " <<
84  return ss.str();
85  }
86 
87  return mnemonic;
88 }
89 
90 } // namespace RiscvISA
91 } // namespace gem5
gem5::RiscvISA::CSRData
const std::map< int, CSRMetadata > CSRData
Definition: misc.hh:366
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::RiscvISA::SystemOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: standard.cc:78
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::RiscvISA::CSROp::uimm
uint64_t uimm
Definition: standard.hh:93
gem5::StaticInst::destRegIdx
const RegId & destRegIdx(int i) const
Return logical index (architectural reg num) of i'th destination reg.
Definition: static_inst.hh:237
misc.hh
gem5::RiscvISA::registerName
std::string registerName(RegId reg)
Definition: utility.hh:106
gem5::RiscvISA::ss
Bitfield< 11, 8 > ss
Definition: pra_constants.hh:257
gem5::StaticInst::srcRegIdx
const RegId & srcRegIdx(int i) const
Return logical index (architectural reg num) of i'th source reg.
Definition: static_inst.hh:247
standard.hh
gem5::RiscvISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
static_inst.hh
static_inst.hh
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::RiscvISA::RegOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: standard.cc:48
gem5::RiscvISA::CSROp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: standard.cc:61
utility.hh
gem5::StaticInst::mnemonic
const char * mnemonic
Base mnemonic (e.g., "add").
Definition: static_inst.hh:281
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::StaticInst::_numSrcRegs
int8_t _numSrcRegs
See numSrcRegs().
Definition: static_inst.hh:109
gem5::RiscvISA::CSROp::csr
uint64_t csr
Definition: standard.hh:92

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