gem5  v21.1.0.2
timer_sp804.cc
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37 
38 #include "dev/arm/timer_sp804.hh"
39 
40 #include <cassert>
41 
42 #include "base/intmath.hh"
43 #include "base/logging.hh"
44 #include "base/trace.hh"
45 #include "debug/Checkpoint.hh"
46 #include "debug/Timer.hh"
47 #include "dev/arm/base_gic.hh"
48 #include "mem/packet.hh"
49 #include "mem/packet_access.hh"
50 
51 namespace gem5
52 {
53 
55  : AmbaPioDevice(p, 0x1000),
56  timer0(name() + ".timer0", this, p.int0->get(), p.clock0),
57  timer1(name() + ".timer1", this, p.int1->get(), p.clock1)
58 {
59 }
60 
61 Sp804::Timer::Timer(std::string __name, Sp804 *_parent,
62  ArmInterruptPin *_interrupt, Tick _clock)
63  : _name(__name), parent(_parent), interrupt(_interrupt),
64  clock(_clock), control(0x20),
65  rawInt(false), pendingInt(false), loadValue(0xffffffff),
66  zeroEvent([this]{ counterAtZero(); }, name())
67 {
68 }
69 
70 
71 Tick
73 {
74  assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
75  assert(pkt->getSize() == 4);
76  Addr daddr = pkt->getAddr() - pioAddr;
77  DPRINTF(Timer, "Reading from DualTimer at offset: %#x\n", daddr);
78 
79  if (daddr < Timer::Size)
80  timer0.read(pkt, daddr);
81  else if ((daddr - Timer::Size) < Timer::Size)
82  timer1.read(pkt, daddr - Timer::Size);
83  else if (!readId(pkt, ambaId, pioAddr))
84  panic("Tried to read SP804 at offset %#x that doesn't exist\n", daddr);
85  pkt->makeAtomicResponse();
86  return pioDelay;
87 }
88 
89 
90 void
92 {
93  switch(daddr) {
94  case LoadReg:
95  pkt->setLE<uint32_t>(loadValue);
96  break;
97  case CurrentReg:
98  DPRINTF(Timer, "Event schedule for %d, clock=%d, prescale=%d\n",
99  zeroEvent.when(), clock, control.timerPrescale);
100  Tick time;
101  time = zeroEvent.when() - curTick();
102  time = (time / clock) >> (4 * control.timerPrescale);
103  DPRINTF(Timer, "-- returning counter at %d\n", time);
104  pkt->setLE<uint32_t>(time);
105  break;
106  case ControlReg:
107  pkt->setLE<uint32_t>(control);
108  break;
109  case RawISR:
110  pkt->setLE<uint32_t>(rawInt);
111  break;
112  case MaskedISR:
113  pkt->setLE<uint32_t>(pendingInt);
114  break;
115  case BGLoad:
116  pkt->setLE<uint32_t>(loadValue);
117  break;
118  default:
119  panic("Tried to read SP804 timer at offset %#x\n", daddr);
120  break;
121  }
122  DPRINTF(Timer, "Reading %#x from Timer at offset: %#x\n",
123  pkt->getLE<uint32_t>(), daddr);
124 }
125 
126 Tick
128 {
129  assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
130  assert(pkt->getSize() == 4);
131  Addr daddr = pkt->getAddr() - pioAddr;
132  DPRINTF(Timer, "Writing to DualTimer at offset: %#x\n", daddr);
133 
134  if (daddr < Timer::Size)
135  timer0.write(pkt, daddr);
136  else if ((daddr - Timer::Size) < Timer::Size)
137  timer1.write(pkt, daddr - Timer::Size);
138  else if (!readId(pkt, ambaId, pioAddr))
139  panic("Tried to write SP804 at offset %#x that doesn't exist\n", daddr);
140  pkt->makeAtomicResponse();
141  return pioDelay;
142 }
143 
144 void
146 {
147  DPRINTF(Timer, "Writing %#x to Timer at offset: %#x\n",
148  pkt->getLE<uint32_t>(), daddr);
149  switch (daddr) {
150  case LoadReg:
151  loadValue = pkt->getLE<uint32_t>();
152  restartCounter(loadValue);
153  break;
154  case CurrentReg:
155  // Spec says this value can't be written, but linux writes it anyway
156  break;
157  case ControlReg:
158  bool old_enable;
159  old_enable = control.timerEnable;
160  control = pkt->getLE<uint32_t>();
161  if ((old_enable == 0) && control.timerEnable)
162  restartCounter(loadValue);
163  break;
164  case IntClear:
165  rawInt = false;
166  if (pendingInt) {
167  pendingInt = false;
168  DPRINTF(Timer, "Clearing interrupt\n");
169  interrupt->clear();
170  }
171  break;
172  case BGLoad:
173  loadValue = pkt->getLE<uint32_t>();
174  break;
175  default:
176  panic("Tried to write SP804 timer at offset %#x\n", daddr);
177  break;
178  }
179 }
180 
181 void
183 {
184  DPRINTF(Timer, "Resetting counter with value %#x\n", val);
185  if (!control.timerEnable)
186  return;
187 
188  Tick time = clock << (4 * control.timerPrescale);
189  if (control.timerSize)
190  time *= val;
191  else
192  time *= bits(val,15,0);
193 
194  if (zeroEvent.scheduled()) {
195  DPRINTF(Timer, "-- Event was already schedule, de-scheduling\n");
196  parent->deschedule(zeroEvent);
197  }
198  parent->schedule(zeroEvent, curTick() + time);
199  DPRINTF(Timer, "-- Scheduling new event for: %d\n", curTick() + time);
200 }
201 
202 void
204 {
205  if (!control.timerEnable)
206  return;
207 
208  DPRINTF(Timer, "Counter reached zero\n");
209 
210  rawInt = true;
211  bool old_pending = pendingInt;
212  if (control.intEnable)
213  pendingInt = true;
214  if (pendingInt && !old_pending) {
215  DPRINTF(Timer, "-- Causing interrupt\n");
216  interrupt->raise();
217  }
218 
219  if (control.oneShot)
220  return;
221 
222  // Free-running
223  if (control.timerMode == 0)
224  restartCounter(0xffffffff);
225  else
226  restartCounter(loadValue);
227 }
228 
229 void
231 {
232  DPRINTF(Checkpoint, "Serializing Arm Sp804\n");
233 
234  uint32_t control_serial = control;
235  SERIALIZE_SCALAR(control_serial);
236 
237  SERIALIZE_SCALAR(rawInt);
238  SERIALIZE_SCALAR(pendingInt);
239  SERIALIZE_SCALAR(loadValue);
240 
241  bool is_in_event = zeroEvent.scheduled();
242  SERIALIZE_SCALAR(is_in_event);
243 
244  Tick event_time;
245  if (is_in_event){
246  event_time = zeroEvent.when();
247  SERIALIZE_SCALAR(event_time);
248  }
249 }
250 
251 void
253 {
254  DPRINTF(Checkpoint, "Unserializing Arm Sp804\n");
255 
256  uint32_t control_serial;
257  UNSERIALIZE_SCALAR(control_serial);
258  control = control_serial;
259 
260  UNSERIALIZE_SCALAR(rawInt);
261  UNSERIALIZE_SCALAR(pendingInt);
262  UNSERIALIZE_SCALAR(loadValue);
263 
264  bool is_in_event;
265  UNSERIALIZE_SCALAR(is_in_event);
266 
267  Tick event_time;
268  if (is_in_event){
269  UNSERIALIZE_SCALAR(event_time);
270  parent->schedule(zeroEvent, event_time);
271  }
272 }
273 
274 
275 
276 void
278 {
279  timer0.serializeSection(cp, "timer0");
280  timer1.serializeSection(cp, "timer1");
281 }
282 
283 void
285 {
286  timer0.unserializeSection(cp, "timer0");
287  timer1.unserializeSection(cp, "timer1");
288 }
289 
290 } // namespace gem5
gem5::AmbaPioDevice::ambaId
uint64_t ambaId
Definition: amba_device.hh:81
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
gem5::Sp804::Timer::restartCounter
void restartCounter(uint32_t val)
Restart the counter ticking at val.
Definition: timer_sp804.cc:182
gem5::BasicPioDevice::pioAddr
Addr pioAddr
Address that the device listens to.
Definition: io_device.hh:151
gem5::Sp804::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: timer_sp804.cc:277
UNSERIALIZE_SCALAR
#define UNSERIALIZE_SCALAR(scalar)
Definition: serialize.hh:575
gem5::Sp804::Timer::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: timer_sp804.cc:230
int1
bool int1
Definition: common.h:43
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::Sp804::Timer::write
void write(PacketPtr pkt, Addr daddr)
Handle write for a single timer.
Definition: timer_sp804.cc:145
base_gic.hh
gem5::Serializable::serializeSection
void serializeSection(CheckpointOut &cp, const char *name) const
Serialize an object into a new section.
Definition: serialize.cc:74
gem5::Sp804
Definition: timer_sp804.hh:59
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::Packet::makeAtomicResponse
void makeAtomicResponse()
Definition: packet.hh:1043
gem5::Sp804::Timer::read
void read(PacketPtr pkt, Addr daddr)
Handle read for a single timer.
Definition: timer_sp804.cc:91
gem5::AmbaPioDevice::Params
AmbaPioDeviceParams Params
Definition: amba_device.hh:84
gem5::Sp804::Timer::counterAtZero
void counterAtZero()
Called when the counter reaches 0.
Definition: timer_sp804.cc:203
gem5::AmbaPioDevice
Definition: amba_device.hh:78
gem5::Sp804::Sp804
Sp804(const Params &p)
The constructor for RealView just registers itself with the MMU.
Definition: timer_sp804.cc:54
packet.hh
gem5::Sp804::Timer
Definition: timer_sp804.hh:62
gem5::Sp804::read
Tick read(PacketPtr pkt) override
Handle a read to the device.
Definition: timer_sp804.cc:72
gem5::Named::name
virtual std::string name() const
Definition: named.hh:47
gem5::Serializable::unserializeSection
void unserializeSection(CheckpointIn &cp, const char *name)
Unserialize an a child object.
Definition: serialize.cc:81
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::BasicPioDevice::pioDelay
Tick pioDelay
Delay that the device experinces on an access.
Definition: io_device.hh:157
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
gem5::Sp804::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: timer_sp804.cc:284
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::Sp804::Timer::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: timer_sp804.cc:252
name
const std::string & name()
Definition: trace.cc:49
SERIALIZE_SCALAR
#define SERIALIZE_SCALAR(scalar)
Definition: serialize.hh:568
packet_access.hh
gem5::Sp804::Timer::Size
@ Size
Definition: timer_sp804.hh:75
gem5::Sp804::timer1
Timer timer1
Definition: timer_sp804.hh:139
gem5::Sp804::timer0
Timer timer0
Timers that do the actual work.
Definition: timer_sp804.hh:138
timer_sp804.hh
gem5::Sp804::Timer::Timer
Timer(std::string __name, Sp804 *parent, ArmInterruptPin *_interrupt, Tick clock)
Definition: timer_sp804.cc:61
logging.hh
gem5::Packet::getLE
T getLE() const
Get the data in the packet byte swapped from little endian to host endian.
Definition: packet_access.hh:78
gem5::BasicPioDevice::pioSize
Addr pioSize
Size that the device's address range.
Definition: io_device.hh:154
gem5::Sp804::write
Tick write(PacketPtr pkt) override
All writes are simply ignored.
Definition: timer_sp804.cc:127
gem5::Sp804::Timer::timerPrescale
Bitfield< 3, 2 > timerPrescale
Definition: timer_sp804.hh:81
gem5::ArmInterruptPin
Generic representation of an Arm interrupt pin.
Definition: base_gic.hh:200
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::AmbaDevice::readId
bool readId(PacketPtr pkt, uint64_t amba_id, Addr pio_addr)
Definition: amba_device.cc:75
trace.hh
gem5::Packet::setLE
void setLE(T v)
Set the value in the data pointer to v as little endian.
Definition: packet_access.hh:108
gem5::Packet::getAddr
Addr getAddr() const
Definition: packet.hh:781
intmath.hh
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::Packet::getSize
unsigned getSize() const
Definition: packet.hh:791
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177

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