gem5
v24.0.0.0
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arch
arm
insts
tme64classic.cc
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/*
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* Copyright (c) 2020 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "
arch/arm/faults.hh
"
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#include "
arch/arm/insts/tme64.hh
"
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namespace
gem5
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{
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using namespace
ArmISA;
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namespace
ArmISAInst {
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Fault
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Tstart64::initiateAcc
(
ExecContext
*xc,
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trace::InstRecord
*traceData)
const
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{
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return
std::make_shared<UndefinedInstruction>(
machInst
,
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false
,
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mnemonic
);
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}
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Fault
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Tstart64::completeAcc
(
PacketPtr
pkt,
ExecContext
*xc,
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trace::InstRecord
*traceData)
const
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{
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return
std::make_shared<UndefinedInstruction>(
machInst
,
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false
,
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mnemonic
);
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}
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Fault
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Ttest64::execute
(
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ExecContext
*xc,
trace::InstRecord
*traceData)
const
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{
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return
std::make_shared<UndefinedInstruction>(
machInst
,
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false
,
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mnemonic
);
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}
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Fault
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Tcancel64::initiateAcc
(
ExecContext
*xc,
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trace::InstRecord
*traceData)
const
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{
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return
std::make_shared<UndefinedInstruction>(
machInst
,
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false
,
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mnemonic
);
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}
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Fault
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Tcancel64::completeAcc
(
PacketPtr
pkt,
ExecContext
*xc,
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trace::InstRecord
*traceData)
const
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{
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return
std::make_shared<UndefinedInstruction>(
machInst
,
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false
,
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mnemonic
);
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}
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Fault
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MicroTcommit64::initiateAcc
(
ExecContext
*xc,
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trace::InstRecord
*traceData)
const
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{
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return
std::make_shared<UndefinedInstruction>(
machInst
,
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false
,
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mnemonic
);
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}
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Fault
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MicroTcommit64::completeAcc
(
PacketPtr
pkt,
ExecContext
*xc,
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trace::InstRecord
*traceData)
const
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{
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return
std::make_shared<UndefinedInstruction>(
machInst
,
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false
,
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mnemonic
);
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}
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}
// namespace ArmISAInst
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}
// namespace gem5
faults.hh
gem5::ArmISAInst::MicroTcommit64::initiateAcc
Fault initiateAcc(ExecContext *, trace::InstRecord *) const
Definition
tme64classic.cc:94
gem5::ArmISAInst::MicroTcommit64::completeAcc
Fault completeAcc(PacketPtr, ExecContext *, trace::InstRecord *) const
Definition
tme64classic.cc:103
gem5::ArmISAInst::Tcancel64::completeAcc
Fault completeAcc(PacketPtr, ExecContext *, trace::InstRecord *) const
Definition
tme64classic.cc:85
gem5::ArmISAInst::Tcancel64::initiateAcc
Fault initiateAcc(ExecContext *, trace::InstRecord *) const
Definition
tme64classic.cc:76
gem5::ArmISAInst::Tstart64::initiateAcc
Fault initiateAcc(ExecContext *, trace::InstRecord *) const
Definition
tme64classic.cc:49
gem5::ArmISAInst::Tstart64::completeAcc
Fault completeAcc(PacketPtr, ExecContext *, trace::InstRecord *) const
Definition
tme64classic.cc:58
gem5::ArmISAInst::Ttest64::execute
Fault execute(ExecContext *, trace::InstRecord *) const
Definition
tme64classic.cc:67
gem5::ArmISA::ArmStaticInst::machInst
ExtMachInst machInst
Definition
static_inst.hh:151
gem5::ExecContext
The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate th...
Definition
exec_context.hh:72
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition
packet.hh:295
gem5::StaticInst::mnemonic
const char * mnemonic
Base mnemonic (e.g., "add").
Definition
static_inst.hh:268
gem5::trace::InstRecord
Definition
insttracer.hh:62
gem5
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition
binary32.hh:36
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition
types.hh:249
tme64.hh
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