gem5  v21.1.0.2
tme64.cc
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37 
38 #include "arch/arm/insts/tme64.hh"
39 
40 #include <sstream>
41 
42 #include "debug/ArmTme.hh"
43 
44 namespace gem5
45 {
46 
47 using namespace ArmISA;
48 
49 namespace ArmISAInst {
50 
51 std::string
53  Addr pc, const loader::SymbolTable *symtab) const
54 {
55  std::stringstream ss;
56  printMnemonic(ss, "", false);
57  ccprintf(ss, "#0x%x", imm);
58  return ss.str();
59 }
60 
61 std::string
63  Addr pc, const loader::SymbolTable *symtab) const
64 {
65  std::stringstream ss;
66  printMnemonic(ss);
67  printIntReg(ss, dest);
68  return ss.str();
69 }
70 
71 std::string
73  Addr pc, const loader::SymbolTable *symtab) const
74 {
75  std::stringstream ss;
76  printMnemonic(ss);
77  return ss.str();
78 }
79 
81  : MicroTmeBasic64("utfence", machInst, MemReadOp)
82 {
83  _numSrcRegs = 0;
84  _numDestRegs = 0;
85  _numFPDestRegs = 0;
86  _numVecDestRegs = 0;
88  _numIntDestRegs = 0;
89  _numCCDestRegs = 0;
90  flags[IsMicroop] = true;
91  flags[IsReadBarrier] = true;
92  flags[IsWriteBarrier] = true;
93 }
94 
95 Fault
97  ExecContext *xc, Trace::InstRecord *traceData) const
98 {
99  return NoFault;
100 }
101 
102 Fault
104  Trace::InstRecord *traceData) const
105 {
106  panic("tfence should not have memory semantics");
107 
108  return NoFault;
109 }
110 
111 Fault
113  Trace::InstRecord *traceData) const
114 {
115  panic("tfence should not have memory semantics");
116 
117  return NoFault;
118 }
119 
120 Tstart64::Tstart64(ExtMachInst machInst, IntRegIndex _dest)
121  : TmeRegNone64("tstart", machInst, MemReadOp, _dest)
122 {
124  nullptr,
125  reinterpret_cast<RegIdArrayPtr>(
126  &std::remove_pointer_t<decltype(this)>::destRegIdxArr));
127  ;
128 
129  _numSrcRegs = 0;
130  _numDestRegs = 0;
131  _numFPDestRegs = 0;
132  _numVecDestRegs = 0;
134  _numIntDestRegs = 0;
135  _numCCDestRegs = 0;
137  _numIntDestRegs++;
138  flags[IsHtmStart] = true;
139  flags[IsInteger] = true;
140  flags[IsLoad] = true;
141  flags[IsMicroop] = true;
142  flags[IsNonSpeculative] = true;
143 }
144 
145 Fault
147  ExecContext *xc, Trace::InstRecord *traceData) const
148 {
149  panic("TME is not supported with atomic memory");
150 
151  return NoFault;
152 }
153 
154 Ttest64::Ttest64(ExtMachInst machInst, IntRegIndex _dest)
155  : TmeRegNone64("ttest", machInst, MemReadOp, _dest)
156 {
158  nullptr,
159  reinterpret_cast<RegIdArrayPtr>(
160  &std::remove_pointer_t<decltype(this)>::destRegIdxArr));
161  ;
162 
163  _numSrcRegs = 0;
164  _numDestRegs = 0;
165  _numFPDestRegs = 0;
166  _numVecDestRegs = 0;
168  _numIntDestRegs = 0;
169  _numCCDestRegs = 0;
171  _numIntDestRegs++;
172  flags[IsInteger] = true;
173  flags[IsMicroop] = true;
174 }
175 
176 Tcancel64::Tcancel64(ExtMachInst machInst, uint64_t _imm)
177  : TmeImmOp64("tcancel", machInst, MemReadOp, _imm)
178 {
179  _numSrcRegs = 0;
180  _numDestRegs = 0;
181  _numFPDestRegs = 0;
182  _numVecDestRegs = 0;
184  _numIntDestRegs = 0;
185  _numCCDestRegs = 0;
186  flags[IsLoad] = true;
187  flags[IsMicroop] = true;
188  flags[IsNonSpeculative] = true;
189  flags[IsHtmCancel] = true;
190 }
191 
192 Fault
194  ExecContext *xc, Trace::InstRecord *traceData) const
195 {
196  panic("TME is not supported with atomic memory");
197 
198  return NoFault;
199 }
200 
201 MacroTmeOp::MacroTmeOp(const char *mnem,
202  ExtMachInst _machInst,
203  OpClass __opClass) :
204  PredMacroOp(mnem, machInst, __opClass) {
205  _numSrcRegs = 0;
206  _numDestRegs = 0;
207  _numFPDestRegs = 0;
208  _numVecDestRegs = 0;
210  _numIntDestRegs = 0;
211  _numCCDestRegs = 0;
212 
213  numMicroops = 0;
214  microOps = nullptr;
215 }
216 
218  : MicroTmeBasic64("utcommit", machInst, MemReadOp)
219 {
220  _numSrcRegs = 0;
221  _numDestRegs = 0;
222  _numFPDestRegs = 0;
223  _numVecDestRegs = 0;
225  _numIntDestRegs = 0;
226  _numCCDestRegs = 0;
227  flags[IsHtmStop] = true;
228  flags[IsLoad] = true;
229  flags[IsMicroop] = true;
230  flags[IsNonSpeculative] = true;
231 }
232 
233 Fault
235 {
236  panic("TME is not supported with atomic memory");
237 
238  return NoFault;
239 }
240 
242  MacroTmeOp("tcommit", machInst, MemReadOp)
243 {
244  numMicroops = 2;
246 
247  microOps[0] = new ArmISAInst::MicroTfence64(_machInst);
250 
251  microOps[1] = new ArmISAInst::MicroTcommit64(_machInst);
253  microOps[1]->setLastMicroop();
254 }
255 
256 } // namespace ArmISAInst
257 } // namespace gem5
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:260
gem5::ArmISAInst::Tstart64::Tstart64
Tstart64(ArmISA::ExtMachInst, ArmISA::IntRegIndex)
Definition: tme64.cc:120
gem5::StaticInst::RegIdArrayPtr
RegId(StaticInst::*)[] RegIdArrayPtr
Definition: static_inst.hh:91
gem5::ArmISAInst::Tcommit64::Tcommit64
Tcommit64(ArmISA::ExtMachInst _machInst)
Definition: tme64.cc:241
gem5::StaticInst::_numFPDestRegs
int8_t _numFPDestRegs
The following are used to track physical register usage for machines with separate int & FP reg files...
Definition: static_inst.hh:117
gem5::StaticInst::_numIntDestRegs
int8_t _numIntDestRegs
Definition: static_inst.hh:118
gem5::ArmISA::PredMacroOp::numMicroops
uint32_t numMicroops
Definition: pred_inst.hh:344
gem5::ArmISAInst::MacroTmeOp::MacroTmeOp
MacroTmeOp(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass)
Definition: tme64.cc:201
gem5::ArmISAInst::MicroTfence64::completeAcc
Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const
Definition: tme64.cc:112
tme64.hh
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::ArmISAInst::MicroTcommit64::execute
Fault execute(ExecContext *, Trace::InstRecord *) const
Definition: tme64.cc:234
gem5::StaticInst::setDestRegIdx
void setDestRegIdx(int i, const RegId &val)
Definition: static_inst.hh:240
gem5::ArmISAInst::MicroTfence64::execute
Fault execute(ExecContext *, Trace::InstRecord *) const
Definition: tme64.cc:96
gem5::ArmISAInst::MicroTcommit64::MicroTcommit64
MicroTcommit64(ArmISA::ExtMachInst)
Definition: tme64.cc:217
gem5::StaticInst::_numCCDestRegs
int8_t _numCCDestRegs
Definition: static_inst.hh:119
gem5::ccprintf
void ccprintf(cp::Print &print)
Definition: cprintf.hh:130
gem5::ArmISAInst::Ttest64::destRegIdxArr
RegId destRegIdxArr[1]
Definition: tme64.hh:117
gem5::RefCountingPtr< StaticInst >
gem5::ArmISAInst::Ttest64::Ttest64
Ttest64(ArmISA::ExtMachInst, ArmISA::IntRegIndex)
Definition: tme64.cc:154
gem5::ArmISAInst::MicroTfence64
Definition: tme64.hh:135
gem5::ArmISAInst::Tcancel64::execute
Fault execute(ExecContext *, Trace::InstRecord *) const
Definition: tme64.cc:193
gem5::ArmISAInst::Tstart64::destRegIdxArr
RegId destRegIdxArr[1]
Definition: tme64.hh:104
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::ArmISAInst::TmeImmOp64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
Internal function to generate disassembly string.
Definition: tme64.cc:52
gem5::ArmISAInst::TmeRegNone64::dest
ArmISA::IntRegIndex dest
Definition: tme64.hh:89
gem5::ArmISA::PredMacroOp::microOps
StaticInstPtr * microOps
Definition: pred_inst.hh:345
gem5::ArmISAInst::MicroTmeBasic64
Definition: tme64.hh:59
gem5::StaticInst::_numVecElemDestRegs
int8_t _numVecElemDestRegs
Definition: static_inst.hh:125
gem5::ArmISAInst::Tcancel64::Tcancel64
Tcancel64(ArmISA::ExtMachInst, uint64_t)
Definition: tme64.cc:176
gem5::ArmISAInst::MicroTcommit64
Definition: tme64.hh:145
gem5::StaticInst::flags
std::bitset< Num_Flags > flags
Flag values for this instruction.
Definition: static_inst.hh:103
gem5::StaticInst::setRegIdxArrays
void setRegIdxArrays(RegIdArrayPtr src, RegIdArrayPtr dest)
Set the pointers which point to the arrays of source and destination register indices.
Definition: static_inst.hh:269
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISAInst::MicroTmeBasic64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
Internal function to generate disassembly string.
Definition: tme64.cc:72
gem5::MemReadOp
static const OpClass MemReadOp
Definition: op_class.hh:102
gem5::StaticInst::setLastMicroop
void setLastMicroop()
Definition: static_inst.hh:227
gem5::ArmISA::PredMacroOp
Base class for predicated macro-operations.
Definition: pred_inst.hh:340
gem5::StaticInst::setDelayedCommit
void setDelayedCommit()
Definition: static_inst.hh:228
gem5::X86ISA::ExtMachInst
Definition: types.hh:206
gem5::ArmISAInst::TmeRegNone64
Definition: tme64.hh:86
gem5::ArmISA::imm
Bitfield< 7, 0 > imm
Definition: types.hh:132
gem5::ArmISA::ss
Bitfield< 21 > ss
Definition: misc_types.hh:59
gem5::StaticInst::setFirstMicroop
void setFirstMicroop()
Definition: static_inst.hh:226
gem5::ArmISAInst::TmeRegNone64::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
Internal function to generate disassembly string.
Definition: tme64.cc:62
gem5::StaticInst::_numDestRegs
int8_t _numDestRegs
See numDestRegs().
Definition: static_inst.hh:112
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::ArmISAInst::TmeImmOp64
Definition: tme64.hh:71
gem5::ExecContext
The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate th...
Definition: exec_context.hh:73
gem5::ArmISAInst::MacroTmeOp
Definition: tme64.hh:156
gem5::ArmISAInst::MicroTfence64::MicroTfence64
MicroTfence64(ArmISA::ExtMachInst)
Definition: tme64.cc:80
gem5::Trace::InstRecord
Definition: insttracer.hh:58
gem5::ArmISAInst::MicroTfence64::initiateAcc
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const
Definition: tme64.cc:103
gem5::IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:57
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::StaticInst::_numSrcRegs
int8_t _numSrcRegs
See numSrcRegs().
Definition: static_inst.hh:109
gem5::ArmISAInst::Tstart64::execute
Fault execute(ExecContext *, Trace::InstRecord *) const
Definition: tme64.cc:146
gem5::StaticInst::_numVecDestRegs
int8_t _numVecDestRegs
To use in architectures with vector register file.
Definition: static_inst.hh:124
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:88
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177

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