gem5  v21.1.0.2
uart8250.hh
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28 
33 #ifndef __DEV_UART8250_HH__
34 #define __DEV_UART8250_HH__
35 
36 #include "base/bitunion.hh"
37 #include "base/logging.hh"
38 #include "dev/io_device.hh"
39 #include "dev/reg_bank.hh"
40 #include "dev/serial/uart.hh"
41 #include "params/Uart8250.hh"
42 
43 namespace gem5
44 {
45 
46 const uint8_t UART_MCR_LOOP = 0x10;
47 
48 class Terminal;
49 class Platform;
50 
51 class Uart8250 : public Uart
52 {
53  protected:
54  BitUnion8(Ier)
55  Bitfield<0> rdi; // Receive data available interrupt.
56  Bitfield<1> thri; // Transmit holding register interrupt.
57  Bitfield<2> rlsi; // Receive line status interrupt.
58  Bitfield<3> msi; // Modem status interrupt.
59  EndBitUnion(Ier)
60 
61  BitUnion8(Iir)
62  Bitfield<0> pending; // 0 = pending, 1 = not pending.
63  Bitfield<2, 1> id; // ID of highest priority interrupt.
64  Bitfield<7, 3> zeroes;
65  EndBitUnion(Iir)
66 
67  BitUnion8(Lcr)
68  Bitfield<1, 0> wordSize;
69  Bitfield<2> stopBits;
70  Bitfield<5, 3> parity;
71  Bitfield<6> breakCont;
72  Bitfield<7> dlab;
73  EndBitUnion(Lcr)
74 
75  BitUnion8(Lsr)
76  Bitfield<0> rdr; // Received data ready?
77  Bitfield<1> overrunError;
78  Bitfield<2> parityError;
79  Bitfield<3> framingError;
80  Bitfield<4> breakCond;
81  Bitfield<5> tbe; // Transmit buffer empty.
82  Bitfield<6> txEmpty; // Transmitter empty.
83  Bitfield<7> unused;
85 
86  enum class InterruptIds
87  {
88  Modem = 0, // Modem Status (lowest priority).
89  Tx = 1, // Tx Data.
90  Rx = 2, // Rx Data.
91  Line = 3, // Rx Line Status (highest priority).
92  };
93 
94  class Registers : public RegisterBankLE
95  {
96  public:
97  Registers(Uart8250 *uart, const std::string &new_name);
98 
99  class PairedRegister : public RegisterBase
100  {
101  protected:
102  RegisterBase &_reg1, &_reg2;
103 
104  public:
105  PairedRegister(RegisterBase &reg1, RegisterBase &reg2) :
106  RegisterBase(reg1.name() + "/" + reg2.name(), reg1.size()),
107  _reg1(reg1), _reg2(reg2)
108  {
109  panic_if(reg1.size() != reg2.size(),
110  "Mismatched paired register sizes %d, %d",
111  reg1.size(), reg2.size());
112  }
113 
114  void serialize(std::ostream &os) const override {}
115  bool unserialize(const std::string &s) override { return true; }
116  };
117 
119  {
120  private:
121  RegisterBase *selected = nullptr;
122 
123  public:
124  BankedRegister(RegisterBase &reg1, RegisterBase &reg2) :
125  PairedRegister(reg1, reg2), selected(&reg1)
126  {}
127 
128  void select(bool second) { selected = second ? &_reg2 : &_reg1; }
129 
130  const std::string &
131  name() const override
132  {
133  return selected->name();
134  }
135 
136  void read(void *buf) override { selected->read(buf); }
137  void
138  read(void *buf, off_t offset, size_t bytes) override
139  {
140  selected->read(buf, offset, bytes);
141  }
142  void write(const void *buf) override { selected->write(buf); }
143  void
144  write(const void *buf, off_t offset, size_t bytes) override
145  {
146  selected->write(buf, offset, bytes);
147  }
148  };
149 
151  {
152  public:
154 
155  void read(void *buf) override { _reg1.read(buf); }
156  void
157  read(void *buf, off_t offset, size_t bytes) override
158  {
159  _reg1.read(buf, offset, bytes);
160  }
161  void write(const void *buf) override { _reg2.write(buf); }
162  void
163  write(const void *buf, off_t offset, size_t bytes) override
164  {
165  _reg2.write(buf, offset, bytes);
166  }
167  };
168 
169  // Offset 0.
170  Register8 rbr = {"rbr"};
171  Register8 thr = {"thr"};
173 
174  Register8 dll = {"dll"};
176 
177  // Offset 1.
178  Register<Ier> ier = {"ier", 0};
179  Register8 dlh = {"dlh"};
181 
182  // Offset 2.
183  Register<Iir> iir = {"iir"};
184  Register8 fcr = {"fcr"};
186 
187  // Offsets 3 - 6.
188  Register<Lcr> lcr = {"lcr"};
189  Register8 mcr = {"mcr"};
190  Register<Lsr> lsr = {"lsr"};
191  Register8 msr = {"msr"};
192 
193  // The scratch register didn't exist on the 8250.
194  RegisterRaz sr = {"sr", 1};
195  };
197  template <class T>
198  using Register = Registers::Register<T>;
199 
201 
202  uint8_t readRbr(Register8 &reg);
203  void writeThr(Register8 &reg, const uint8_t &data);
204  void writeIer(Register<Ier> &reg, const Ier &ier);
205  Iir readIir(Register<Iir> &reg);
206 
208 
209  void processIntrEvent(int intrBit);
210  void scheduleIntr(Event *event);
211 
214 
215  public:
216  using Params = Uart8250Params;
217  Uart8250(const Params &p);
218 
219  Tick read(PacketPtr pkt) override;
220  Tick write(PacketPtr pkt) override;
221  AddrRangeList getAddrRanges() const override;
222 
226  void dataAvailable() override;
227 
228 
233  virtual bool intStatus() { return status ? true : false; }
234 
235  void serialize(CheckpointOut &cp) const override;
236  void unserialize(CheckpointIn &cp) override;
237 };
238 
239 } // namespace gem5
240 
241 #endif // __TSUNAMI_UART_HH__
gem5::scmi::Platform
Definition: scmi_platform.hh:264
gem5::RegisterBank< ByteOrder::little >::Register8
Register< uint8_t > Register8
Definition: reg_bank.hh:788
gem5::Uart8250::writeIer
void writeIer(Register< Ier > &reg, const Ier &ier)
Definition: uart8250.cc:179
gem5::UART_MCR_LOOP
const uint8_t UART_MCR_LOOP
Definition: uart8250.hh:46
gem5::Uart8250::scheduleIntr
void scheduleIntr(Event *event)
Definition: uart8250.cc:76
io_device.hh
gem5::Uart8250::Registers::ierDlh
BankedRegister ierDlh
Definition: uart8250.hh:180
gem5::Uart8250::Registers::iirFcr
RWSwitchedRegister iirFcr
Definition: uart8250.hh:185
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::Uart8250::rlsi
Bitfield< 2 > rlsi
Definition: uart8250.hh:57
gem5::Uart8250::Registers::BankedRegister::write
void write(const void *buf) override
Definition: uart8250.hh:142
gem5::Uart8250::breakCont
Bitfield< 6 > breakCont
Definition: uart8250.hh:71
gem5::Uart8250::Registers::PairedRegister::serialize
void serialize(std::ostream &os) const override
Definition: uart8250.hh:114
gem5::Uart8250::writeThr
void writeThr(Register8 &reg, const uint8_t &data)
Definition: uart8250.cc:150
gem5::Uart8250::tbe
Bitfield< 5 > tbe
Definition: uart8250.hh:81
gem5::Uart8250::txEmpty
Bitfield< 6 > txEmpty
Definition: uart8250.hh:82
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::Uart8250::Registers::thr
Register8 thr
Definition: uart8250.hh:171
gem5::MipsISA::event
Bitfield< 10, 5 > event
Definition: pra_constants.hh:300
gem5::Uart8250::Registers
Definition: uart8250.hh:94
gem5::Uart8250::write
Tick write(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: uart8250.cc:230
gem5::Uart8250::Registers::Registers
Registers(Uart8250 *uart, const std::string &new_name)
Definition: uart8250.cc:96
gem5::Uart8250::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: uart8250.cc:284
gem5::Uart8250::Uart8250
Uart8250(const Params &p)
Definition: uart8250.cc:88
gem5::Uart8250::breakCond
Bitfield< 4 > breakCond
Definition: uart8250.hh:80
gem5::Uart8250::Registers::rbr
Register8 rbr
Definition: uart8250.hh:170
gem5::Uart8250::getAddrRanges
AddrRangeList getAddrRanges() const override
Determine the address ranges that this device responds to.
Definition: uart8250.cc:255
gem5::Uart::status
int status
Definition: uart.hh:52
gem5::Uart8250::Registers::BankedRegister::BankedRegister
BankedRegister(RegisterBase &reg1, RegisterBase &reg2)
Definition: uart8250.hh:124
gem5::Uart8250::overrunError
Bitfield< 1 > overrunError
Definition: uart8250.hh:77
gem5::Uart8250::Registers::RWSwitchedRegister::read
void read(void *buf) override
Definition: uart8250.hh:155
gem5::RegisterBank< ByteOrder::little >::size
Addr size() const
Definition: reg_bank.hh:823
gem5::Uart8250::zeroes
Bitfield< 7, 3 > zeroes
Definition: uart8250.hh:64
gem5::PioDevice::Params
PioDeviceParams Params
Definition: io_device.hh:134
gem5::Uart8250::Registers::BankedRegister::selected
RegisterBase * selected
Definition: uart8250.hh:121
gem5::Uart8250::registers
Registers registers
Definition: uart8250.hh:200
gem5::Uart8250::Registers::dll
Register8 dll
Definition: uart8250.hh:174
gem5::Uart8250::Registers::BankedRegister::read
void read(void *buf, off_t offset, size_t bytes) override
Definition: uart8250.hh:138
gem5::Uart8250::Registers::dlh
Register8 dlh
Definition: uart8250.hh:179
gem5::Uart8250::id
Bitfield< 2, 1 > id
Definition: uart8250.hh:63
gem5::Uart8250::parity
Bitfield< 5, 3 > parity
Definition: uart8250.hh:70
gem5::Uart8250::Registers::BankedRegister::write
void write(const void *buf, off_t offset, size_t bytes) override
Definition: uart8250.hh:144
gem5::Uart
Definition: uart.hh:49
gem5::Uart8250::Registers::iir
Register< Iir > iir
Definition: uart8250.hh:183
gem5::Uart8250::msi
Bitfield< 3 > msi
Definition: uart8250.hh:58
gem5::Uart8250::Registers::BankedRegister::name
const std::string & name() const override
Definition: uart8250.hh:131
gem5::Uart8250::Registers::msr
Register8 msr
Definition: uart8250.hh:191
gem5::Event
Definition: eventq.hh:251
gem5::Uart8250::thri
Bitfield< 1 > thri
Definition: uart8250.hh:56
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::Uart8250::dlab
Bitfield< 7 > dlab
Definition: uart8250.hh:72
gem5::Uart8250::Registers::PairedRegister::PairedRegister
PairedRegister(RegisterBase &reg1, RegisterBase &reg2)
Definition: uart8250.hh:105
uart.hh
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::Uart8250::Register
Registers::Register< T > Register
Definition: uart8250.hh:198
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::Uart8250::lastTxInt
Tick lastTxInt
Definition: uart8250.hh:207
gem5::Terminal
Definition: terminal.hh:64
bitunion.hh
gem5::Uart8250::unused
Bitfield< 7 > unused
Definition: uart8250.hh:83
gem5::ArmISA::s
Bitfield< 4 > s
Definition: misc_types.hh:561
gem5::Uart8250::Registers::BankedRegister
Definition: uart8250.hh:118
gem5::Uart8250::Registers::RWSwitchedRegister::read
void read(void *buf, off_t offset, size_t bytes) override
Definition: uart8250.hh:157
gem5::Uart8250::wordSize
wordSize
Definition: uart8250.hh:68
gem5::ArmISA::offset
Bitfield< 23, 0 > offset
Definition: types.hh:144
gem5::Uart8250::readIir
Iir readIir(Register< Iir > &reg)
Definition: uart8250.cc:160
gem5::Uart8250::stopBits
Bitfield< 2 > stopBits
Definition: uart8250.hh:69
gem5::Uart8250::Registers::fcr
Register8 fcr
Definition: uart8250.hh:184
gem5::Uart8250
Definition: uart8250.hh:51
gem5::Uart8250::BitUnion8
BitUnion8(Ier) Bitfield< 0 > rdi
gem5::Uart8250::dataAvailable
void dataAvailable() override
Inform the uart that there is data available.
Definition: uart8250.cc:244
gem5::Uart8250::Registers::BankedRegister::select
void select(bool second)
Definition: uart8250.hh:128
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::EventFunctionWrapper
Definition: eventq.hh:1115
gem5::Uart8250::Registers::RWSwitchedRegister::write
void write(const void *buf, off_t offset, size_t bytes) override
Definition: uart8250.hh:163
gem5::Uart8250::Registers::RWSwitchedRegister
Definition: uart8250.hh:150
gem5::Uart8250::Register8
Registers::Register8 Register8
Definition: uart8250.hh:196
gem5::Uart8250::Registers::BankedRegister::read
void read(void *buf) override
Definition: uart8250.hh:136
gem5::Uart8250::intStatus
virtual bool intStatus()
Return if we have an interrupt pending.
Definition: uart8250.hh:233
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:203
gem5::Uart8250::EndBitUnion
EndBitUnion(Ier) BitUnion8(Iir) Bitfield< 0 > pending
gem5::Uart8250::Registers::PairedRegister::_reg2
RegisterBase & _reg2
Definition: uart8250.hh:102
gem5::Uart8250::parityError
Bitfield< 2 > parityError
Definition: uart8250.hh:78
gem5::Uart8250::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: uart8250.cc:263
gem5::RegisterBank< ByteOrder::little >::name
const std::string & name() const
Definition: reg_bank.hh:824
gem5::X86ISA::os
Bitfield< 17 > os
Definition: misc.hh:809
gem5::Uart8250::Registers::sr
RegisterRaz sr
Definition: uart8250.hh:194
gem5::Uart8250::framingError
Bitfield< 3 > framingError
Definition: uart8250.hh:79
gem5::Uart8250::Registers::rbrThrDll
BankedRegister rbrThrDll
Definition: uart8250.hh:175
gem5::Uart8250::processIntrEvent
void processIntrEvent(int intrBit)
Definition: uart8250.cc:50
gem5::Uart8250::Registers::lsr
Register< Lsr > lsr
Definition: uart8250.hh:190
gem5::RegisterBank< ByteOrder::little >
gem5::Uart8250::rxIntrEvent
EventFunctionWrapper rxIntrEvent
Definition: uart8250.hh:213
logging.hh
gem5::Uart8250::Registers::rbrThr
RWSwitchedRegister rbrThr
Definition: uart8250.hh:172
gem5::Uart8250::Registers::RWSwitchedRegister::write
void write(const void *buf) override
Definition: uart8250.hh:161
gem5::Uart8250::Registers::PairedRegister::unserialize
bool unserialize(const std::string &s) override
Definition: uart8250.hh:115
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::Uart8250::Registers::ier
Register< Ier > ier
Definition: uart8250.hh:178
gem5::Uart8250::read
Tick read(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: uart8250.cc:217
gem5::Uart8250::Registers::mcr
Register8 mcr
Definition: uart8250.hh:189
std::list< AddrRange >
gem5::Uart8250::Registers::PairedRegister::_reg1
RegisterBase & _reg1
Definition: uart8250.hh:102
gem5::Uart8250::txIntrEvent
EventFunctionWrapper txIntrEvent
Definition: uart8250.hh:212
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::Uart8250::readRbr
uint8_t readRbr(Register8 &reg)
Definition: uart8250.cc:132
gem5::Uart8250::Registers::PairedRegister
Definition: uart8250.hh:99
reg_bank.hh
gem5::Uart8250::Registers::lcr
Register< Lcr > lcr
Definition: uart8250.hh:188

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