gem5  v19.0.0.0
All Classes Namespaces Files Functions Variables Typedefs Enumerations Enumerator Friends Macros Modules Pages
process.cc
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2003-2004 The Regents of The University of Michigan
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are
7  * met: redistributions of source code must retain the above copyright
8  * notice, this list of conditions and the following disclaimer;
9  * redistributions in binary form must reproduce the above copyright
10  * notice, this list of conditions and the following disclaimer in the
11  * documentation and/or other materials provided with the distribution;
12  * neither the name of the copyright holders nor the names of its
13  * contributors may be used to endorse or promote products derived from
14  * this software without specific prior written permission.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27  *
28  * Authors: Gabe Black
29  * Ali Saidi
30  */
31 
32 #include "arch/alpha/process.hh"
33 
34 #include "arch/alpha/isa_traits.hh"
37 #include "base/logging.hh"
38 #include "cpu/thread_context.hh"
39 #include "debug/Loader.hh"
40 #include "mem/page_table.hh"
41 #include "params/Process.hh"
42 #include "sim/aux_vector.hh"
43 #include "sim/byteswap.hh"
44 #include "sim/process_impl.hh"
45 #include "sim/syscall_return.hh"
46 #include "sim/system.hh"
47 
48 using namespace AlphaISA;
49 using namespace std;
50 
51 AlphaProcess::AlphaProcess(ProcessParams *params, ObjectFile *objFile)
52  : Process(params,
53  new EmulationPageTable(params->name, params->pid, PageBytes),
54  objFile)
55 {
56  fatal_if(params->useArchPT, "Arch page tables not implemented.");
57  Addr brk_point = roundUp(image.maxAddr(), PageBytes);
58 
59  // Set up stack. On Alpha, stack goes below the image.
60  Addr stack_base = image.minAddr() - (409600 + 4096);
61 
62  // Set up region for mmaps.
63  Addr mmap_end = 0x10000;
64 
65  Addr max_stack_size = 8 * 1024 * 1024;
66 
67  // Set pointer for next thread stack. Reserve 8M for main stack.
68  Addr next_thread_stack_base = stack_base - max_stack_size;
69 
70  memState = make_shared<MemState>(brk_point, stack_base, max_stack_size,
71  next_thread_stack_base, mmap_end);
72 }
73 
74 void
75 AlphaProcess::argsInit(int intSize, int pageSize)
76 {
78 
79  ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile);
80  if (elfObject)
81  {
82  // modern glibc uses a bunch of auxiliary vectors to set up
83  // TLS as well as do a bunch of other stuff
84  // these vectors go on the bottom of the stack, below argc/argv/envp
85  // pointers but above actual arg strings
86  // I don't have all the ones glibc looks at here, but so far it doesn't
87  // seem to be a problem.
88  // check out _dl_aux_init() in glibc/elf/dl-support.c for details
89  // --Lisa
90  auxv.emplace_back(M5_AT_PAGESZ, AlphaISA::PageBytes);
91  auxv.emplace_back(M5_AT_CLKTCK, 100);
92  auxv.emplace_back(M5_AT_PHDR, elfObject->programHeaderTable());
93  DPRINTF(Loader, "auxv at PHDR %08p\n",
94  elfObject->programHeaderTable());
95  auxv.emplace_back(M5_AT_PHNUM, elfObject->programHeaderCount());
96  // This is the base address of the ELF interpreter; it should be
97  // zero for static executables or contain the base address for
98  // dynamic executables.
99  auxv.emplace_back(M5_AT_BASE, getBias());
100  auxv.emplace_back(M5_AT_ENTRY, objFile->entryPoint());
101  auxv.emplace_back(M5_AT_UID, uid());
102  auxv.emplace_back(M5_AT_EUID, euid());
103  auxv.emplace_back(M5_AT_GID, gid());
104  auxv.emplace_back(M5_AT_EGID, egid());
105 
106  }
107 
108  // Calculate how much space we need for arg & env & auxv arrays.
109  int argv_array_size = intSize * (argv.size() + 1);
110  int envp_array_size = intSize * (envp.size() + 1);
111  int auxv_array_size = intSize * 2 * (auxv.size() + 1);
112 
113  int arg_data_size = 0;
114  for (vector<string>::size_type i = 0; i < argv.size(); ++i) {
115  arg_data_size += argv[i].size() + 1;
116  }
117  int env_data_size = 0;
118  for (vector<string>::size_type i = 0; i < envp.size(); ++i) {
119  env_data_size += envp[i].size() + 1;
120  }
121 
122  int space_needed =
123  argv_array_size +
124  envp_array_size +
125  auxv_array_size +
126  arg_data_size +
127  env_data_size;
128 
129  if (space_needed < 32*1024)
130  space_needed = 32*1024;
131 
132  // set bottom of stack
133  memState->setStackMin(memState->getStackBase() - space_needed);
134  // align it
135  memState->setStackMin(roundDown(memState->getStackMin(), pageSize));
136  memState->setStackSize(memState->getStackBase() - memState->getStackMin());
137  // map memory
138  allocateMem(memState->getStackMin(), roundUp(memState->getStackSize(),
139  pageSize));
140 
141  // map out initial stack contents
142  Addr argv_array_base = memState->getStackMin() + intSize; // room for argc
143  Addr envp_array_base = argv_array_base + argv_array_size;
144  Addr auxv_array_base = envp_array_base + envp_array_size;
145  Addr arg_data_base = auxv_array_base + auxv_array_size;
146  Addr env_data_base = arg_data_base + arg_data_size;
147 
148  // write contents to stack
149  uint64_t argc = argv.size();
150  if (intSize == 8)
151  argc = htole((uint64_t)argc);
152  else if (intSize == 4)
153  argc = htole((uint32_t)argc);
154  else
155  panic("Unknown int size");
156 
157  initVirtMem.writeBlob(memState->getStackMin(), &argc, intSize);
158 
159  copyStringArray(argv, argv_array_base, arg_data_base,
161  copyStringArray(envp, envp_array_base, env_data_base,
163 
164  //Copy the aux stuff
165  Addr auxv_array_end = auxv_array_base;
166  for (const auto &aux: auxv) {
167  initVirtMem.write(auxv_array_end, aux, GuestByteOrder);
168  auxv_array_end += sizeof(aux);
169  }
170 
172 
173  tc->setIntReg(FirstArgumentReg, argc);
174  tc->setIntReg(FirstArgumentReg + 1, argv_array_base);
175  tc->setIntReg(StackPointerReg, memState->getStackMin());
176 
177  tc->pcState(getStartPC());
178 }
179 
180 void
182 {
184  tc->setMiscRegNoEffect(IPR_DTB_ASN, _pid << 57);
185 }
186 
187 
188 void
190 {
192  // need to set up ASN after unserialization since _pid value may
193  // come from checkpoint
194  setupASNReg();
195 }
196 
197 
198 void
200 {
201  // need to set up ASN before further initialization since init
202  // will involve writing to virtual memory addresses
203  setupASNReg();
204 
206 
208 
210  tc->setIntReg(GlobalPointerReg, 0);
211  //Operate in user mode
214  //No super page mapping
216 }
217 
218 RegVal
220 {
221  assert(i < 6);
222  return tc->readIntReg(FirstArgumentReg + i++);
223 }
224 
225 void
227 {
228  // check for error condition. Alpha syscall convention is to
229  // indicate success/failure in reg a3 (r19) and put the
230  // return value itself in the standard return value reg (v0).
231  if (sysret.successful()) {
232  // no error
234  tc->setIntReg(ReturnValueReg, sysret.returnValue());
235  } else {
236  // got an error, return details
238  tc->setIntReg(ReturnValueReg, sysret.errnoValue());
239  }
240 }
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:167
#define DPRINTF(x,...)
Definition: trace.hh:229
ObjectFile * objFile
Definition: process.hh:217
Addr programHeaderTable()
Definition: elf_object.hh:128
const std::string & name()
Definition: trace.cc:54
Bitfield< 7 > i
virtual TheISA::PCState pcState() const =0
virtual RegVal readIntReg(RegIndex reg_idx) const =0
bool successful() const
Was the system call successful?
std::vector< ContextID > contextIds
Definition: process.hh:167
virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val)=0
void allocateMem(Addr vaddr, int64_t size, bool clobber=false)
Definition: process.cc:333
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: process.cc:405
SETranslatingPortProxy initVirtMem
Definition: process.hh:183
uint64_t uid()
Definition: process.hh:87
RegVal getSyscallArg(ThreadContext *tc, int &i) override
Definition: process.cc:219
uint64_t RegVal
Definition: types.hh:168
Overload hash function for BasicBlockRange type.
Definition: vec_reg.hh:586
void initState() override
initState() is called on each SimObject when not restoring from a checkpoint.
Definition: process.cc:307
Definition: cprintf.cc:42
T roundUp(const T &val, const U &align)
This function is used to align addresses in memory.
Definition: intmath.hh:168
std::shared_ptr< MemState > memState
Definition: process.hh:283
ThreadContext is the external interface to all thread state for anything outside of the CPU...
int errnoValue() const
The errno value.
const ByteOrder GuestByteOrder
Definition: isa_traits.hh:42
STL vector class.
Definition: stl.hh:40
ThreadContext * getThreadContext(ContextID tid) const
Definition: system.hh:194
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: process.cc:189
Addr minAddr() const
T htole(T value)
Definition: byteswap.hh:144
void writeBlob(Addr addr, const void *p, int size) const
Same as tryWriteBlob, but insists on success.
Definition: port_proxy.hh:189
uint64_t _pid
Definition: process.hh:272
Addr maxAddr() const
void copyStringArray(std::vector< std::string > &strings, AddrType array_ptr, AddrType data_ptr, const ByteOrder bo, PortProxy &memProxy)
Definition: process_impl.hh:43
uint64_t euid()
Definition: process.hh:88
Addr getStartPC()
Definition: process.cc:532
System * system
Definition: process.hh:170
#define fatal_if(cond,...)
Conditional fatal macro that checks the supplied condition and only causes a fatal error if the condi...
Definition: logging.hh:203
const RegIndex StackPointerReg
Definition: registers.hh:77
T roundDown(const T &val, const U &align)
This function is used to align addresses in memory.
Definition: intmath.hh:185
std::vector< std::string > envp
Definition: process.hh:221
virtual void setIntReg(RegIndex reg_idx, RegVal val)=0
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
int64_t returnValue() const
The return value.
const Addr PageBytes
Definition: isa_traits.hh:47
AlphaProcess(ProcessParams *params, ObjectFile *objFile)
Definition: process.cc:51
const int MachineBytes
Definition: isa_traits.hh:107
Declarations of a non-full system Page Table.
uint16_t programHeaderCount()
Definition: elf_object.hh:130
static const int FirstArgumentReg
Definition: process.cc:54
void setSyscallReturn(ThreadContext *tc, SyscallReturn return_value) override
Definition: process.cc:226
void argsInit(int intSize, int pageSize)
Definition: process.cc:75
Addr entryPoint() const
Definition: object_file.hh:131
uint64_t gid()
Definition: process.hh:89
void setupASNReg()
Definition: process.cc:181
void write(Addr address, const T &data) const
Write object T to address.
Definition: port_proxy.hh:293
const RegIndex ReturnValueReg
Definition: registers.hh:81
std::vector< std::string > argv
Definition: process.hh:220
This class represents the return value from an emulated system call, including any errno setting...
Each instance of a Loader subclass will have a chance to try to load an object file when tryLoaders i...
Definition: process.hh:191
const RegIndex GlobalPointerReg
Definition: registers.hh:78
const RegIndex SyscallSuccessReg
Definition: registers.hh:87
void initState() override
initState() is called on each SimObject when not restoring from a checkpoint.
Definition: process.cc:199
Addr getBias()
Definition: process.cc:524
MemoryImage image
Definition: process.hh:218
uint64_t egid()
Definition: process.hh:90

Generated on Fri Feb 28 2020 16:26:56 for gem5 by doxygen 1.8.13