gem5  v19.0.0.0
All Classes Namespaces Files Functions Variables Typedefs Enumerations Enumerator Friends Macros Modules Pages
base_cpu.cc
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2012, 2015, 2017 ARM Limited
3  * All rights reserved
4  *
5  * The license below extends only to copyright in the software and shall
6  * not be construed as granting a license to any other intellectual
7  * property including but not limited to intellectual property relating
8  * to a hardware implementation of the functionality of the software
9  * licensed hereunder. You may use the software subject to the license
10  * terms below provided that you ensure that this notice is replicated
11  * unmodified and in its entirety in all distributions of the software,
12  * modified or unmodified, in source code or in binary form.
13  *
14  * Redistribution and use in source and binary forms, with or without
15  * modification, are permitted provided that the following conditions are
16  * met: redistributions of source code must retain the above copyright
17  * notice, this list of conditions and the following disclaimer;
18  * redistributions in binary form must reproduce the above copyright
19  * notice, this list of conditions and the following disclaimer in the
20  * documentation and/or other materials provided with the distribution;
21  * neither the name of the copyright holders nor the names of its
22  * contributors may be used to endorse or promote products derived from
23  * this software without specific prior written permission.
24  *
25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36  *
37  * Authors: Andreas Sandberg
38  */
39 
40 #include "arch/arm/kvm/base_cpu.hh"
41 
42 #include <linux/kvm.h>
43 
44 #include "arch/arm/interrupts.hh"
45 #include "debug/KvmInt.hh"
46 #include "params/BaseArmKvmCPU.hh"
47 
48 #define INTERRUPT_ID(type, vcpu, irq) ( \
49  ((type) << KVM_ARM_IRQ_TYPE_SHIFT) | \
50  ((vcpu) << KVM_ARM_IRQ_VCPU_SHIFT) | \
51  ((irq) << KVM_ARM_IRQ_NUM_SHIFT))
52 
53 #define INTERRUPT_VCPU_IRQ(vcpu) \
54  INTERRUPT_ID(KVM_ARM_IRQ_TYPE_CPU, vcpu, KVM_ARM_IRQ_CPU_IRQ)
55 
56 #define INTERRUPT_VCPU_FIQ(vcpu) \
57  INTERRUPT_ID(KVM_ARM_IRQ_TYPE_CPU, vcpu, KVM_ARM_IRQ_CPU_FIQ)
58 
59 
60 BaseArmKvmCPU::BaseArmKvmCPU(BaseArmKvmCPUParams *params)
61  : BaseKvmCPU(params),
62  irqAsserted(false), fiqAsserted(false)
63 {
64 }
65 
67 {
68 }
69 
70 void
72 {
74 
75  /* TODO: This needs to be moved when we start to support VMs with
76  * multiple threads since kvmArmVCpuInit requires that all CPUs in
77  * the VM have been created.
78  */
79  struct kvm_vcpu_init target_config;
80  memset(&target_config, 0, sizeof(target_config));
81 
82  vm.kvmArmPreferredTarget(target_config);
83  if (!((ArmSystem *)system)->highestELIs64()) {
84  target_config.features[0] |= (1 << KVM_ARM_VCPU_EL1_32BIT);
85  }
86  kvmArmVCpuInit(target_config);
87 }
88 
89 Tick
91 {
92  auto interrupt = static_cast<ArmISA::Interrupts *>(interrupts[0]);
93  const bool simFIQ(interrupt->checkRaw(INT_FIQ));
94  const bool simIRQ(interrupt->checkRaw(INT_IRQ));
95 
96  if (!vm.hasKernelIRQChip()) {
97  if (fiqAsserted != simFIQ) {
98  DPRINTF(KvmInt, "KVM: Update FIQ state: %i\n", simFIQ);
100  }
101  if (irqAsserted != simIRQ) {
102  DPRINTF(KvmInt, "KVM: Update IRQ state: %i\n", simIRQ);
104  }
105  } else {
106  warn_if(simFIQ && !fiqAsserted,
107  "FIQ raised by the simulated interrupt controller " \
108  "despite in-kernel GIC emulation. This is probably a bug.");
109 
110  warn_if(simIRQ && !irqAsserted,
111  "IRQ raised by the simulated interrupt controller " \
112  "despite in-kernel GIC emulation. This is probably a bug.");
113  }
114 
115  irqAsserted = simIRQ;
116  fiqAsserted = simFIQ;
117 
118  return BaseKvmCPU::kvmRun(ticks);
119 }
120 
123 {
124  // Do we need to request a list of registers from the kernel?
125  if (_regIndexList.size() == 0) {
126  // Start by probing for the size of the list. We do this
127  // calling the ioctl with a struct size of 0. The kernel will
128  // return the number of elements required to hold the list.
129  kvm_reg_list regs_probe;
130  regs_probe.n = 0;
131  getRegList(regs_probe);
132 
133  // Request the actual register list now that we know how many
134  // register we need to allocate space for.
135  std::unique_ptr<struct kvm_reg_list> regs;
136  const size_t size(sizeof(struct kvm_reg_list) +
137  regs_probe.n * sizeof(uint64_t));
138  regs.reset((struct kvm_reg_list *)operator new(size));
139  regs->n = regs_probe.n;
140  if (!getRegList(*regs))
141  panic("Failed to determine register list size.\n");
142 
143  _regIndexList.assign(regs->reg, regs->reg + regs->n);
144  }
145 
146  return _regIndexList;
147 }
148 
149 void
150 BaseArmKvmCPU::kvmArmVCpuInit(const struct kvm_vcpu_init &init)
151 {
152  if (ioctl(KVM_ARM_VCPU_INIT, (void *)&init) == -1)
153  panic("KVM: Failed to initialize vCPU\n");
154 }
155 
156 bool
157 BaseArmKvmCPU::getRegList(struct kvm_reg_list &regs) const
158 {
159  if (ioctl(KVM_GET_REG_LIST, (void *)&regs) == -1) {
160  if (errno == E2BIG) {
161  return false;
162  } else {
163  panic("KVM: Failed to get vCPU register list (errno: %i)\n",
164  errno);
165  }
166  } else {
167  return true;
168  }
169 }
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:167
#define DPRINTF(x,...)
Definition: trace.hh:229
void kvmArmVCpuInit(const struct kvm_vcpu_init &init)
Tell the kernel to initialize this CPU.
Definition: base_cpu.cc:150
BaseArmKvmCPU(BaseArmKvmCPUParams *params)
Definition: base_cpu.cc:60
std::vector< BaseInterrupts * > interrupts
Definition: base.hh:222
virtual Tick kvmRun(Tick ticks)
Request KVM to run the guest for a given number of ticks.
Definition: base.cc:724
bool hasKernelIRQChip() const
Is in-kernel IRQ chip emulation enabled?
Definition: vm.hh:353
System * system
Definition: base.hh:386
Base class for KVM based CPU models.
Definition: base.hh:79
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: base.cc:109
void setIRQLine(uint32_t irq, bool high)
Set the status of an IRQ line using KVM_IRQ_LINE.
Definition: vm.cc:502
const long vcpuID
KVM internal ID of the vCPU.
Definition: base.hh:638
void startup() override
startup() is the final initialization call before simulation.
Definition: base_cpu.cc:71
#define INTERRUPT_VCPU_IRQ(vcpu)
Definition: base_cpu.cc:53
const RegIndexVector & getRegList() const
Get a list of registers supported by getOneReg() and setOneReg().
Definition: base_cpu.cc:122
KvmVM & vm
Definition: base.hh:153
RegIndexVector _regIndexList
Cached copy of the list of registers supported by KVM.
Definition: base_cpu.hh:108
uint64_t Tick
Tick count type.
Definition: types.hh:63
#define warn_if(cond,...)
Conditional warning macro that checks the supplied condition and only prints a warning if the conditi...
Definition: logging.hh:228
Tick kvmRun(Tick ticks) override
Request KVM to run the guest for a given number of ticks.
Definition: base_cpu.cc:90
#define INTERRUPT_VCPU_FIQ(vcpu)
Definition: base_cpu.cc:56
bool irqAsserted
Cached state of the IRQ line.
Definition: base_cpu.hh:62
int ioctl(int request, long p1) const
vCPU ioctl interface.
Definition: base.cc:1174
void startup() override
startup() is the final initialization call before simulation.
Definition: base.cc:120
bool fiqAsserted
Cached state of the FIQ line.
Definition: base_cpu.hh:64
virtual ~BaseArmKvmCPU()
Definition: base_cpu.cc:66

Generated on Fri Feb 28 2020 16:26:57 for gem5 by doxygen 1.8.13