base.hh

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/*
 * Copyright (c) 2012 ARM Limited
 * All rights reserved
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 * Authors: Andreas Sandberg
 */

#ifndef __CPU_KVM_BASE_HH__
#define __CPU_KVM_BASE_HH__

#include <pthread.h>

#include <csignal>
#include <memory>
#include <queue>

#include "base/statistics.hh"
#include "cpu/kvm/perfevent.hh"
#include "cpu/kvm/timer.hh"
#include "cpu/kvm/vm.hh"
#include "cpu/base.hh"
#include "cpu/simple_thread.hh"
#include "sim/faults.hh"

#define KVM_KICK_SIGNAL SIGRTMIN

// forward declarations
class ThreadContext;
struct BaseKvmCPUParams;

class BaseKvmCPU : public BaseCPU
{
  public:
    BaseKvmCPU(BaseKvmCPUParams *params);
    virtual ~BaseKvmCPU();

    void init() override;
    void startup() override;
    void regStats() override;

    void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
    void unserializeThread(CheckpointIn &cp, ThreadID tid) override;

    DrainState drain() override;
    void drainResume() override;
    void notifyFork() override;

    void switchOut() override;
    void takeOverFrom(BaseCPU *cpu) override;

    void verifyMemoryMode() const override;

    Port &getDataPort() override { return dataPort; }
    Port &getInstPort() override { return instPort; }

    void wakeup(ThreadID tid = 0) override;
    void activateContext(ThreadID thread_num) override;
    void suspendContext(ThreadID thread_num) override;
    void deallocateContext(ThreadID thread_num);
    void haltContext(ThreadID thread_num) override;

    long getVCpuID() const { return vcpuID; }
    ThreadContext *getContext(int tn) override;

    Counter totalInsts() const override;
    Counter totalOps() const override;

    void finishMMIOPending();

    virtual void dump() const;

    void kick() const { pthread_kill(vcpuThread, KVM_KICK_SIGNAL); }

    SimpleThread *thread;

    ThreadContext *tc;

    KvmVM &vm;

  protected:
    enum Status {
        Idle,
        Running,
        RunningService,
        RunningMMIOPending,
        RunningServiceCompletion,
    };

    Status _status;

    void tick();

    virtual uint64_t getHostCycles() const;

    virtual Tick kvmRun(Tick ticks);

    virtual Tick kvmRunDrain();

    struct kvm_run *getKvmRunState() { return _kvmRun; };

    uint8_t *getGuestData(uint64_t offset) const {
        return (uint8_t *)_kvmRun + offset;
    };

    void kvmNonMaskableInterrupt();

    void kvmInterrupt(const struct kvm_interrupt &interrupt);

    void getRegisters(struct kvm_regs &regs) const;
    void setRegisters(const struct kvm_regs &regs);
    void getSpecialRegisters(struct kvm_sregs &regs) const;
    void setSpecialRegisters(const struct kvm_sregs &regs);
    void getFPUState(struct kvm_fpu &state) const;
    void setFPUState(const struct kvm_fpu &state);
    void setOneReg(uint64_t id, const void *addr);
    void setOneReg(uint64_t id, uint64_t value) { setOneReg(id, &value); }
    void setOneReg(uint64_t id, uint32_t value) { setOneReg(id, &value); }
    void getOneReg(uint64_t id, void *addr) const;
    uint64_t getOneRegU64(uint64_t id) const {
        uint64_t value;
        getOneReg(id, &value);
        return value;
    }
    uint32_t getOneRegU32(uint64_t id) const {
        uint32_t value;
        getOneReg(id, &value);
        return value;
    }
    std::string getAndFormatOneReg(uint64_t id) const;

    virtual void updateKvmState() = 0;

    virtual void updateThreadContext() = 0;

    void syncThreadContext();

    EventQueue *deviceEventQueue() { return vm.eventQueue(); }

    void syncKvmState();
    virtual Tick handleKvmExit();

    virtual Tick handleKvmExitIO();

    virtual Tick handleKvmExitHypercall();

    virtual Tick handleKvmExitIRQWindowOpen();

    virtual Tick handleKvmExitUnknown();

    virtual Tick handleKvmExitException();

    virtual Tick handleKvmExitFailEntry();
    virtual bool archIsDrained() const { return true; }

    Tick doMMIOAccess(Addr paddr, void *data, int size, bool write);

    void setSignalMask(const sigset_t *mask);
    int ioctl(int request, long p1) const;
    int ioctl(int request, void *p1) const {
        return ioctl(request, (long)p1);
    }
    int ioctl(int request) const {
        return ioctl(request, 0L);
    }
    class KVMCpuPort : public MasterPort
    {

      public:
        KVMCpuPort(const std::string &_name, BaseKvmCPU *_cpu)
            : MasterPort(_name, _cpu), cpu(_cpu), activeMMIOReqs(0)
        { }
        Tick submitIO(PacketPtr pkt);

        Status nextIOState() const;

      protected:
        BaseKvmCPU *cpu;

        std::queue<PacketPtr> pendingMMIOPkts;

        unsigned int activeMMIOReqs;

        bool recvTimingResp(PacketPtr pkt) override;

        void recvReqRetry() override;

    };

    KVMCpuPort dataPort;

    KVMCpuPort instPort;

    const bool alwaysSyncTC;

    bool threadContextDirty;

    bool kvmStateDirty;

    const long vcpuID;

    pthread_t vcpuThread;

  private:
    Tick flushCoalescedMMIO();

    void setupSignalHandler();

    bool discardPendingSignal(int signum) const;

    void startupThread();

    bool tryDrain();

    void ioctlRun();

    int vcpuFD;
    int vcpuMMapSize;
    struct kvm_run *_kvmRun;
    struct kvm_coalesced_mmio_ring *mmioRing;
    const long pageSize;

    EventFunctionWrapper tickEvent;

    void setupInstStop();

    void setupCounters();

    void setupInstCounter(uint64_t period = 0);

    uint64_t activeInstPeriod;

    PerfKvmCounter hwCycles;

    PerfKvmCounter hwInstructions;

    bool perfControlledByTimer;
    std::unique_ptr<BaseKvmTimer> runTimer;

    float hostFactor;

  public:
    /* @{ */
    Stats::Scalar numInsts;
    Stats::Scalar numVMExits;
    Stats::Scalar numVMHalfEntries;
    Stats::Scalar numExitSignal;
    Stats::Scalar numMMIO;
    Stats::Scalar numCoalescedMMIO;
    Stats::Scalar numIO;
    Stats::Scalar numHalt;
    Stats::Scalar numInterrupts;
    Stats::Scalar numHypercalls;
    /* @} */

    Counter ctrInsts;
};

#endif