bridge.hh

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/*
 * Copyright (c) 2011-2013 ARM Limited
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 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
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 * modified or unmodified, in source code or in binary form.
 *
 * Copyright (c) 2006 The Regents of The University of Michigan
 * All rights reserved.
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 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
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 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * Authors: Ali Saidi
 *          Steve Reinhardt
 *          Andreas Hansson
 */

#ifndef __MEM_BRIDGE_HH__
#define __MEM_BRIDGE_HH__

#include <deque>

#include "base/types.hh"
#include "mem/port.hh"
#include "params/Bridge.hh"
#include "sim/clocked_object.hh"

class Bridge : public ClockedObject
{
  protected:

    class DeferredPacket
    {

      public:

        const Tick tick;
        const PacketPtr pkt;

        DeferredPacket(PacketPtr _pkt, Tick _tick) : tick(_tick), pkt(_pkt)
        { }
    };

    // Forward declaration to allow the slave port to have a pointer
    class BridgeMasterPort;

    class BridgeSlavePort : public SlavePort
    {

      private:

        Bridge& bridge;

        BridgeMasterPort& masterPort;

        const Cycles delay;

        const AddrRangeList ranges;

        std::deque<DeferredPacket> transmitList;

        unsigned int outstandingResponses;

        bool retryReq;

        unsigned int respQueueLimit;

        std::unique_ptr<Packet> pendingDelete;

        bool respQueueFull() const;

        void trySendTiming();

        EventFunctionWrapper sendEvent;

      public:

        BridgeSlavePort(const std::string& _name, Bridge& _bridge,
                        BridgeMasterPort& _masterPort, Cycles _delay,
                        int _resp_limit, std::vector<AddrRange> _ranges);

        void schedTimingResp(PacketPtr pkt, Tick when);

        void retryStalledReq();

      protected:

        bool recvTimingReq(PacketPtr pkt);

        void recvRespRetry();

        Tick recvAtomic(PacketPtr pkt);

        void recvFunctional(PacketPtr pkt);

        AddrRangeList getAddrRanges() const;
    };


    class BridgeMasterPort : public MasterPort
    {

      private:

        Bridge& bridge;

        BridgeSlavePort& slavePort;

        const Cycles delay;

        std::deque<DeferredPacket> transmitList;

        const unsigned int reqQueueLimit;

        void trySendTiming();

        EventFunctionWrapper sendEvent;

      public:

        BridgeMasterPort(const std::string& _name, Bridge& _bridge,
                         BridgeSlavePort& _slavePort, Cycles _delay,
                         int _req_limit);

        bool reqQueueFull() const;

        void schedTimingReq(PacketPtr pkt, Tick when);

        bool trySatisfyFunctional(PacketPtr pkt);

      protected:

        bool recvTimingResp(PacketPtr pkt);

        void recvReqRetry();
    };

    BridgeSlavePort slavePort;

    BridgeMasterPort masterPort;

  public:

    Port &getPort(const std::string &if_name,
                  PortID idx=InvalidPortID) override;

    void init() override;

    typedef BridgeParams Params;

    Bridge(Params *p);
};

#endif //__MEM_BRIDGE_HH__