gem5  v19.0.0.0
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MipsISA Namespace Reference

Namespaces

 Kernel
 

Classes

class  AddressErrorFault
 
class  AddressFault
 
class  BreakpointFault
 
class  CoprocessorUnusableFault
 
struct  CoreSpecific
 
class  Decoder
 
class  DspStateDisabledFault
 
class  IntegerOverflowFault
 
class  InterruptFault
 
class  Interrupts
 
class  ISA
 
class  MachineCheckFault
 
class  MipsFault
 
class  MipsFaultBase
 
class  NonMaskableInterrupt
 
class  ProcessInfo
 
struct  PTE
 
class  RemoteGDB
 
class  ReservedInstructionFault
 
class  ResetFault
 
class  SoftResetFault
 
class  StackTrace
 
class  SystemCallFault
 
class  ThreadFault
 
class  TLB
 
struct  TlbEntry
 
class  TlbFault
 
class  TlbInvalidFault
 
class  TlbModifiedFault
 
class  TlbRefillFault
 
class  TrapFault
 
struct  VAddr
 

Typedefs

typedef MipsFaultBase::FaultVals FaultVals
 
typedef Addr FaultVect
 
using VecElem = ::DummyVecElem
 
using VecReg = ::DummyVecReg
 
using ConstVecReg = ::DummyConstVecReg
 
using VecRegContainer = ::DummyVecRegContainer
 
using VecPredReg = ::DummyVecPredReg
 
using ConstVecPredReg = ::DummyConstVecPredReg
 
using VecPredRegContainer = ::DummyVecPredRegContainer
 
typedef uint32_t MachInst
 
typedef uint64_t ExtMachInst
 
typedef GenericISA::DelaySlotPCState< MachInst > PCState
 

Enumerations

enum  {
  SIMD_FMT_L, SIMD_FMT_W, SIMD_FMT_PH, SIMD_FMT_QB,
  SIMD_NUM_FMTS
}
 
enum  {
  DSP_POS, DSP_SCOUNT, DSP_C, DSP_OUFLAG,
  DSP_CCOND, DSP_EFI, DSP_NUM_FIELDS
}
 
enum  { CMP_EQ, CMP_LT, CMP_LE }
 
enum  {
  MODE_L, MODE_R, MODE_LA, MODE_RA,
  MODE_X
}
 
enum  { UNSIGNED, SIGNED }
 
enum  { NOSATURATE, SATURATE }
 
enum  { NOROUND, ROUND }
 
enum  ExcCode {
  ExcCodeDummy = 0, ExcCodeInt = 0, ExcCodeMod = 1, ExcCodeTlbL = 2,
  ExcCodeTlbS = 3, ExcCodeAdEL = 4, ExcCodeAdES = 5, ExcCodeIBE = 6,
  ExcCodeDBE = 7, ExcCodeSys = 8, ExcCodeBp = 9, ExcCodeRI = 10,
  ExcCodeCpU = 11, ExcCodeOv = 12, ExcCodeTr = 13, ExcCodeC2E = 18,
  ExcCodeMDMX = 22, ExcCodeWatch = 23, ExcCodeMCheck = 24, ExcCodeThread = 25,
  ExcCodeCacheErr = 30
}
 
enum  InterruptLevels {
  INTLEVEL_SOFTWARE_MIN = 4, INTLEVEL_SOFTWARE_MAX = 19, INTLEVEL_EXTERNAL_MIN = 20, INTLEVEL_EXTERNAL_MAX = 34,
  INTLEVEL_IRQ0 = 20, INTLEVEL_IRQ1 = 21, INTINDEX_ETHERNET = 0, INTINDEX_SCSI = 1,
  INTLEVEL_IRQ2 = 22, INTLEVEL_IRQ3 = 23, INTLEVEL_SERIAL = 33, NumInterruptLevels = INTLEVEL_EXTERNAL_MAX
}
 
enum  mode_type {
  mode_kernel = 0, mode_supervisor = 1, mode_user = 2, mode_debug = 3,
  mode_number
}
 
enum  FPControlRegNums {
  FLOATREG_FIR = NumFloatArchRegs, FLOATREG_FCCR, FLOATREG_FEXR, FLOATREG_FENR,
  FLOATREG_FCSR
}
 
enum  FCSRBits {
  Inexact = 1, Underflow, Overflow, DivideByZero,
  Invalid, Unimplemented
}
 
enum  FCSRFields { Flag_Field = 1, Enable_Field = 6, Cause_Field = 11 }
 
enum  MiscIntRegNums {
  INTREG_LO = NumIntArchRegs, INTREG_DSP_LO0 = INTREG_LO, INTREG_HI, INTREG_DSP_HI0 = INTREG_HI,
  INTREG_DSP_ACX0, INTREG_DSP_LO1, INTREG_DSP_HI1, INTREG_DSP_ACX1,
  INTREG_DSP_LO2, INTREG_DSP_HI2, INTREG_DSP_ACX2, INTREG_DSP_LO3,
  INTREG_DSP_HI3, INTREG_DSP_ACX3, INTREG_DSP_CONTROL
}
 
enum  MiscRegIndex {
  MISCREG_INDEX = 0, MISCREG_MVP_CONTROL, MISCREG_MVP_CONF0, MISCREG_MVP_CONF1,
  MISCREG_CP0_RANDOM = 8, MISCREG_VPE_CONTROL, MISCREG_VPE_CONF0, MISCREG_VPE_CONF1,
  MISCREG_YQMASK, MISCREG_VPE_SCHEDULE, MISCREG_VPE_SCHEFBACK, MISCREG_VPE_OPT,
  MISCREG_ENTRYLO0 = 16, MISCREG_TC_STATUS, MISCREG_TC_BIND, MISCREG_TC_RESTART,
  MISCREG_TC_HALT, MISCREG_TC_CONTEXT, MISCREG_TC_SCHEDULE, MISCREG_TC_SCHEFBACK,
  MISCREG_ENTRYLO1 = 24, MISCREG_CONTEXT = 32, MISCREG_CONTEXT_CONFIG, MISCREG_PAGEMASK = 40,
  MISCREG_PAGEGRAIN = 41, MISCREG_WIRED = 48, MISCREG_SRS_CONF0, MISCREG_SRS_CONF1,
  MISCREG_SRS_CONF2, MISCREG_SRS_CONF3, MISCREG_SRS_CONF4, MISCREG_HWRENA = 56,
  MISCREG_BADVADDR = 64, MISCREG_COUNT = 72, MISCREG_ENTRYHI = 80, MISCREG_COMPARE = 88,
  MISCREG_STATUS = 96, MISCREG_INTCTL, MISCREG_SRSCTL, MISCREG_SRSMAP,
  MISCREG_CAUSE = 104, MISCREG_EPC = 112, MISCREG_PRID = 120, MISCREG_EBASE,
  MISCREG_CONFIG = 128, MISCREG_CONFIG1, MISCREG_CONFIG2, MISCREG_CONFIG3,
  MISCREG_CONFIG4, MISCREG_CONFIG5, MISCREG_CONFIG6, MISCREG_CONFIG7,
  MISCREG_LLADDR = 136, MISCREG_WATCHLO0 = 144, MISCREG_WATCHLO1, MISCREG_WATCHLO2,
  MISCREG_WATCHLO3, MISCREG_WATCHLO4, MISCREG_WATCHLO5, MISCREG_WATCHLO6,
  MISCREG_WATCHLO7, MISCREG_WATCHHI0 = 152, MISCREG_WATCHHI1, MISCREG_WATCHHI2,
  MISCREG_WATCHHI3, MISCREG_WATCHHI4, MISCREG_WATCHHI5, MISCREG_WATCHHI6,
  MISCREG_WATCHHI7, MISCREG_XCCONTEXT64 = 160, MISCREG_DEBUG = 184, MISCREG_TRACE_CONTROL1,
  MISCREG_TRACE_CONTROL2, MISCREG_USER_TRACE_DATA, MISCREG_TRACE_BPC, MISCREG_DEPC = 192,
  MISCREG_PERFCNT0 = 200, MISCREG_PERFCNT1, MISCREG_PERFCNT2, MISCREG_PERFCNT3,
  MISCREG_PERFCNT4, MISCREG_PERFCNT5, MISCREG_PERFCNT6, MISCREG_PERFCNT7,
  MISCREG_ERRCTL = 208, MISCREG_CACHEERR0 = 216, MISCREG_CACHEERR1, MISCREG_CACHEERR2,
  MISCREG_CACHEERR3, MISCREG_TAGLO0 = 224, MISCREG_DATALO1, MISCREG_TAGLO2,
  MISCREG_DATALO3, MISCREG_TAGLO4, MISCREG_DATALO5, MISCREG_TAGLO6,
  MISCREG_DATALO7, MISCREG_TAGHI0 = 232, MISCREG_DATAHI1, MISCREG_TAGHI2,
  MISCREG_DATAHI3, MISCREG_TAGHI4, MISCREG_DATAHI5, MISCREG_TAGHI6,
  MISCREG_DATAHI7, MISCREG_ERROR_EPC = 240, MISCREG_DESAVE = 248, MISCREG_LLFLAG = 257,
  MISCREG_TP_VALUE, MISCREG_NUMREGS
}
 
enum  ConvertType {
  SINGLE_TO_DOUBLE, SINGLE_TO_WORD, SINGLE_TO_LONG, DOUBLE_TO_SINGLE,
  DOUBLE_TO_WORD, DOUBLE_TO_LONG, LONG_TO_SINGLE, LONG_TO_DOUBLE,
  LONG_TO_WORD, LONG_TO_PS, WORD_TO_SINGLE, WORD_TO_DOUBLE,
  WORD_TO_LONG, WORD_TO_PS, PL_TO_SINGLE, PU_TO_SINGLE
}
 
enum  RoundMode { RND_ZERO, RND_DOWN, RND_UP, RND_NEAREST }
 

Functions

int32_t bitrev (int32_t value)
 
uint64_t dspSaturate (uint64_t value, int32_t fmt, int32_t sign, uint32_t *overflow)
 
uint64_t checkOverflow (uint64_t value, int32_t fmt, int32_t sign, uint32_t *overflow)
 
uint64_t signExtend (uint64_t value, int32_t signpos)
 
uint64_t addHalfLsb (uint64_t value, int32_t lsbpos)
 
int32_t dspAbs (int32_t a, int32_t fmt, uint32_t *dspctl)
 
int32_t dspAdd (int32_t a, int32_t b, int32_t fmt, int32_t saturate, int32_t sign, uint32_t *dspctl)
 
int32_t dspAddh (int32_t a, int32_t b, int32_t fmt, int32_t round, int32_t sign)
 
int32_t dspSub (int32_t a, int32_t b, int32_t fmt, int32_t saturate, int32_t sign, uint32_t *dspctl)
 
int32_t dspSubh (int32_t a, int32_t b, int32_t fmt, int32_t round, int32_t sign)
 
int32_t dspShll (int32_t a, uint32_t sa, int32_t fmt, int32_t saturate, int32_t sign, uint32_t *dspctl)
 
int32_t dspShrl (int32_t a, uint32_t sa, int32_t fmt, int32_t sign)
 
int32_t dspShra (int32_t a, uint32_t sa, int32_t fmt, int32_t round, int32_t sign, uint32_t *dspctl)
 
int32_t dspMul (int32_t a, int32_t b, int32_t fmt, int32_t saturate, uint32_t *dspctl)
 
int32_t dspMulq (int32_t a, int32_t b, int32_t fmt, int32_t saturate, int32_t round, uint32_t *dspctl)
 
int32_t dspMuleu (int32_t a, int32_t b, int32_t mode, uint32_t *dspctl)
 
int32_t dspMuleq (int32_t a, int32_t b, int32_t mode, uint32_t *dspctl)
 
int64_t dspDpaq (int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t infmt, int32_t outfmt, int32_t postsat, int32_t mode, uint32_t *dspctl)
 
int64_t dspDpsq (int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t infmt, int32_t outfmt, int32_t postsat, int32_t mode, uint32_t *dspctl)
 
int64_t dspDpa (int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt, int32_t sign, int32_t mode)
 
int64_t dspDps (int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt, int32_t sign, int32_t mode)
 
int64_t dspMaq (int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt, int32_t mode, int32_t saturate, uint32_t *dspctl)
 
int64_t dspMulsa (int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt)
 
int64_t dspMulsaq (int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt, uint32_t *dspctl)
 
void dspCmp (int32_t a, int32_t b, int32_t fmt, int32_t sign, int32_t op, uint32_t *dspctl)
 
int32_t dspCmpg (int32_t a, int32_t b, int32_t fmt, int32_t sign, int32_t op)
 
int32_t dspCmpgd (int32_t a, int32_t b, int32_t fmt, int32_t sign, int32_t op, uint32_t *dspctl)
 
int32_t dspPrece (int32_t a, int32_t infmt, int32_t insign, int32_t outfmt, int32_t outsign, int32_t mode)
 
int32_t dspPrecrqu (int32_t a, int32_t b, uint32_t *dspctl)
 
int32_t dspPrecrq (int32_t a, int32_t b, int32_t fmt, uint32_t *dspctl)
 
int32_t dspPrecrSra (int32_t a, int32_t b, int32_t sa, int32_t fmt, int32_t round)
 
int32_t dspPick (int32_t a, int32_t b, int32_t fmt, uint32_t *dspctl)
 
int32_t dspPack (int32_t a, int32_t b, int32_t fmt)
 
int32_t dspExtr (int64_t dspac, int32_t fmt, int32_t sa, int32_t round, int32_t saturate, uint32_t *dspctl)
 
int32_t dspExtp (int64_t dspac, int32_t size, uint32_t *dspctl)
 
int32_t dspExtpd (int64_t dspac, int32_t size, uint32_t *dspctl)
 
void simdPack (uint64_t *values_ptr, int32_t *reg, int32_t fmt)
 
void simdUnpack (int32_t reg, uint64_t *values_ptr, int32_t fmt, int32_t sign)
 
void writeDSPControl (uint32_t *dspctl, uint32_t value, uint32_t mask)
 
uint32_t readDSPControl (uint32_t *dspctl, uint32_t mask)
 
 BitUnion32 (DebugReg) Bitfield< 31 > dbd
 
 SubBitUnion (ejtagVer, 17, 15) Bitfield< 17 > ejtagVer2
 
 EndSubBitUnion (ejtagVer) Bitfield< 14
 
 EndBitUnion (DebugReg) BitUnion32(TraceControlReg) Bitfield< 31 > ts
 
 EndBitUnion (TraceControlReg) BitUnion32(TraceControl2Reg) Bitfield< 29 > cpuidv
 
 EndBitUnion (TraceControl2Reg) BitUnion32(TraceBPCReg) Bitfield< 31 > mb
 
 EndBitUnion (TraceBPCReg) BitUnion32(TraceBPC2Reg) Bitfield< 17
 
 EndBitUnion (TraceBPC2Reg) BitUnion32(Debug2Reg) Bitfield< 3 > prm
 
static uint8_t getCauseIP (ThreadContext *tc)
 
static void setCauseIP (ThreadContext *tc, uint8_t val)
 
StaticInstPtr decodeInst (ExtMachInst)
 
Addr Phys2K0Seg (Addr addr)
 
Addr VAddrImpl (Addr a)
 
Addr VAddrVPN (Addr a)
 
Addr VAddrOffset (Addr a)
 
template<class XC >
void handleLockedSnoop (XC *xc, PacketPtr pkt, Addr cacheBlockMask)
 
template<class XC >
void handleLockedRead (XC *xc, const RequestPtr &req)
 
template<class XC >
void handleLockedSnoopHit (XC *xc)
 
template<class XC >
bool handleLockedWrite (XC *xc, const RequestPtr &req, Addr cacheBlockMask)
 
template<class XC >
void globalClearExclusive (XC *xc)
 
Cycles handleIprRead (ThreadContext *, Packet *)
 
Cycles handleIprWrite (ThreadContext *, Packet *)
 
static RegVal readRegOtherThread (ThreadContext *tc, const RegId &reg, ThreadID tid=InvalidThreadID)
 
static void setRegOtherThread (ThreadContext *tc, const RegId &reg, RegVal val, ThreadID tid=InvalidThreadID)
 
static RegVal readRegOtherThread (ExecContext *xc, const RegId &reg, ThreadID tid=InvalidThreadID)
 
static void setRegOtherThread (ExecContext *xc, const RegId &reg, RegVal val, ThreadID tid=InvalidThreadID)
 
template<class TC >
unsigned getVirtProcNum (TC *tc)
 
template<class TC >
unsigned getTargetThread (TC *tc)
 
template<class TC >
void haltThread (TC *tc)
 
template<class TC >
void restoreThread (TC *tc)
 
template<class TC >
void forkThread (TC *tc, Fault &fault, int Rd_bits, int Rs, int Rt)
 
template<class TC >
int yieldThread (TC *tc, Fault &fault, int src_reg, uint32_t yield_mask)
 
template<class TC >
void updateStatusView (TC *tc)
 
template<class TC >
void updateTCStatusView (TC *tc)
 
 BitUnion32 (MVPControlReg) Bitfield< 3 > cpa
 
 EndBitUnion (MVPControlReg) BitUnion32(MVPConf0Reg) Bitfield< 31 > m
 
 EndBitUnion (MVPConf0Reg) BitUnion32(VPEControlReg) Bitfield< 21 > ysi
 
 EndBitUnion (VPEControlReg) BitUnion32(VPEConf0Reg) Bitfield< 31 > m
 
 EndBitUnion (VPEConf0Reg) BitUnion32(TCBindReg) Bitfield< 28
 
 EndBitUnion (TCBindReg) BitUnion32(TCStatusReg) Bitfield< 31
 
 EndBitUnion (TCStatusReg) BitUnion32(TCHaltReg) Bitfield< 0 > h
 
 BitUnion32 (IndexReg) Bitfield< 31 > p
 
 EndBitUnion (IndexReg) BitUnion32(RandomReg) Bitfield< 30
 
 EndBitUnion (RandomReg) BitUnion64(EntryLoReg) Bitfield< 63
 
 EndBitUnion (EntryLoReg) BitUnion64(ContextReg) Bitfield< 63
 
 EndBitUnion (ContextReg) BitUnion32(PageMaskReg) Bitfield< 28
 
 EndBitUnion (PageMaskReg) BitUnion32(PageGrainReg) Bitfield< 31
 
 EndBitUnion (PageGrainReg) BitUnion32(WiredReg) Bitfield< 30
 
 EndBitUnion (WiredReg) BitUnion32(HWREnaReg) Bitfield< 31
 
 EndBitUnion (HWREnaReg) BitUnion64(EntryHiReg) Bitfield< 63
 
 EndBitUnion (EntryHiReg) BitUnion32(StatusReg) SubBitUnion(cu
 
 EndSubBitUnion (cu) Bitfield< 27 > rp
 
 SubBitUnion (im, 15, 8) Bitfield< 15 > im7
 
 EndSubBitUnion (im) Bitfield< 7 > kx
 
 EndBitUnion (StatusReg) BitUnion32(IntCtlReg) Bitfield< 31
 
 EndBitUnion (IntCtlReg) BitUnion32(SRSCtlReg) Bitfield< 29
 
 EndBitUnion (SRSCtlReg) BitUnion32(SRSMapReg) Bitfield< 31
 
 EndBitUnion (SRSMapReg) BitUnion32(CauseReg) Bitfield< 31 > bd
 
 SubBitUnion (ip, 15, 8) Bitfield< 15 > ip7
 
 EndSubBitUnion (ip)
 
 EndBitUnion (CauseReg) BitUnion32(PRIdReg) Bitfield< 31
 
 EndBitUnion (PRIdReg) BitUnion32(EBaseReg) Bitfield< 29
 
 EndBitUnion (EBaseReg) BitUnion32(ConfigReg) Bitfield< 31 > m
 
 EndBitUnion (ConfigReg) BitUnion32(Config1Reg) Bitfield< 31 > m
 
 EndBitUnion (Config1Reg) BitUnion32(Config2Reg) Bitfield< 31 > m
 
 EndBitUnion (Config2Reg) BitUnion32(Config3Reg) Bitfield< 31 > m
 
 EndBitUnion (Config3Reg) BitUnion64(WatchLoReg) Bitfield< 63
 
 EndBitUnion (WatchLoReg) BitUnion32(WatchHiReg) Bitfield< 31 > m
 
 EndBitUnion (WatchHiReg) BitUnion32(PerfCntCtlReg) Bitfield< 31 > m
 
 EndBitUnion (PerfCntCtlReg) BitUnion32(CacheErrReg) Bitfield< 31 > er
 
 EndBitUnion (CacheErrReg) BitUnion32(TagLoReg) Bitfield< 31
 
uint64_t getArgument (ThreadContext *tc, int &number, uint16_t size, bool fp)
 
uint64_t fpConvert (ConvertType cvt_type, double fp_val)
 
double roundFP (double val, int digits)
 
double truncFP (double val)
 
bool getCondCode (uint32_t fcsr, int cc_idx)
 
uint32_t genCCVector (uint32_t fcsr, int cc_num, uint32_t cc_val)
 
uint32_t genInvalidVector (uint32_t fcsr_bits)
 
bool isNan (void *val_ptr, int size)
 
bool isQnan (void *val_ptr, int size)
 
bool isSnan (void *val_ptr, int size)
 
void copyRegs (ThreadContext *src, ThreadContext *dest)
 
void copyMiscRegs (ThreadContext *src, ThreadContext *dest)
 
void skipFunction (ThreadContext *tc)
 
PCState buildRetPC (const PCState &curPC, const PCState &callPC)
 
static bool inUserMode (ThreadContext *tc)
 
Addr TruncPage (Addr addr)
 
Addr RoundPage (Addr addr)
 
void advancePC (PCState &pc, const StaticInstPtr &inst)
 
uint64_t getExecutingAsid (ThreadContext *tc)
 
Addr vtophys (Addr vaddr)
 
Addr vtophys (ThreadContext *tc, Addr vaddr)
 

Variables

const uint32_t DSP_CTL_POS [DSP_NUM_FIELDS] = { 0, 7, 13, 16, 24, 14 }
 
const uint32_t DSP_CTL_MASK [DSP_NUM_FIELDS]
 
const uint32_t SIMD_MAX_VALS = 4
 
const uint32_t SIMD_NVALS [SIMD_NUM_FMTS] = { 1, 1, 2, 4 }
 
const uint32_t SIMD_NBITS [SIMD_NUM_FMTS] = { 64, 32, 16, 8 }
 
const uint32_t SIMD_LOG2N [SIMD_NUM_FMTS] = { 6, 5, 4, 3 }
 
const uint64_t FIXED_L_SMAX = ULL(0x7fffffffffffffff)
 
const uint64_t FIXED_W_SMAX = ULL(0x000000007fffffff)
 
const uint64_t FIXED_H_SMAX = ULL(0x0000000000007fff)
 
const uint64_t FIXED_B_SMAX = ULL(0x000000000000007f)
 
const uint64_t FIXED_L_UMAX = ULL(0xffffffffffffffff)
 
const uint64_t FIXED_W_UMAX = ULL(0x00000000ffffffff)
 
const uint64_t FIXED_H_UMAX = ULL(0x000000000000ffff)
 
const uint64_t FIXED_B_UMAX = ULL(0x00000000000000ff)
 
const uint64_t FIXED_SMAX [SIMD_NUM_FMTS]
 
const uint64_t FIXED_UMAX [SIMD_NUM_FMTS]
 
const uint64_t FIXED_L_SMIN = ULL(0x8000000000000000)
 
const uint64_t FIXED_W_SMIN = ULL(0xffffffff80000000)
 
const uint64_t FIXED_H_SMIN = ULL(0xffffffffffff8000)
 
const uint64_t FIXED_B_SMIN = ULL(0xffffffffffffff80)
 
const uint64_t FIXED_L_UMIN = ULL(0x0000000000000000)
 
const uint64_t FIXED_W_UMIN = ULL(0x0000000000000000)
 
const uint64_t FIXED_H_UMIN = ULL(0x0000000000000000)
 
const uint64_t FIXED_B_UMIN = ULL(0x0000000000000000)
 
const uint64_t FIXED_SMIN [SIMD_NUM_FMTS]
 
const uint64_t FIXED_UMIN [SIMD_NUM_FMTS]
 
Bitfield< 30 > dm
 
Bitfield< 29 > nodcr
 
Bitfield< 28 > lsnm
 
Bitfield< 27 > doze
 
Bitfield< 26 > halt
 
Bitfield< 25 > conutdm
 
Bitfield< 24 > ibusep
 
Bitfield< 23 > mcheckep
 
Bitfield< 22 > cacheep
 
Bitfield< 21 > dbusep
 
Bitfield< 20, 19 > iexi
 
Bitfield< 19 > ddbsImpr
 
Bitfield< 18 > ddblImpr
 
Bitfield< 16 > ejtagVer1
 
Bitfield< 15 > ejtagVer0
 
 dexcCode
 
Bitfield< 9 > nosst
 
Bitfield< 8 > sst
 
Bitfield< 7 > offline
 
Bitfield< 6 > dibimpr
 
Bitfield< 5 > dint
 
Bitfield< 4 > dib
 
Bitfield< 3 > ddbs
 
Bitfield< 2 > ddbl
 
Bitfield< 1 > dbp
 
Bitfield< 0 > dss
 
Bitfield< 30 > ut
 
Bitfield< 27 > tb
 
Bitfield< 26 > io
 
Bitfield< 25 > d
 
Bitfield< 24 > e
 
Bitfield< 23 > k
 
Bitfield< 22 > s
 
Bitfield< 21 > u
 
Bitfield< 20, 13 > asidM
 
Bitfield< 12, 5 > asid
 
Bitfield< 4 > g
 
Bitfield< 3 > tfcr
 
Bitfield< 2 > tlsm
 
Bitfield< 1 > tim
 
Bitfield< 0 > on
 
Bitfield< 28, 21 > cpuid
 
Bitfield< 20 > tcv
 
Bitfield< 19, 12 > tcnum
 
Bitfield< 11, 7 > mode
 
Bitfield< 6, 5 > validModes
 
Bitfield< 4 > tbi
 
Bitfield< 3 > tbu
 
Bitfield< 2, 0 > syp
 
Bitfield< 27 > ate
 
Bitfield< 26, 24 > bpc8
 
Bitfield< 23, 21 > bpc7
 
Bitfield< 20, 18 > bpc6
 
Bitfield< 17, 15 > bpc5
 
Bitfield< 14, 12 > bpc4
 
Bitfield< 11, 9 > bpc3
 
Bitfield< 8, 6 > bpc2
 
Bitfield< 5, 3 > bpc1
 
Bitfield< 2, 0 > bpc0
 
 bpc14
 
Bitfield< 14, 12 > bpc13
 
Bitfield< 11, 9 > bpc12
 
Bitfield< 8, 6 > bpc11
 
Bitfield< 5, 3 > bpc10
 
Bitfield< 2, 0 > bpc9
 
Bitfield< 2 > dq
 
Bitfield< 1 > tup
 
Bitfield< 0 > paco
 
const ByteOrder GuestByteOrder = LittleEndianByteOrder
 
const Addr PageShift = 13
 
const Addr PageBytes = ULL(1) << PageShift
 
const Addr Page_Mask = ~(PageBytes - 1)
 
const Addr PageOffset = PageBytes - 1
 
const Addr PteShift = 3
 
const Addr NPtePageShift = PageShift - PteShift
 
const Addr NPtePage = ULL(1) << NPtePageShift
 
const Addr PteMask = NPtePage - 1
 
const Addr USegBase = ULL(0x0)
 
const Addr USegEnd = ULL(0x7FFFFFFF)
 
const Addr KSeg0End = ULL(0x9FFFFFFF)
 
const Addr KSeg0Base = ULL(0x80000000)
 
const Addr KSeg0Mask = ULL(0x1FFFFFFF)
 
const Addr KSeg1End = ULL(0xBFFFFFFF)
 
const Addr KSeg1Base = ULL(0xA0000000)
 
const Addr KSeg1Mask = ULL(0x1FFFFFFF)
 
const Addr KSSegEnd = ULL(0xDFFFFFFF)
 
const Addr KSSegBase = ULL(0xC0000000)
 
const Addr KSeg3End = ULL(0xFFFFFFFF)
 
const Addr KSeg3Base = ULL(0xE0000000)
 
const unsigned VABits = 32
 
const unsigned PABits = 32
 
const Addr VAddrImplMask = (ULL(1) << VABits) - 1
 
const Addr VAddrUnImplMask = ~VAddrImplMask
 
const Addr PAddrImplMask = (ULL(1) << PABits) - 1
 
const int ANNOTE_NONE = 0
 
const uint32_t ITOUCH_ANNOTE = 0xffffffff
 
const bool HasUnalignedMemAcc = true
 
const bool CurThreadInfoImplemented = false
 
const int CurThreadInfoReg = -1
 
Bitfield< 2 > stlb
 
Bitfield< 1 > vpc
 
Bitfield< 0 > evp
 
Bitfield< 29 > tlbs
 
Bitfield< 28 > gs
 
Bitfield< 27 > pcp
 
Bitfield< 25, 16 > ptlbe
 
Bitfield< 15 > tca
 
Bitfield< 13, 10 > pvpe
 
Bitfield< 7, 0 > ptc
 
Bitfield< 18, 16 > excpt
 
Bitfield< 15 > te
 
Bitfield< 7, 0 > targTC
 
Bitfield< 28, 21 > xtc
 
Bitfield< 19 > tcs
 
Bitfield< 18 > scs
 
Bitfield< 17 > dcs
 
Bitfield< 16 > ics
 
Bitfield< 1 > mvp
 
Bitfield< 0 > vpa
 
 curTC
 
Bitfield< 20, 18 > a0
 
Bitfield< 17 > tbe
 
Bitfield< 3, 0 > curVPE
 
 tcu
 
Bitfield< 27 > tmx
 
Bitfield< 24, 23 > rnst
 
Bitfield< 21 > tds
 
Bitfield< 20 > dt
 
Bitfield< 19, 16 > impl
 
Bitfield< 15 > da
 
Bitfield< 13 > a
 
Bitfield< 12, 11 > tksu
 
Bitfield< 10 > ixmt
 
Bitfield< 30, 0 > index
 
 random
 
 fill
 
Bitfield< 29, 6 > pfn
 
Bitfield< 5, 3 > c
 
Bitfield< 1 > v
 
 pteBase
 
Bitfield< 22, 4 > badVPN2
 
 mask
 
Bitfield< 12, 11 > maskx
 
 aseUp
 
Bitfield< 29 > elpa
 
Bitfield< 28 > esp
 
Bitfield< 12, 8 > aseDn
 
 wired
 
 r
 
Bitfield< 39, 13 > vpn2
 
Bitfield< 12, 11 > vpn2x
 
Bitfield< 31 > cu3
 
Bitfield< 30 > cu2
 
Bitfield< 29 > cu1
 
Bitfield< 28 > cu0
 
Bitfield< 26 > fr
 
Bitfield< 25 > re
 
Bitfield< 24 > mx
 
Bitfield< 23 > px
 
Bitfield< 22 > bev
 
Bitfield< 21 > ts
 
Bitfield< 20 > sr
 
Bitfield< 19 > nmi
 
Bitfield< 15, 10 > ipl
 
Bitfield< 14 > im6
 
Bitfield< 13 > im5
 
Bitfield< 12 > im4
 
Bitfield< 11 > im3
 
Bitfield< 10 > im2
 
Bitfield< 9 > im1
 
Bitfield< 8 > im0
 
Bitfield< 6 > sx
 
Bitfield< 5 > ux
 
Bitfield< 4, 3 > ksu
 
Bitfield< 4 > um
 
Bitfield< 3 > r0
 
Bitfield< 2 > erl
 
Bitfield< 1 > exl
 
Bitfield< 0 > ie
 
 ipti
 
Bitfield< 28, 26 > ippci
 
Bitfield< 9, 5 > vs
 
 hss
 
Bitfield< 21, 18 > eicss
 
Bitfield< 15, 12 > ess
 
Bitfield< 9, 6 > pss
 
Bitfield< 3, 0 > css
 
 ssv7
 
Bitfield< 27, 24 > ssv6
 
Bitfield< 23, 20 > ssv5
 
Bitfield< 19, 16 > ssv4
 
Bitfield< 15, 12 > ssv3
 
Bitfield< 11, 8 > ssv2
 
Bitfield< 7, 4 > ssv1
 
Bitfield< 3, 0 > ssv0
 
Bitfield< 30 > ti
 
Bitfield< 29, 28 > ce
 
Bitfield< 27 > dc
 
Bitfield< 26 > pci
 
Bitfield< 23 > iv
 
Bitfield< 22 > wp
 
Bitfield< 15, 10 > ripl
 
Bitfield< 14 > ip6
 
Bitfield< 13 > ip5
 
Bitfield< 12 > ip4
 
Bitfield< 11 > ip3
 
Bitfield< 10 > ip2
 
Bitfield< 9 > ip1
 
Bitfield< 8 > ip0
 
Bitfield< 6, 2 > excCode
 
 coOp
 
Bitfield< 23, 16 > coId
 
Bitfield< 15, 8 > procId
 
Bitfield< 7, 0 > rev
 
 exceptionBase
 
Bitfield< 9, 9 > cpuNum
 
Bitfield< 30, 28 > k23
 
Bitfield< 27, 25 > ku
 
Bitfield< 15 > be
 
Bitfield< 14, 13 > at
 
Bitfield< 12, 10 > ar
 
Bitfield< 9, 7 > mt
 
Bitfield< 3 > vi
 
Bitfield< 2, 0 > k0
 
Bitfield< 30, 25 > mmuSize
 
Bitfield< 24, 22 > is
 
Bitfield< 21, 19 > il
 
Bitfield< 18, 16 > ia
 
Bitfield< 15, 13 > ds
 
Bitfield< 12, 10 > dl
 
Bitfield< 6 > c2
 
Bitfield< 5 > md
 
Bitfield< 4 > pc
 
Bitfield< 3 > wr
 
Bitfield< 2 > ca
 
Bitfield< 1 > ep
 
Bitfield< 0 > fp
 
Bitfield< 30, 28 > tu
 
Bitfield< 23, 20 > tl
 
Bitfield< 19, 16 > ta
 
Bitfield< 15, 12 > su
 
Bitfield< 11, 8 > ss
 
Bitfield< 7, 4 > sl
 
Bitfield< 3, 0 > sa
 
Bitfield< 10 > dspp
 
Bitfield< 7 > lpa
 
Bitfield< 6 > veic
 
Bitfield< 5 > vint
 
Bitfield< 4 > sp
 
Bitfield< 1 > sm
 
 vaddr
 
Bitfield< 2 > i
 
Bitfield< 0 > w
 
Bitfield< 10, 5 > event
 
Bitfield< 30 > ec
 
Bitfield< 29 > ed
 
Bitfield< 28 > et
 
Bitfield< 27 > es
 
Bitfield< 26 > ee
 
Bitfield< 25 > eb
 
 pTagLo
 
Bitfield< 7, 6 > pState
 
Bitfield< 5 > l
 
Bitfield< 0 > p
 
const int NumIntArchRegs = 32
 
const int NumIntSpecialRegs = 9
 
const int NumFloatArchRegs = 32
 
const int NumFloatSpecialRegs = 5
 
const int MaxShadowRegSets = 16
 
const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs
 
const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs
 
const int NumVecRegs = 1
 
const int NumVecPredRegs = 1
 
const int NumCCRegs = 0
 
const uint32_t MIPS32_QNAN = 0x7fbfffff
 
const uint64_t MIPS64_QNAN = ULL(0x7ff7ffffffffffff)
 
const int ZeroReg = 0
 
const int AssemblerReg = 1
 
const int SyscallSuccessReg = 7
 
const int FirstArgumentReg = 4
 
const int ReturnValueReg = 2
 
const int KernelReg0 = 26
 
const int KernelReg1 = 27
 
const int GlobalPointerReg = 28
 
const int StackPointerReg = 29
 
const int FramePointerReg = 30
 
const int ReturnAddressReg = 31
 
const int SyscallPseudoReturnReg = 3
 
const int NumMiscRegs = MISCREG_NUMREGS
 
const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs
 
constexpr unsigned NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg
 
constexpr size_t VecRegSizeBytes = ::DummyVecRegSizeBytes
 
constexpr size_t VecPredRegSizeBits = ::DummyVecPredRegSizeBits
 
constexpr bool VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr
 

Typedef Documentation

◆ ConstVecPredReg

using MipsISA::ConstVecPredReg = typedef ::DummyConstVecPredReg

Definition at line 296 of file registers.hh.

◆ ConstVecReg

using MipsISA::ConstVecReg = typedef ::DummyConstVecReg

Definition at line 289 of file registers.hh.

◆ ExtMachInst

typedef uint64_t MipsISA::ExtMachInst

Definition at line 41 of file types.hh.

◆ FaultVals

typedef MipsFaultBase::FaultVals MipsISA::FaultVals

Definition at line 49 of file faults.cc.

◆ FaultVect

typedef Addr MipsISA::FaultVect

Definition at line 48 of file faults.hh.

◆ MachInst

typedef uint32_t MipsISA::MachInst

Definition at line 40 of file types.hh.

◆ PCState

typedef GenericISA::DelaySlotPCState<MachInst> MipsISA::PCState

Definition at line 43 of file types.hh.

◆ VecElem

using MipsISA::VecElem = typedef ::DummyVecElem

Definition at line 287 of file registers.hh.

◆ VecPredReg

using MipsISA::VecPredReg = typedef ::DummyVecPredReg

Definition at line 295 of file registers.hh.

◆ VecPredRegContainer

using MipsISA::VecPredRegContainer = typedef ::DummyVecPredRegContainer

Definition at line 297 of file registers.hh.

◆ VecReg

using MipsISA::VecReg = typedef ::DummyVecReg

Definition at line 288 of file registers.hh.

◆ VecRegContainer

using MipsISA::VecRegContainer = typedef ::DummyVecRegContainer

Definition at line 290 of file registers.hh.

Enumeration Type Documentation

◆ anonymous enum

anonymous enum
Enumerator
SIMD_FMT_L 
SIMD_FMT_W 
SIMD_FMT_PH 
SIMD_FMT_QB 
SIMD_NUM_FMTS 

Definition at line 44 of file dsp.hh.

◆ anonymous enum

anonymous enum
Enumerator
DSP_POS 
DSP_SCOUNT 
DSP_C 
DSP_OUFLAG 
DSP_CCOND 
DSP_EFI 
DSP_NUM_FIELDS 

Definition at line 53 of file dsp.hh.

◆ anonymous enum

anonymous enum
Enumerator
CMP_EQ 
CMP_LT 
CMP_LE 

Definition at line 64 of file dsp.hh.

◆ anonymous enum

anonymous enum
Enumerator
MODE_L 
MODE_R 
MODE_LA 
MODE_RA 
MODE_X 

Definition at line 71 of file dsp.hh.

◆ anonymous enum

anonymous enum
Enumerator
UNSIGNED 
SIGNED 

Definition at line 80 of file dsp.hh.

◆ anonymous enum

anonymous enum
Enumerator
NOSATURATE 
SATURATE 

Definition at line 81 of file dsp.hh.

◆ anonymous enum

anonymous enum
Enumerator
NOROUND 
ROUND 

Definition at line 82 of file dsp.hh.

◆ ConvertType

enum MipsISA::ConvertType
Enumerator
SINGLE_TO_DOUBLE 
SINGLE_TO_WORD 
SINGLE_TO_LONG 
DOUBLE_TO_SINGLE 
DOUBLE_TO_WORD 
DOUBLE_TO_LONG 
LONG_TO_SINGLE 
LONG_TO_DOUBLE 
LONG_TO_WORD 
LONG_TO_PS 
WORD_TO_SINGLE 
WORD_TO_DOUBLE 
WORD_TO_LONG 
WORD_TO_PS 
PL_TO_SINGLE 
PU_TO_SINGLE 

Definition at line 46 of file types.hh.

◆ ExcCode

enum MipsISA::ExcCode
Enumerator
ExcCodeDummy 
ExcCodeInt 
ExcCodeMod 
ExcCodeTlbL 
ExcCodeTlbS 
ExcCodeAdEL 
ExcCodeAdES 
ExcCodeIBE 
ExcCodeDBE 
ExcCodeSys 
ExcCodeBp 
ExcCodeRI 
ExcCodeCpU 
ExcCodeOv 
ExcCodeTr 
ExcCodeC2E 
ExcCodeMDMX 
ExcCodeWatch 
ExcCodeMCheck 
ExcCodeThread 
ExcCodeCacheErr 

Definition at line 50 of file faults.hh.

◆ FCSRBits

enum MipsISA::FCSRBits
Enumerator
Inexact 
Underflow 
Overflow 
DivideByZero 
Invalid 
Unimplemented 

Definition at line 76 of file registers.hh.

◆ FCSRFields

enum MipsISA::FCSRFields
Enumerator
Flag_Field 
Enable_Field 
Cause_Field 

Definition at line 85 of file registers.hh.

◆ FPControlRegNums

enum MipsISA::FPControlRegNums
Enumerator
FLOATREG_FIR 
FLOATREG_FCCR 
FLOATREG_FEXR 
FLOATREG_FENR 
FLOATREG_FCSR 

Definition at line 68 of file registers.hh.

◆ InterruptLevels

enum MipsISA::InterruptLevels
Enumerator
INTLEVEL_SOFTWARE_MIN 
INTLEVEL_SOFTWARE_MAX 
INTLEVEL_EXTERNAL_MIN 
INTLEVEL_EXTERNAL_MAX 
INTLEVEL_IRQ0 
INTLEVEL_IRQ1 
INTINDEX_ETHERNET 
INTINDEX_SCSI 
INTLEVEL_IRQ2 
INTLEVEL_IRQ3 
INTLEVEL_SERIAL 
NumInterruptLevels 

Definition at line 110 of file isa_traits.hh.

◆ MiscIntRegNums

enum MipsISA::MiscIntRegNums
Enumerator
INTREG_LO 
INTREG_DSP_LO0 
INTREG_HI 
INTREG_DSP_HI0 
INTREG_DSP_ACX0 
INTREG_DSP_LO1 
INTREG_DSP_HI1 
INTREG_DSP_ACX1 
INTREG_DSP_LO2 
INTREG_DSP_HI2 
INTREG_DSP_ACX2 
INTREG_DSP_LO3 
INTREG_DSP_HI3 
INTREG_DSP_ACX3 
INTREG_DSP_CONTROL 

Definition at line 91 of file registers.hh.

◆ MiscRegIndex

enum MipsISA::MiscRegIndex
Enumerator
MISCREG_INDEX 
MISCREG_MVP_CONTROL 
MISCREG_MVP_CONF0 
MISCREG_MVP_CONF1 
MISCREG_CP0_RANDOM 
MISCREG_VPE_CONTROL 
MISCREG_VPE_CONF0 
MISCREG_VPE_CONF1 
MISCREG_YQMASK 
MISCREG_VPE_SCHEDULE 
MISCREG_VPE_SCHEFBACK 
MISCREG_VPE_OPT 
MISCREG_ENTRYLO0 
MISCREG_TC_STATUS 
MISCREG_TC_BIND 
MISCREG_TC_RESTART 
MISCREG_TC_HALT 
MISCREG_TC_CONTEXT 
MISCREG_TC_SCHEDULE 
MISCREG_TC_SCHEFBACK 
MISCREG_ENTRYLO1 
MISCREG_CONTEXT 
MISCREG_CONTEXT_CONFIG 
MISCREG_PAGEMASK 
MISCREG_PAGEGRAIN 
MISCREG_WIRED 
MISCREG_SRS_CONF0 
MISCREG_SRS_CONF1 
MISCREG_SRS_CONF2 
MISCREG_SRS_CONF3 
MISCREG_SRS_CONF4 
MISCREG_HWRENA 
MISCREG_BADVADDR 
MISCREG_COUNT 
MISCREG_ENTRYHI 
MISCREG_COMPARE 
MISCREG_STATUS 
MISCREG_INTCTL 
MISCREG_SRSCTL 
MISCREG_SRSMAP 
MISCREG_CAUSE 
MISCREG_EPC 
MISCREG_PRID 
MISCREG_EBASE 
MISCREG_CONFIG 
MISCREG_CONFIG1 
MISCREG_CONFIG2 
MISCREG_CONFIG3 
MISCREG_CONFIG4 
MISCREG_CONFIG5 
MISCREG_CONFIG6 
MISCREG_CONFIG7 
MISCREG_LLADDR 
MISCREG_WATCHLO0 
MISCREG_WATCHLO1 
MISCREG_WATCHLO2 
MISCREG_WATCHLO3 
MISCREG_WATCHLO4 
MISCREG_WATCHLO5 
MISCREG_WATCHLO6 
MISCREG_WATCHLO7 
MISCREG_WATCHHI0 
MISCREG_WATCHHI1 
MISCREG_WATCHHI2 
MISCREG_WATCHHI3 
MISCREG_WATCHHI4 
MISCREG_WATCHHI5 
MISCREG_WATCHHI6 
MISCREG_WATCHHI7 
MISCREG_XCCONTEXT64 
MISCREG_DEBUG 
MISCREG_TRACE_CONTROL1 
MISCREG_TRACE_CONTROL2 
MISCREG_USER_TRACE_DATA 
MISCREG_TRACE_BPC 
MISCREG_DEPC 
MISCREG_PERFCNT0 
MISCREG_PERFCNT1 
MISCREG_PERFCNT2 
MISCREG_PERFCNT3 
MISCREG_PERFCNT4 
MISCREG_PERFCNT5 
MISCREG_PERFCNT6 
MISCREG_PERFCNT7 
MISCREG_ERRCTL 
MISCREG_CACHEERR0 
MISCREG_CACHEERR1 
MISCREG_CACHEERR2 
MISCREG_CACHEERR3 
MISCREG_TAGLO0 
MISCREG_DATALO1 
MISCREG_TAGLO2 
MISCREG_DATALO3 
MISCREG_TAGLO4 
MISCREG_DATALO5 
MISCREG_TAGLO6 
MISCREG_DATALO7 
MISCREG_TAGHI0 
MISCREG_DATAHI1 
MISCREG_TAGHI2 
MISCREG_DATAHI3 
MISCREG_TAGHI4 
MISCREG_DATAHI5 
MISCREG_TAGHI6 
MISCREG_DATAHI7 
MISCREG_ERROR_EPC 
MISCREG_DESAVE 
MISCREG_LLFLAG 
MISCREG_TP_VALUE 
MISCREG_NUMREGS 

Definition at line 132 of file registers.hh.

◆ mode_type

enum MipsISA::mode_type
Enumerator
mode_kernel 
mode_supervisor 
mode_user 
mode_debug 
mode_number 

Definition at line 131 of file isa_traits.hh.

◆ RoundMode

enum MipsISA::RoundMode
Enumerator
RND_ZERO 
RND_DOWN 
RND_UP 
RND_NEAREST 

Definition at line 70 of file types.hh.

Function Documentation

◆ addHalfLsb()

uint64_t MipsISA::addHalfLsb ( uint64_t  value,
int32_t  lsbpos 
)

Definition at line 129 of file dsp.cc.

References ULL.

Referenced by dspAddh(), dspExtr(), dspMulq(), dspPrecrq(), dspPrecrSra(), dspShra(), and dspSubh().

◆ advancePC()

void MipsISA::advancePC ( PCState &  pc,
const StaticInstPtr &  inst 
)
inline

Definition at line 112 of file utility.hh.

References GenericISA::DelaySlotPCState< MachInst >::advance().

◆ bitrev()

int32_t MipsISA::bitrev ( int32_t  value)

Definition at line 43 of file dsp.cc.

References i, and ArmISA::shift.

◆ BitUnion32() [1/3]

MipsISA::BitUnion32 ( DebugReg  )

◆ BitUnion32() [2/3]

MipsISA::BitUnion32 ( IndexReg  )

◆ BitUnion32() [3/3]

MipsISA::BitUnion32 ( MVPControlReg  )

◆ buildRetPC()

PCState MipsISA::buildRetPC ( const PCState &  curPC,
const PCState &  callPC 
)
inline

Definition at line 48 of file utility.hh.

References GenericISA::DelaySlotPCState< MachInst >::advance(), fp, fpConvert(), genCCVector(), genInvalidVector(), getArgument(), getCondCode(), isNan(), isQnan(), isSnan(), GenericISA::SimplePCState< MachInst >::npc(), GenericISA::SimplePCState< MachInst >::pc(), roundFP(), truncFP(), and X86ISA::val.

◆ checkOverflow()

uint64_t MipsISA::checkOverflow ( uint64_t  value,
int32_t  fmt,
int32_t  sign,
uint32_t *  overflow 
)

Definition at line 91 of file dsp.cc.

References FIXED_SMAX, FIXED_SMIN, FIXED_UMAX, FIXED_UMIN, SIGNED, and UNSIGNED.

Referenced by dspAdd(), dspExtr(), dspMul(), dspShll(), and dspSub().

◆ copyMiscRegs()

void MipsISA::copyMiscRegs ( ThreadContext *  src,
ThreadContext *  dest 
)

Definition at line 243 of file utility.cc.

References panic.

Referenced by RoundPage().

◆ copyRegs()

void MipsISA::copyRegs ( ThreadContext *  src,
ThreadContext *  dest 
)

Definition at line 221 of file utility.cc.

References i, NumCCRegs, NumFloatRegs, NumIntRegs, NumMiscRegs, ThreadContext::pcState(), ThreadContext::readFloatRegFlat(), ThreadContext::readIntRegFlat(), ThreadContext::readMiscRegNoEffect(), ThreadContext::setFloatRegFlat(), ThreadContext::setIntRegFlat(), and ThreadContext::setMiscRegNoEffect().

Referenced by RoundPage().

◆ decodeInst()

StaticInstPtr MipsISA::decodeInst ( ExtMachInst  )

◆ dspAbs()

int32_t MipsISA::dspAbs ( int32_t  a,
int32_t  fmt,
uint32_t *  dspctl 
)

Definition at line 135 of file dsp.cc.

References DSP_CTL_POS, DSP_OUFLAG, FIXED_SMAX, FIXED_SMIN, i, SIGNED, SIMD_MAX_VALS, SIMD_NVALS, simdPack(), simdUnpack(), and writeDSPControl().

◆ dspAdd()

int32_t MipsISA::dspAdd ( int32_t  a,
int32_t  b,
int32_t  fmt,
int32_t  saturate,
int32_t  sign,
uint32_t *  dspctl 
)

Definition at line 166 of file dsp.cc.

References checkOverflow(), DSP_CTL_POS, DSP_OUFLAG, dspSaturate(), i, SIMD_MAX_VALS, SIMD_NVALS, simdPack(), simdUnpack(), and writeDSPControl().

◆ dspAddh()

int32_t MipsISA::dspAddh ( int32_t  a,
int32_t  b,
int32_t  fmt,
int32_t  round,
int32_t  sign 
)

Definition at line 198 of file dsp.cc.

References addHalfLsb(), i, SIMD_MAX_VALS, SIMD_NVALS, simdPack(), and simdUnpack().

◆ dspCmp()

void MipsISA::dspCmp ( int32_t  a,
int32_t  b,
int32_t  fmt,
int32_t  sign,
int32_t  op,
uint32_t *  dspctl 
)

Definition at line 771 of file dsp.cc.

References CMP_EQ, CMP_LE, CMP_LT, DSP_CCOND, DSP_CTL_POS, i, SIMD_MAX_VALS, SIMD_NVALS, simdUnpack(), and writeDSPControl().

◆ dspCmpg()

int32_t MipsISA::dspCmpg ( int32_t  a,
int32_t  b,
int32_t  fmt,
int32_t  sign,
int32_t  op 
)

Definition at line 804 of file dsp.cc.

References CMP_EQ, CMP_LE, CMP_LT, i, SIMD_MAX_VALS, SIMD_NVALS, and simdUnpack().

◆ dspCmpgd()

int32_t MipsISA::dspCmpgd ( int32_t  a,
int32_t  b,
int32_t  fmt,
int32_t  sign,
int32_t  op,
uint32_t *  dspctl 
)

Definition at line 836 of file dsp.cc.

References CMP_EQ, CMP_LE, CMP_LT, DSP_CCOND, DSP_CTL_POS, i, SIMD_MAX_VALS, SIMD_NVALS, simdUnpack(), and writeDSPControl().

◆ dspDpa()

int64_t MipsISA::dspDpa ( int64_t  dspac,
int32_t  a,
int32_t  b,
int32_t  ac,
int32_t  fmt,
int32_t  sign,
int32_t  mode 
)

Definition at line 628 of file dsp.cc.

References i, MODE_L, MODE_R, MODE_X, SIMD_MAX_VALS, SIMD_NVALS, and simdUnpack().

◆ dspDpaq()

int64_t MipsISA::dspDpaq ( int64_t  dspac,
int32_t  a,
int32_t  b,
int32_t  ac,
int32_t  infmt,
int32_t  outfmt,
int32_t  postsat,
int32_t  mode,
uint32_t *  dspctl 
)

Definition at line 494 of file dsp.cc.

References bits(), dspSaturate(), FIXED_SMAX, FIXED_SMIN, i, insertBits(), MODE_X, SIGNED, SIMD_FMT_L, SIMD_MAX_VALS, SIMD_NVALS, and simdUnpack().

◆ dspDps()

int64_t MipsISA::dspDps ( int64_t  dspac,
int32_t  a,
int32_t  b,
int32_t  ac,
int32_t  fmt,
int32_t  sign,
int32_t  mode 
)

Definition at line 656 of file dsp.cc.

References i, MODE_L, MODE_R, MODE_X, SIMD_MAX_VALS, SIMD_NVALS, and simdUnpack().

◆ dspDpsq()

int64_t MipsISA::dspDpsq ( int64_t  dspac,
int32_t  a,
int32_t  b,
int32_t  ac,
int32_t  infmt,
int32_t  outfmt,
int32_t  postsat,
int32_t  mode,
uint32_t *  dspctl 
)

Definition at line 561 of file dsp.cc.

References bits(), dspSaturate(), FIXED_SMAX, FIXED_SMIN, i, insertBits(), MODE_X, SIGNED, SIMD_FMT_L, SIMD_MAX_VALS, SIMD_NVALS, and simdUnpack().

◆ dspExtp()

int32_t MipsISA::dspExtp ( int64_t  dspac,
int32_t  size,
uint32_t *  dspctl 
)

Definition at line 1084 of file dsp.cc.

References bits(), and insertBits().

◆ dspExtpd()

int32_t MipsISA::dspExtpd ( int64_t  dspac,
int32_t  size,
uint32_t *  dspctl 
)

Definition at line 1104 of file dsp.cc.

References bits(), and insertBits().

◆ dspExtr()

int32_t MipsISA::dspExtr ( int64_t  dspac,
int32_t  fmt,
int32_t  sa,
int32_t  round,
int32_t  saturate,
uint32_t *  dspctl 
)

Definition at line 1041 of file dsp.cc.

References addHalfLsb(), bits(), checkOverflow(), dspSaturate(), FIXED_SMAX, insertBits(), sa, SIGNED, and SIMD_FMT_L.

◆ dspMaq()

int64_t MipsISA::dspMaq ( int64_t  dspac,
int32_t  a,
int32_t  b,
int32_t  ac,
int32_t  fmt,
int32_t  mode,
int32_t  saturate,
uint32_t *  dspctl 
)

Definition at line 684 of file dsp.cc.

References dspSaturate(), FIXED_SMAX, FIXED_SMIN, i, insertBits(), MODE_L, MODE_R, SIGNED, SIMD_MAX_VALS, SIMD_NVALS, and simdUnpack().

◆ dspMul()

int32_t MipsISA::dspMul ( int32_t  a,
int32_t  b,
int32_t  fmt,
int32_t  saturate,
uint32_t *  dspctl 
)

Definition at line 391 of file dsp.cc.

References checkOverflow(), DSP_CTL_POS, DSP_OUFLAG, dspSaturate(), i, SIGNED, SIMD_MAX_VALS, SIMD_NVALS, simdPack(), simdUnpack(), and writeDSPControl().

◆ dspMuleq()

int32_t MipsISA::dspMuleq ( int32_t  a,
int32_t  b,
int32_t  mode,
uint32_t *  dspctl 
)

Definition at line 457 of file dsp.cc.

References DSP_CTL_POS, DSP_OUFLAG, dspSaturate(), i, MODE_L, MODE_R, SIGNED, SIMD_FMT_PH, SIMD_FMT_W, SIMD_MAX_VALS, SIMD_NVALS, simdPack(), simdUnpack(), and writeDSPControl().

◆ dspMuleu()

int32_t MipsISA::dspMuleu ( int32_t  a,
int32_t  b,
int32_t  mode,
uint32_t *  dspctl 
)

Definition at line 423 of file dsp.cc.

References DSP_CTL_POS, DSP_OUFLAG, dspSaturate(), i, MODE_L, MODE_R, SIMD_FMT_PH, SIMD_FMT_QB, SIMD_MAX_VALS, SIMD_NVALS, simdPack(), simdUnpack(), UNSIGNED, and writeDSPControl().

◆ dspMulq()

int32_t MipsISA::dspMulq ( int32_t  a,
int32_t  b,
int32_t  fmt,
int32_t  saturate,
int32_t  round,
uint32_t *  dspctl 
)

Definition at line 350 of file dsp.cc.

References addHalfLsb(), DSP_CTL_POS, DSP_OUFLAG, FIXED_SMAX, FIXED_SMIN, i, sa, SIGNED, SIMD_MAX_VALS, SIMD_NBITS, SIMD_NVALS, simdPack(), simdUnpack(), and writeDSPControl().

◆ dspMulsa()

int64_t MipsISA::dspMulsa ( int64_t  dspac,
int32_t  a,
int32_t  b,
int32_t  ac,
int32_t  fmt 
)

Definition at line 728 of file dsp.cc.

References SIGNED, SIMD_MAX_VALS, and simdUnpack().

◆ dspMulsaq()

int64_t MipsISA::dspMulsaq ( int64_t  dspac,
int32_t  a,
int32_t  b,
int32_t  ac,
int32_t  fmt,
uint32_t *  dspctl 
)

Definition at line 742 of file dsp.cc.

References FIXED_SMAX, FIXED_SMIN, i, insertBits(), SIGNED, SIMD_MAX_VALS, SIMD_NVALS, and simdUnpack().

◆ dspPack()

int32_t MipsISA::dspPack ( int32_t  a,
int32_t  b,
int32_t  fmt 
)

Definition at line 1022 of file dsp.cc.

References SIMD_MAX_VALS, simdPack(), simdUnpack(), and UNSIGNED.

◆ dspPick()

int32_t MipsISA::dspPick ( int32_t  a,
int32_t  b,
int32_t  fmt,
uint32_t *  dspctl 
)

Definition at line 997 of file dsp.cc.

References bits(), DSP_CCOND, DSP_CTL_POS, i, SIMD_MAX_VALS, SIMD_NVALS, simdPack(), simdUnpack(), and UNSIGNED.

◆ dspPrece()

int32_t MipsISA::dspPrece ( int32_t  a,
int32_t  infmt,
int32_t  insign,
int32_t  outfmt,
int32_t  outsign,
int32_t  mode 
)

Definition at line 873 of file dsp.cc.

References i, MODE_L, MODE_LA, MODE_R, MODE_RA, sa, SIGNED, SIMD_MAX_VALS, SIMD_NBITS, SIMD_NVALS, simdPack(), simdUnpack(), and UNSIGNED.

◆ dspPrecrq()

int32_t MipsISA::dspPrecrq ( int32_t  a,
int32_t  b,
int32_t  fmt,
uint32_t *  dspctl 
)

Definition at line 944 of file dsp.cc.

References addHalfLsb(), dspSaturate(), insertBits(), SIGNED, SIMD_MAX_VALS, simdPack(), and simdUnpack().

◆ dspPrecrqu()

int32_t MipsISA::dspPrecrqu ( int32_t  a,
int32_t  b,
uint32_t *  dspctl 
)

Definition at line 915 of file dsp.cc.

References dspSaturate(), i, insertBits(), SIGNED, SIMD_FMT_PH, SIMD_FMT_QB, SIMD_MAX_VALS, SIMD_NBITS, simdPack(), simdUnpack(), and UNSIGNED.

◆ dspPrecrSra()

int32_t MipsISA::dspPrecrSra ( int32_t  a,
int32_t  b,
int32_t  sa,
int32_t  fmt,
int32_t  round 
)

Definition at line 969 of file dsp.cc.

References addHalfLsb(), i, sa, SIGNED, SIMD_MAX_VALS, SIMD_NVALS, simdPack(), and simdUnpack().

◆ dspSaturate()

uint64_t MipsISA::dspSaturate ( uint64_t  value,
int32_t  fmt,
int32_t  sign,
uint32_t *  overflow 
)

Definition at line 61 of file dsp.cc.

References FIXED_SMAX, FIXED_SMIN, FIXED_UMAX, FIXED_UMIN, SIGNED, and UNSIGNED.

Referenced by dspAdd(), dspDpaq(), dspDpsq(), dspExtr(), dspMaq(), dspMul(), dspMuleq(), dspMuleu(), dspPrecrq(), dspPrecrqu(), dspShll(), and dspSub().

◆ dspShll()

int32_t MipsISA::dspShll ( int32_t  a,
uint32_t  sa,
int32_t  fmt,
int32_t  saturate,
int32_t  sign,
uint32_t *  dspctl 
)

Definition at line 278 of file dsp.cc.

References bits(), checkOverflow(), DSP_CTL_POS, DSP_OUFLAG, dspSaturate(), i, SIMD_LOG2N, SIMD_MAX_VALS, SIMD_NVALS, simdPack(), simdUnpack(), and writeDSPControl().

◆ dspShra()

int32_t MipsISA::dspShra ( int32_t  a,
uint32_t  sa,
int32_t  fmt,
int32_t  round,
int32_t  sign,
uint32_t *  dspctl 
)

Definition at line 326 of file dsp.cc.

References addHalfLsb(), bits(), i, sa, SIGNED, SIMD_LOG2N, SIMD_MAX_VALS, SIMD_NVALS, simdPack(), and simdUnpack().

◆ dspShrl()

int32_t MipsISA::dspShrl ( int32_t  a,
uint32_t  sa,
int32_t  fmt,
int32_t  sign 
)

Definition at line 307 of file dsp.cc.

References bits(), i, SIMD_LOG2N, SIMD_MAX_VALS, SIMD_NVALS, simdPack(), simdUnpack(), and UNSIGNED.

◆ dspSub()

int32_t MipsISA::dspSub ( int32_t  a,
int32_t  b,
int32_t  fmt,
int32_t  saturate,
int32_t  sign,
uint32_t *  dspctl 
)

Definition at line 222 of file dsp.cc.

References checkOverflow(), DSP_CTL_POS, DSP_OUFLAG, dspSaturate(), i, SIMD_MAX_VALS, SIMD_NVALS, simdPack(), simdUnpack(), and writeDSPControl().

◆ dspSubh()

int32_t MipsISA::dspSubh ( int32_t  a,
int32_t  b,
int32_t  fmt,
int32_t  round,
int32_t  sign 
)

Definition at line 253 of file dsp.cc.

References addHalfLsb(), i, SIMD_MAX_VALS, SIMD_NVALS, simdPack(), and simdUnpack().

◆ EndBitUnion() [1/35]

MipsISA::EndBitUnion ( MVPControlReg  )

◆ EndBitUnion() [2/35]

MipsISA::EndBitUnion ( IndexReg  )

◆ EndBitUnion() [3/35]

MipsISA::EndBitUnion ( RandomReg  )

◆ EndBitUnion() [4/35]

MipsISA::EndBitUnion ( MVPConf0Reg  )

◆ EndBitUnion() [5/35]

MipsISA::EndBitUnion ( EntryLoReg  )

◆ EndBitUnion() [6/35]

MipsISA::EndBitUnion ( VPEControlReg  )

◆ EndBitUnion() [7/35]

MipsISA::EndBitUnion ( ContextReg  )

◆ EndBitUnion() [8/35]

MipsISA::EndBitUnion ( DebugReg  )

◆ EndBitUnion() [9/35]

MipsISA::EndBitUnion ( VPEConf0Reg  )

◆ EndBitUnion() [10/35]

MipsISA::EndBitUnion ( PageMaskReg  )

◆ EndBitUnion() [11/35]

MipsISA::EndBitUnion ( TCBindReg  )

◆ EndBitUnion() [12/35]

MipsISA::EndBitUnion ( PageGrainReg  )

◆ EndBitUnion() [13/35]

MipsISA::EndBitUnion ( WiredReg  )

◆ EndBitUnion() [14/35]

MipsISA::EndBitUnion ( TraceControlReg  )

◆ EndBitUnion() [15/35]

MipsISA::EndBitUnion ( HWREnaReg  )

◆ EndBitUnion() [16/35]

MipsISA::EndBitUnion ( TCStatusReg  )

◆ EndBitUnion() [17/35]

MipsISA::EndBitUnion ( EntryHiReg  )

◆ EndBitUnion() [18/35]

MipsISA::EndBitUnion ( TraceControl2Reg  )

◆ EndBitUnion() [19/35]

MipsISA::EndBitUnion ( TraceBPCReg  )

◆ EndBitUnion() [20/35]

MipsISA::EndBitUnion ( TraceBPC2Reg  )

◆ EndBitUnion() [21/35]

MipsISA::EndBitUnion ( StatusReg  )

◆ EndBitUnion() [22/35]

MipsISA::EndBitUnion ( IntCtlReg  )

◆ EndBitUnion() [23/35]

MipsISA::EndBitUnion ( SRSCtlReg  )

◆ EndBitUnion() [24/35]

MipsISA::EndBitUnion ( SRSMapReg  )

◆ EndBitUnion() [25/35]

MipsISA::EndBitUnion ( CauseReg  )

◆ EndBitUnion() [26/35]

MipsISA::EndBitUnion ( PRIdReg  )

◆ EndBitUnion() [27/35]

MipsISA::EndBitUnion ( EBaseReg  )

◆ EndBitUnion() [28/35]

MipsISA::EndBitUnion ( ConfigReg  )

◆ EndBitUnion() [29/35]

MipsISA::EndBitUnion ( Config1Reg  )

◆ EndBitUnion() [30/35]

MipsISA::EndBitUnion ( Config2Reg  )

◆ EndBitUnion() [31/35]

MipsISA::EndBitUnion ( Config3Reg  )

◆ EndBitUnion() [32/35]

MipsISA::EndBitUnion ( WatchLoReg  )

◆ EndBitUnion() [33/35]

MipsISA::EndBitUnion ( WatchHiReg  )

◆ EndBitUnion() [34/35]

MipsISA::EndBitUnion ( PerfCntCtlReg  )

◆ EndBitUnion() [35/35]

MipsISA::EndBitUnion ( CacheErrReg  )

◆ EndSubBitUnion() [1/4]

MipsISA::EndSubBitUnion ( ejtagVer  )

◆ EndSubBitUnion() [2/4]

MipsISA::EndSubBitUnion ( cu  )

◆ EndSubBitUnion() [3/4]

MipsISA::EndSubBitUnion ( im  )

◆ EndSubBitUnion() [4/4]

MipsISA::EndSubBitUnion ( ip  )

◆ forkThread()

template<class TC >
void MipsISA::forkThread ( TC *  tc,
Fault &  fault,
int  Rd_bits,
int  Rs,
int  Rt 
)

Definition at line 171 of file mt.hh.

References IntRegClass, MISCREG_MVP_CONF0, MISCREG_STATUS, MISCREG_TC_BIND, MISCREG_TC_HALT, MISCREG_TC_RESTART, MISCREG_TC_STATUS, MISCREG_VPE_CONTROL, MiscRegClass, readRegOtherThread(), setRegOtherThread(), and ArmISA::status.

◆ fpConvert()

uint64_t MipsISA::fpConvert ( ConvertType  cvt_type,
double  fp_val 
)

Definition at line 58 of file utility.cc.

References panic, SINGLE_TO_DOUBLE, SINGLE_TO_WORD, WORD_TO_DOUBLE, and WORD_TO_SINGLE.

Referenced by buildRetPC().

◆ genCCVector()

uint32_t MipsISA::genCCVector ( uint32_t  fcsr,
int  cc_num,
uint32_t  cc_val 
)

Definition at line 128 of file utility.cc.

References bits().

Referenced by buildRetPC().

◆ genInvalidVector()

uint32_t MipsISA::genInvalidVector ( uint32_t  fcsr_bits)

Definition at line 140 of file utility.cc.

References Cause_Field, Flag_Field, and Invalid.

Referenced by buildRetPC().

◆ getArgument()

uint64_t MipsISA::getArgument ( ThreadContext *  tc,
int &  number,
uint16_t  size,
bool  fp 
)

Definition at line 51 of file utility.cc.

References panic.

Referenced by buildRetPC().

◆ getCauseIP()

static uint8_t MipsISA::getCauseIP ( ThreadContext *  tc)
inlinestatic

Definition at line 46 of file interrupts.cc.

References MISCREG_CAUSE, and ThreadContext::readMiscRegNoEffect().

Referenced by MipsISA::Interrupts::clear(), MipsISA::Interrupts::interruptsPending(), and MipsISA::Interrupts::post().

◆ getCondCode()

bool MipsISA::getCondCode ( uint32_t  fcsr,
int  cc_idx 
)

Definition at line 120 of file utility.cc.

References ArmISA::shift.

Referenced by buildRetPC().

◆ getExecutingAsid()

uint64_t MipsISA::getExecutingAsid ( ThreadContext *  tc)
inline

Definition at line 118 of file utility.hh.

◆ getTargetThread()

template<class TC >
unsigned MipsISA::getTargetThread ( TC *  tc)
inline

Definition at line 127 of file mt.hh.

References MISCREG_VPE_CONTROL.

◆ getVirtProcNum()

template<class TC >
unsigned MipsISA::getVirtProcNum ( TC *  tc)
inline

Definition at line 119 of file mt.hh.

References MISCREG_TC_BIND.

◆ globalClearExclusive()

template<class XC >
void MipsISA::globalClearExclusive ( XC *  xc)
inline

Definition at line 144 of file locked_mem.hh.

◆ haltThread()

template<class TC >
void MipsISA::haltThread ( TC *  tc)
inline

Definition at line 135 of file mt.hh.

References curTick(), MISCREG_TC_RESTART, GenericISA::SimplePCState< MachInst >::npc(), GenericISA::SimplePCState< MachInst >::pc(), pc, and warn.

Referenced by MipsISA::ISA::updateCPU().

◆ handleIprRead()

Cycles MipsISA::handleIprRead ( ThreadContext *  ,
Packet *   
)
inline

Definition at line 48 of file mmapped_ipr.hh.

◆ handleIprWrite()

Cycles MipsISA::handleIprWrite ( ThreadContext *  ,
Packet *   
)
inline

Definition at line 49 of file mmapped_ipr.hh.

◆ handleLockedRead()

template<class XC >
void MipsISA::handleLockedRead ( XC *  xc,
const RequestPtr &  req 
)
inline

Definition at line 78 of file locked_mem.hh.

References DPRINTF, MISCREG_LLADDR, and MISCREG_LLFLAG.

◆ handleLockedSnoop()

template<class XC >
void MipsISA::handleLockedSnoop ( XC *  xc,
PacketPtr  pkt,
Addr  cacheBlockMask 
)
inline

Definition at line 63 of file locked_mem.hh.

References Packet::getAddr(), MISCREG_LLADDR, and MISCREG_LLFLAG.

◆ handleLockedSnoopHit()

template<class XC >
void MipsISA::handleLockedSnoopHit ( XC *  xc)
inline

Definition at line 89 of file locked_mem.hh.

◆ handleLockedWrite()

template<class XC >
bool MipsISA::handleLockedWrite ( XC *  xc,
const RequestPtr &  req,
Addr  cacheBlockMask 
)
inline

Definition at line 95 of file locked_mem.hh.

References curTick(), DPRINTF, MISCREG_LLADDR, MISCREG_LLFLAG, and warn.

◆ inUserMode()

static bool MipsISA::inUserMode ( ThreadContext *  tc)
inlinestatic

Definition at line 75 of file utility.hh.

References MISCREG_DEBUG, MISCREG_STATUS, and ThreadContext::readMiscReg().

◆ isNan()

bool MipsISA::isNan ( void *  val_ptr,
int  size 
)

Definition at line 154 of file utility.cc.

References bits(), and panic.

Referenced by buildRetPC().

◆ isQnan()

bool MipsISA::isQnan ( void *  val_ptr,
int  size 
)

Definition at line 177 of file utility.cc.

References bits(), and panic.

Referenced by buildRetPC().

◆ isSnan()

bool MipsISA::isSnan ( void *  val_ptr,
int  size 
)

Definition at line 199 of file utility.cc.

References bits(), and panic.

Referenced by buildRetPC().

◆ Phys2K0Seg()

Addr MipsISA::Phys2K0Seg ( Addr  addr)
inline

Definition at line 90 of file isa_traits.hh.

References KSeg0Base.

◆ readDSPControl()

uint32_t MipsISA::readDSPControl ( uint32_t *  dspctl,
uint32_t  mask 
)

Definition at line 1179 of file dsp.cc.

References DSP_C, DSP_CCOND, DSP_CTL_MASK, DSP_EFI, DSP_OUFLAG, DSP_POS, and DSP_SCOUNT.

◆ readRegOtherThread() [1/2]

static RegVal MipsISA::readRegOtherThread ( ThreadContext *  tc,
const RegId &  reg,
ThreadID  tid = InvalidThreadID 
)
inlinestatic

Definition at line 56 of file mt.hh.

References RegId::className(), RegId::classValue(), FloatRegClass, BaseCPU::getContext(), ThreadContext::getCpuPtr(), RegId::index(), IntRegClass, InvalidThreadID, MiscRegClass, panic, ThreadContext::readFloatReg(), ThreadContext::readIntReg(), and ThreadContext::readMiscReg().

Referenced by forkThread(), readRegOtherThread(), and yieldThread().

◆ readRegOtherThread() [2/2]

static RegVal MipsISA::readRegOtherThread ( ExecContext *  xc,
const RegId &  reg,
ThreadID  tid = InvalidThreadID 
)
inlinestatic

Definition at line 104 of file mt.hh.

References readRegOtherThread(), X86ISA::reg, and ExecContext::tcBase().

◆ restoreThread()

template<class TC >
void MipsISA::restoreThread ( TC *  tc)
inline

Definition at line 154 of file mt.hh.

References curTick(), MISCREG_TC_RESTART, and warn.

Referenced by MipsISA::ISA::updateCPU().

◆ roundFP()

double MipsISA::roundFP ( double  val,
int  digits 
)

Definition at line 102 of file utility.cc.

References X86ISA::val.

Referenced by buildRetPC().

◆ RoundPage()

Addr MipsISA::RoundPage ( Addr  addr)
inline

Definition at line 101 of file utility.hh.

References copyMiscRegs(), copyRegs(), PageBytes, and skipFunction().

◆ setCauseIP()

static void MipsISA::setCauseIP ( ThreadContext *  tc,
uint8_t  val 
)
inlinestatic

Definition at line 52 of file interrupts.cc.

References MISCREG_CAUSE, ThreadContext::readMiscRegNoEffect(), ThreadContext::setMiscRegNoEffect(), and X86ISA::val.

Referenced by MipsISA::Interrupts::clear(), MipsISA::Interrupts::clearAll(), MipsISA::Interrupts::interruptsPending(), and MipsISA::Interrupts::post().

◆ setRegOtherThread() [1/2]

static void MipsISA::setRegOtherThread ( ThreadContext *  tc,
const RegId &  reg,
RegVal  val,
ThreadID  tid = InvalidThreadID 
)
inlinestatic

Definition at line 80 of file mt.hh.

References RegId::className(), RegId::classValue(), FloatRegClass, BaseCPU::getContext(), ThreadContext::getCpuPtr(), RegId::index(), IntRegClass, InvalidThreadID, MiscRegClass, panic, ThreadContext::setFloatReg(), ThreadContext::setIntReg(), ThreadContext::setMiscReg(), and X86ISA::val.

Referenced by forkThread(), and setRegOtherThread().

◆ setRegOtherThread() [2/2]

static void MipsISA::setRegOtherThread ( ExecContext *  xc,
const RegId &  reg,
RegVal  val,
ThreadID  tid = InvalidThreadID 
)
inlinestatic

Definition at line 111 of file mt.hh.

References X86ISA::reg, setRegOtherThread(), ExecContext::tcBase(), and X86ISA::val.

◆ signExtend()

uint64_t MipsISA::signExtend ( uint64_t  value,
int32_t  signpos 
)

Definition at line 114 of file dsp.cc.

References SIMD_NBITS, and ULL.

Referenced by simdUnpack().

◆ simdPack()

void MipsISA::simdPack ( uint64_t *  values_ptr,
int32_t *  reg,
int32_t  fmt 
)

Definition at line 1128 of file dsp.cc.

References bits(), i, SIMD_NBITS, and SIMD_NVALS.

Referenced by dspAbs(), dspAdd(), dspAddh(), dspMul(), dspMuleq(), dspMuleu(), dspMulq(), dspPack(), dspPick(), dspPrece(), dspPrecrq(), dspPrecrqu(), dspPrecrSra(), dspShll(), dspShra(), dspShrl(), dspSub(), and dspSubh().

◆ simdUnpack()

void MipsISA::simdUnpack ( int32_t  reg,
uint64_t *  values_ptr,
int32_t  fmt,
int32_t  sign 
)

Definition at line 1140 of file dsp.cc.

References bits(), i, SIGNED, signExtend(), SIMD_NBITS, SIMD_NVALS, and UNSIGNED.

Referenced by dspAbs(), dspAdd(), dspAddh(), dspCmp(), dspCmpg(), dspCmpgd(), dspDpa(), dspDpaq(), dspDps(), dspDpsq(), dspMaq(), dspMul(), dspMuleq(), dspMuleu(), dspMulq(), dspMulsa(), dspMulsaq(), dspPack(), dspPick(), dspPrece(), dspPrecrq(), dspPrecrqu(), dspPrecrSra(), dspShll(), dspShra(), dspShrl(), dspSub(), and dspSubh().

◆ skipFunction()

void MipsISA::skipFunction ( ThreadContext *  tc)

Definition at line 248 of file utility.cc.

References ThreadContext::pcState(), ThreadContext::readIntReg(), ReturnAddressReg, and GenericISA::DelaySlotPCState< MachInst >::set().

Referenced by RoundPage().

◆ SubBitUnion() [1/3]

MipsISA::SubBitUnion ( ejtagVer  ,
17  ,
15   
)

◆ SubBitUnion() [2/3]

MipsISA::SubBitUnion ( im  ,
15  ,
8   
)

◆ SubBitUnion() [3/3]

MipsISA::SubBitUnion ( ip  ,
15  ,
8   
)

◆ truncFP()

double MipsISA::truncFP ( double  val)

Definition at line 113 of file utility.cc.

Referenced by buildRetPC().

◆ TruncPage()

Addr MipsISA::TruncPage ( Addr  addr)
inline

Definition at line 95 of file utility.hh.

References PageBytes.

◆ updateStatusView()

template<class TC >
void MipsISA::updateStatusView ( TC *  tc)
inline

Definition at line 305 of file mt.hh.

References MISCREG_STATUS, MISCREG_TC_STATUS, and ArmISA::status.

◆ updateTCStatusView()

template<class TC >
void MipsISA::updateTCStatusView ( TC *  tc)
inline

Definition at line 323 of file mt.hh.

References MISCREG_STATUS, MISCREG_TC_STATUS, and ArmISA::status.

◆ VAddrImpl()

Addr MipsISA::VAddrImpl ( Addr  a)
inline

Definition at line 100 of file isa_traits.hh.

References VAddrImplMask.

◆ VAddrOffset()

Addr MipsISA::VAddrOffset ( Addr  a)
inline

Definition at line 102 of file isa_traits.hh.

References PageOffset.

◆ VAddrVPN()

Addr MipsISA::VAddrVPN ( Addr  a)
inline

Definition at line 101 of file isa_traits.hh.

References PageShift.

◆ vtophys() [1/2]

Addr MipsISA::vtophys ( Addr  vaddr)
inline

Definition at line 47 of file vtophys.cc.

References fatal.

◆ vtophys() [2/2]

Addr MipsISA::vtophys ( ThreadContext *  tc,
Addr  vaddr 
)
inline

Definition at line 54 of file vtophys.cc.

References fatal.

◆ writeDSPControl()

void MipsISA::writeDSPControl ( uint32_t *  dspctl,
uint32_t  value,
uint32_t  mask 
)

Definition at line 1162 of file dsp.cc.

References DSP_C, DSP_CCOND, DSP_CTL_MASK, DSP_EFI, DSP_OUFLAG, DSP_POS, and DSP_SCOUNT.

Referenced by dspAbs(), dspAdd(), dspCmp(), dspCmpgd(), dspMul(), dspMuleq(), dspMuleu(), dspMulq(), dspShll(), and dspSub().

◆ yieldThread()

template<class TC >
int MipsISA::yieldThread ( TC *  tc,
Fault &  fault,
int  src_reg,
uint32_t  yield_mask 
)

Definition at line 239 of file mt.hh.

References curTick(), MISCREG_MVP_CONF0, MISCREG_TC_BIND, MISCREG_TC_HALT, MISCREG_TC_STATUS, MISCREG_VPE_CONTROL, MiscRegClass, readRegOtherThread(), and warn.

Variable Documentation

◆ a

Bitfield<13> MipsISA::a

Definition at line 92 of file mt_constants.hh.

◆ a0

Bitfield<20, 18> MipsISA::a0

Definition at line 79 of file mt_constants.hh.

Referenced by ArmISA::add128(), ArmISA::mul62x62(), and ArmISA::sub128().

◆ ANNOTE_NONE

const int MipsISA::ANNOTE_NONE = 0

Definition at line 140 of file isa_traits.hh.

◆ ar

Bitfield<12, 10> MipsISA::ar

Definition at line 224 of file pra_constants.hh.

Referenced by ArmISA::DataAbort::annotate(), and ArmISA::DataAbort::iss().

◆ aseDn

Bitfield<12, 8> MipsISA::aseDn

Definition at line 82 of file pra_constants.hh.

◆ aseUp

MipsISA::aseUp

Definition at line 78 of file pra_constants.hh.

◆ asid

Bitfield< 23, 16 > MipsISA::asid

Definition at line 84 of file dt_constants.hh.

Referenced by MipsISA::TlbFault< TlbInvalidFault >::setTlbExceptionState().

◆ asidM

Bitfield<20, 13> MipsISA::asidM

Definition at line 83 of file dt_constants.hh.

◆ AssemblerReg

const int MipsISA::AssemblerReg = 1

Definition at line 111 of file registers.hh.

◆ at

Bitfield<14, 13> MipsISA::at

Definition at line 223 of file pra_constants.hh.

◆ ate

Bitfield<27> MipsISA::ate

Definition at line 107 of file dt_constants.hh.

Referenced by HsaObject::createHsaObject().

◆ badVPN2

Bitfield<22, 4> MipsISA::badVPN2

Definition at line 66 of file pra_constants.hh.

◆ be

Bitfield<15> MipsISA::be

Definition at line 222 of file pra_constants.hh.

Referenced by Request::setByteEnable().

◆ bev

Bitfield<22> MipsISA::bev

Definition at line 116 of file pra_constants.hh.

◆ bpc0

Bitfield<2, 0> MipsISA::bpc0

Definition at line 116 of file dt_constants.hh.

◆ bpc1

Bitfield<5, 3> MipsISA::bpc1

Definition at line 115 of file dt_constants.hh.

◆ bpc10

Bitfield<5, 3> MipsISA::bpc10

Definition at line 124 of file dt_constants.hh.

◆ bpc11

Bitfield<8, 6> MipsISA::bpc11

Definition at line 123 of file dt_constants.hh.

◆ bpc12

Bitfield<11, 9> MipsISA::bpc12

Definition at line 122 of file dt_constants.hh.

◆ bpc13

Bitfield<14, 12> MipsISA::bpc13

Definition at line 121 of file dt_constants.hh.

◆ bpc14

MipsISA::bpc14

Definition at line 120 of file dt_constants.hh.

◆ bpc2

Bitfield<8, 6> MipsISA::bpc2

Definition at line 114 of file dt_constants.hh.

◆ bpc3

Bitfield<11, 9> MipsISA::bpc3

Definition at line 113 of file dt_constants.hh.

◆ bpc4

Bitfield<14, 12> MipsISA::bpc4

Definition at line 112 of file dt_constants.hh.

◆ bpc5

Bitfield<17, 15> MipsISA::bpc5

Definition at line 111 of file dt_constants.hh.

◆ bpc6

Bitfield<20, 18> MipsISA::bpc6

Definition at line 110 of file dt_constants.hh.

◆ bpc7

Bitfield<23, 21> MipsISA::bpc7

Definition at line 109 of file dt_constants.hh.

◆ bpc8

Bitfield<26, 24> MipsISA::bpc8

Definition at line 108 of file dt_constants.hh.

◆ bpc9

Bitfield<2, 0> MipsISA::bpc9

Definition at line 125 of file dt_constants.hh.

◆ c

Bitfield<5, 3> MipsISA::c

Definition at line 58 of file pra_constants.hh.

◆ c2

Bitfield<6> MipsISA::c2

Definition at line 240 of file pra_constants.hh.

Referenced by MultiperspectivePerceptron::MPPBranchInfo::hash2(), sc_dt::overflow(), and SC_MODULE().

◆ ca

Bitfield<2> MipsISA::ca

Definition at line 244 of file pra_constants.hh.

◆ cacheep

Bitfield<22> MipsISA::cacheep

Definition at line 50 of file dt_constants.hh.

◆ ce

Bitfield<29, 28> MipsISA::ce

Definition at line 179 of file pra_constants.hh.

Referenced by SparcISA::TLB::translateData().

◆ coId

Bitfield<23, 16> MipsISA::coId

Definition at line 204 of file pra_constants.hh.

◆ conutdm

Bitfield<25> MipsISA::conutdm

Definition at line 47 of file dt_constants.hh.

◆ coOp

MipsISA::coOp

Definition at line 203 of file pra_constants.hh.

◆ cpuid

Bitfield<28, 21> MipsISA::cpuid

Definition at line 94 of file dt_constants.hh.

Referenced by Kvm::capXSave(), PseudoInst::decodeAddrOffset(), Kvm::getVCPUMMapSize(), CPA::hwWe(), AnnotateDumpCallback::process(), Iob::readJBus(), X86KvmCPU::updateCPUID(), PseudoInst::wakeCPU(), and Iob::writeJBus().

◆ cpuNum

Bitfield<9, 9> MipsISA::cpuNum

Definition at line 214 of file pra_constants.hh.

◆ css

Bitfield<3, 0> MipsISA::css

Definition at line 162 of file pra_constants.hh.

◆ cu0

Bitfield<28> MipsISA::cu0

Definition at line 109 of file pra_constants.hh.

◆ cu1

Bitfield<29> MipsISA::cu1

Definition at line 108 of file pra_constants.hh.

◆ cu2

Bitfield<30> MipsISA::cu2

Definition at line 107 of file pra_constants.hh.

◆ cu3

Bitfield<31> MipsISA::cu3

Definition at line 105 of file pra_constants.hh.

◆ curTC

MipsISA::curTC

Definition at line 78 of file mt_constants.hh.

◆ CurThreadInfoImplemented

const bool MipsISA::CurThreadInfoImplemented = false

Definition at line 145 of file isa_traits.hh.

◆ CurThreadInfoReg

const int MipsISA::CurThreadInfoReg = -1

Definition at line 146 of file isa_traits.hh.

◆ curVPE

Bitfield<3, 0> MipsISA::curVPE

Definition at line 81 of file mt_constants.hh.

◆ d

Bitfield< 2 > MipsISA::d

Definition at line 78 of file dt_constants.hh.

◆ da

Bitfield< 9, 7 > MipsISA::da

Definition at line 91 of file mt_constants.hh.

◆ dbp

Bitfield<1> MipsISA::dbp

Definition at line 69 of file dt_constants.hh.

◆ dbusep

Bitfield<21> MipsISA::dbusep

Definition at line 51 of file dt_constants.hh.

◆ dc

Bitfield<27> MipsISA::dc

Definition at line 180 of file pra_constants.hh.

◆ dcs

Bitfield<17> MipsISA::dcs

Definition at line 71 of file mt_constants.hh.

◆ ddbl

Bitfield<2> MipsISA::ddbl

Definition at line 68 of file dt_constants.hh.

◆ ddblImpr

Bitfield<18> MipsISA::ddblImpr

Definition at line 54 of file dt_constants.hh.

◆ ddbs

Bitfield<3> MipsISA::ddbs

Definition at line 67 of file dt_constants.hh.

◆ ddbsImpr

Bitfield<19> MipsISA::ddbsImpr

Definition at line 53 of file dt_constants.hh.

◆ dexcCode

MipsISA::dexcCode

Definition at line 60 of file dt_constants.hh.

◆ dib

Bitfield<4> MipsISA::dib

Definition at line 66 of file dt_constants.hh.

◆ dibimpr

Bitfield<6> MipsISA::dibimpr

Definition at line 64 of file dt_constants.hh.

◆ dint

Bitfield<5> MipsISA::dint

Definition at line 65 of file dt_constants.hh.

◆ dl

Bitfield<12, 10> MipsISA::dl

Definition at line 238 of file pra_constants.hh.

◆ dm

Bitfield<30> MipsISA::dm

Definition at line 42 of file dt_constants.hh.

◆ doze

Bitfield<27> MipsISA::doze

Definition at line 45 of file dt_constants.hh.

◆ dq

Bitfield<2> MipsISA::dq

Definition at line 130 of file dt_constants.hh.

◆ ds

Bitfield<15, 13> MipsISA::ds

Definition at line 237 of file pra_constants.hh.

Referenced by X86System::initState(), and X86ISA::X86_64Process::initState().

◆ DSP_CTL_MASK

const uint32_t MipsISA::DSP_CTL_MASK[DSP_NUM_FIELDS]
Initial value:
=
{ 0x0000003f, 0x00001f80, 0x00002000,
0x00ff0000, 0x0f000000, 0x00004000 }

Definition at line 86 of file dsp.hh.

Referenced by readDSPControl(), and writeDSPControl().

◆ DSP_CTL_POS

const uint32_t MipsISA::DSP_CTL_POS[DSP_NUM_FIELDS] = { 0, 7, 13, 16, 24, 14 }

Definition at line 85 of file dsp.hh.

Referenced by dspAbs(), dspAdd(), dspCmp(), dspCmpgd(), dspMul(), dspMuleq(), dspMuleu(), dspMulq(), dspPick(), dspShll(), and dspSub().

◆ dspp

Bitfield<10> MipsISA::dspp

Definition at line 264 of file pra_constants.hh.

◆ dss

Bitfield<0> MipsISA::dss

Definition at line 70 of file dt_constants.hh.

◆ dt

Bitfield<20> MipsISA::dt

Definition at line 89 of file mt_constants.hh.

◆ e

Bitfield< 28 > MipsISA::e

Definition at line 79 of file dt_constants.hh.

◆ eb

Bitfield<25> MipsISA::eb

Definition at line 314 of file pra_constants.hh.

◆ ec

Bitfield<30> MipsISA::ec

Definition at line 309 of file pra_constants.hh.

◆ ed

Bitfield<29> MipsISA::ed

Definition at line 310 of file pra_constants.hh.

◆ ee

Bitfield<26> MipsISA::ee

Definition at line 313 of file pra_constants.hh.

◆ eicss

Bitfield<21, 18> MipsISA::eicss

Definition at line 156 of file pra_constants.hh.

◆ ejtagVer0

Bitfield<15> MipsISA::ejtagVer0

Definition at line 58 of file dt_constants.hh.

◆ ejtagVer1

Bitfield<16> MipsISA::ejtagVer1

Definition at line 57 of file dt_constants.hh.

◆ elpa

Bitfield<29> MipsISA::elpa

Definition at line 79 of file pra_constants.hh.

◆ ep

Bitfield<1> MipsISA::ep

Definition at line 245 of file pra_constants.hh.

Referenced by SMMUProcess::scheduleWakeup().

◆ erl

Bitfield<2> MipsISA::erl

Definition at line 139 of file pra_constants.hh.

◆ es

Bitfield<27> MipsISA::es

Definition at line 312 of file pra_constants.hh.

◆ esp

Bitfield<28> MipsISA::esp

Definition at line 80 of file pra_constants.hh.

◆ ess

Bitfield<15, 12> MipsISA::ess

Definition at line 158 of file pra_constants.hh.

◆ et

Bitfield<28> MipsISA::et

Definition at line 311 of file pra_constants.hh.

◆ event

Bitfield<10, 5> MipsISA::event

Definition at line 299 of file pra_constants.hh.

Referenced by FlashDevice::accessDevice(), ArmISA::PMU::addEventProbe(), ArmISA::PMU::CounterState::attach(), BaseCPU::BaseCPU(), sc_gem5::SensitivityEvents::clear(), ArmISA::PMU::CounterState::CounterState(), EventQueue::deschedule(), ArmISA::TableWalker::doLongDescriptor(), Trace::TarmacParserRecord::dump(), sc_gem5::ScSignalBaseT< sc_dt::sc_logic, WRITER_POLICY >::event(), Pl111::fillFifo(), DmaReadFifo::handlePending(), BaseCPU::init(), Event::insertBefore(), Iris::ThreadContext::instanceRegistryChanged(), sc_gem5::ScSignalBase::kind(), RubySystem::memWriteback(), EventQueue::name(), Iris::ThreadContext::noThrow(), GpuDispatcher::notifyWgCompl(), ArmISA::PMU::regProbeListeners(), EventQueue::reschedule(), DmaReadFifo::resumeFillTiming(), sc_gem5::Scheduler::schedule(), BaseCPU::scheduleInstStop(), BasePixelPump::serialize(), DVFSHandler::serialize(), IdeDisk::serialize(), EventQueue::serviceOne(), DistEtherLink::Link::unserialize(), BasePixelPump::unserialize(), DVFSHandler::unserialize(), IdeDisk::unserialize(), FlashDevice::writeMemory(), AbstractNVM::~AbstractNVM(), sc_gem5::Object::~Object(), and ThreadContext::~ThreadContext().

◆ evp

Bitfield<0> MipsISA::evp

Definition at line 45 of file mt_constants.hh.

◆ excCode

Bitfield<6, 2> MipsISA::excCode

Definition at line 198 of file pra_constants.hh.

Referenced by MipsISA::MipsFaultBase::setExceptionState().

◆ exceptionBase

MipsISA::exceptionBase

Definition at line 212 of file pra_constants.hh.

◆ excpt

Bitfield<18, 16> MipsISA::excpt

Definition at line 61 of file mt_constants.hh.

◆ exl

Bitfield< 0 > MipsISA::exl

Definition at line 140 of file pra_constants.hh.

◆ fill

Bitfield< 61, 40 > MipsISA::fill

Definition at line 56 of file pra_constants.hh.

Referenced by sc_dt::sc_proxy< sc_subref_r< X > >::assign_(), sc_dt::sc_bv_base::assign_from_string(), sc_dt::sc_lv_base::assign_from_string(), RiscvISA::ISA::clear(), AlphaISA::TLB::flushAll(), DRAMCtrl::minBankPrep(), sc_dt::operator<<(), GenericPciHost::read(), DictionaryCompressor< uint64_t >::resetDictionary(), MSHR::TargetList::resetFlags(), and MSHR::TargetList::updateWriteFlags().

◆ FirstArgumentReg

const int MipsISA::FirstArgumentReg = 4

Definition at line 113 of file registers.hh.

◆ FIXED_B_SMAX

const uint64_t MipsISA::FIXED_B_SMAX = ULL(0x000000000000007f)

Definition at line 108 of file dsp.hh.

◆ FIXED_B_SMIN

const uint64_t MipsISA::FIXED_B_SMIN = ULL(0xffffffffffffff80)

Definition at line 122 of file dsp.hh.

◆ FIXED_B_UMAX

const uint64_t MipsISA::FIXED_B_UMAX = ULL(0x00000000000000ff)

Definition at line 112 of file dsp.hh.

◆ FIXED_B_UMIN

const uint64_t MipsISA::FIXED_B_UMIN = ULL(0x0000000000000000)

Definition at line 126 of file dsp.hh.

◆ FIXED_H_SMAX

const uint64_t MipsISA::FIXED_H_SMAX = ULL(0x0000000000007fff)

Definition at line 107 of file dsp.hh.

◆ FIXED_H_SMIN

const uint64_t MipsISA::FIXED_H_SMIN = ULL(0xffffffffffff8000)

Definition at line 121 of file dsp.hh.

◆ FIXED_H_UMAX

const uint64_t MipsISA::FIXED_H_UMAX = ULL(0x000000000000ffff)

Definition at line 111 of file dsp.hh.

◆ FIXED_H_UMIN

const uint64_t MipsISA::FIXED_H_UMIN = ULL(0x0000000000000000)

Definition at line 125 of file dsp.hh.

◆ FIXED_L_SMAX

const uint64_t MipsISA::FIXED_L_SMAX = ULL(0x7fffffffffffffff)

Definition at line 105 of file dsp.hh.

◆ FIXED_L_SMIN

const uint64_t MipsISA::FIXED_L_SMIN = ULL(0x8000000000000000)

Definition at line 119 of file dsp.hh.

◆ FIXED_L_UMAX

const uint64_t MipsISA::FIXED_L_UMAX = ULL(0xffffffffffffffff)

Definition at line 109 of file dsp.hh.

◆ FIXED_L_UMIN

const uint64_t MipsISA::FIXED_L_UMIN = ULL(0x0000000000000000)

Definition at line 123 of file dsp.hh.

◆ FIXED_SMAX

const uint64_t MipsISA::FIXED_SMAX[SIMD_NUM_FMTS]
Initial value:
=
{ FIXED_L_SMAX, FIXED_W_SMAX, FIXED_H_SMAX, FIXED_B_SMAX }
MipsISA::FIXED_B_SMAX
const uint64_t FIXED_B_SMAX
Definition: dsp.hh:108
MipsISA::FIXED_W_SMAX
const uint64_t FIXED_W_SMAX
Definition: dsp.hh:106
MipsISA::FIXED_L_SMAX
const uint64_t FIXED_L_SMAX
Definition: dsp.hh:105
MipsISA::FIXED_H_SMAX
const uint64_t FIXED_H_SMAX
Definition: dsp.hh:107

Definition at line 113 of file dsp.hh.

Referenced by checkOverflow(), dspAbs(), dspDpaq(), dspDpsq(), dspExtr(), dspMaq(), dspMulq(), dspMulsaq(), and dspSaturate().

◆ FIXED_SMIN

const uint64_t MipsISA::FIXED_SMIN[SIMD_NUM_FMTS]
Initial value:
=
{ FIXED_L_SMIN, FIXED_W_SMIN, FIXED_H_SMIN, FIXED_B_SMIN }
MipsISA::FIXED_B_SMIN
const uint64_t FIXED_B_SMIN
Definition: dsp.hh:122
MipsISA::FIXED_W_SMIN
const uint64_t FIXED_W_SMIN
Definition: dsp.hh:120
MipsISA::FIXED_H_SMIN
const uint64_t FIXED_H_SMIN
Definition: dsp.hh:121
MipsISA::FIXED_L_SMIN
const uint64_t FIXED_L_SMIN
Definition: dsp.hh:119

Definition at line 127 of file dsp.hh.

Referenced by checkOverflow(), dspAbs(), dspDpaq(), dspDpsq(), dspMaq(), dspMulq(), dspMulsaq(), and dspSaturate().

◆ FIXED_UMAX

const uint64_t MipsISA::FIXED_UMAX[SIMD_NUM_FMTS]
Initial value:
=
{ FIXED_L_UMAX, FIXED_W_UMAX, FIXED_H_UMAX, FIXED_B_UMAX }
MipsISA::FIXED_B_UMAX
const uint64_t FIXED_B_UMAX
Definition: dsp.hh:112
MipsISA::FIXED_W_UMAX
const uint64_t FIXED_W_UMAX
Definition: dsp.hh:110
MipsISA::FIXED_L_UMAX
const uint64_t FIXED_L_UMAX
Definition: dsp.hh:109
MipsISA::FIXED_H_UMAX
const uint64_t FIXED_H_UMAX
Definition: dsp.hh:111

Definition at line 115 of file dsp.hh.

Referenced by checkOverflow(), and dspSaturate().

◆ FIXED_UMIN

const uint64_t MipsISA::FIXED_UMIN[SIMD_NUM_FMTS]
Initial value:
=
{ FIXED_L_UMIN, FIXED_W_UMIN, FIXED_H_UMIN, FIXED_B_UMIN }
MipsISA::FIXED_L_UMIN
const uint64_t FIXED_L_UMIN
Definition: dsp.hh:123
MipsISA::FIXED_H_UMIN
const uint64_t FIXED_H_UMIN
Definition: dsp.hh:125
MipsISA::FIXED_B_UMIN
const uint64_t FIXED_B_UMIN
Definition: dsp.hh:126
MipsISA::FIXED_W_UMIN
const uint64_t FIXED_W_UMIN
Definition: dsp.hh:124

Definition at line 129 of file dsp.hh.

Referenced by checkOverflow(), and dspSaturate().

◆ FIXED_W_SMAX

const uint64_t MipsISA::FIXED_W_SMAX = ULL(0x000000007fffffff)

Definition at line 106 of file dsp.hh.

◆ FIXED_W_SMIN

const uint64_t MipsISA::FIXED_W_SMIN = ULL(0xffffffff80000000)

Definition at line 120 of file dsp.hh.

◆ FIXED_W_UMAX

const uint64_t MipsISA::FIXED_W_UMAX = ULL(0x00000000ffffffff)

Definition at line 110 of file dsp.hh.

◆ FIXED_W_UMIN

const uint64_t MipsISA::FIXED_W_UMIN = ULL(0x0000000000000000)

Definition at line 124 of file dsp.hh.

◆ fp

Bitfield<0> MipsISA::fp

Definition at line 246 of file pra_constants.hh.

Referenced by buildRetPC().

◆ fr

Bitfield<26> MipsISA::fr

Definition at line 112 of file pra_constants.hh.

◆ FramePointerReg

const int MipsISA::FramePointerReg = 30

Definition at line 120 of file registers.hh.

◆ g

Bitfield< 30 > MipsISA::g

Definition at line 85 of file dt_constants.hh.

Referenced by MultiperspectivePerceptronTAGE::getIndex(), MultiperspectivePerceptron::getIndex(), SparcISA::SparcStaticInst::passesFpCondition(), Stats::Group::preDumpStats(), QTIsaac< ALPHA >::randinit(), Stats::Group::regStats(), Stats::Group::resetStats(), QTIsaac< ALPHA >::shuffle(), and QTIsaac< ALPHA >::randctx::~randctx().

◆ GlobalPointerReg

const int MipsISA::GlobalPointerReg = 28

Definition at line 118 of file registers.hh.

◆ gs

Bitfield<28> MipsISA::gs

Definition at line 51 of file mt_constants.hh.

◆ GuestByteOrder

const ByteOrder MipsISA::GuestByteOrder = LittleEndianByteOrder

Definition at line 44 of file isa_traits.hh.

Referenced by MipsISA::ProcessInfo::pid(), and MipsISA::ProcessInfo::task().

◆ halt

Bitfield<26> MipsISA::halt

Definition at line 46 of file dt_constants.hh.

Referenced by SC_MODULE(), O3ThreadContext< Impl >::setStatus(), SimpleThread::setStatus(), and ThreadContext::~ThreadContext().

◆ HasUnalignedMemAcc

const bool MipsISA::HasUnalignedMemAcc = true

Definition at line 143 of file isa_traits.hh.

◆ hss

MipsISA::hss

Definition at line 154 of file pra_constants.hh.

◆ i

Bitfield< 2 > MipsISA::i

Definition at line 278 of file pra_constants.hh.

Referenced by bitrev(), MipsISA::ISA::clear(), copyRegs(), dspAbs(), dspAdd(), dspAddh(), dspCmp(), dspCmpg(), dspCmpgd(), dspDpa(), dspDpaq(), dspDps(), dspDpsq(), dspMaq(), dspMul(), dspMuleq(), dspMuleu(), dspMulq(), dspMulsaq(), dspPick(), dspPrece(), dspPrecrqu(), dspPrecrSra(), dspShll(), dspShra(), dspShrl(), dspSub(), dspSubh(), MipsISA::RemoteGDB::MipsGdbRegCache::getRegs(), MipsISA::TLB::insertAt(), MipsISA::ISA::ISA(), MipsISA::TLB::lookup(), MipsISA::TLB::probeEntry(), MipsISA::TLB::serialize(), MipsISA::RemoteGDB::MipsGdbRegCache::setRegs(), simdPack(), simdUnpack(), and MipsISA::TLB::unserialize().

◆ ia

Bitfield<18, 16> MipsISA::ia

Definition at line 236 of file pra_constants.hh.

Referenced by Net::IpAddress::ip().

◆ ibusep

Bitfield<24> MipsISA::ibusep

Definition at line 48 of file dt_constants.hh.

◆ ics

Bitfield<16> MipsISA::ics

Definition at line 72 of file mt_constants.hh.

◆ ie

Bitfield< 4 > MipsISA::ie

Definition at line 141 of file pra_constants.hh.

◆ iexi

Bitfield<20, 19> MipsISA::iexi

Definition at line 52 of file dt_constants.hh.

◆ il

Bitfield<21, 19> MipsISA::il

Definition at line 235 of file pra_constants.hh.

◆ im0

Bitfield<8> MipsISA::im0

Definition at line 131 of file pra_constants.hh.

◆ im1

Bitfield<9> MipsISA::im1

Definition at line 130 of file pra_constants.hh.

◆ im2

Bitfield<10> MipsISA::im2

Definition at line 129 of file pra_constants.hh.

◆ im3

Bitfield<11> MipsISA::im3

Definition at line 128 of file pra_constants.hh.

◆ im4

Bitfield<12> MipsISA::im4

Definition at line 127 of file pra_constants.hh.

◆ im5

Bitfield<13> MipsISA::im5

Definition at line 126 of file pra_constants.hh.

◆ im6

Bitfield<14> MipsISA::im6

Definition at line 125 of file pra_constants.hh.

◆ impl

Bitfield< 4, 3 > MipsISA::impl

Definition at line 90 of file mt_constants.hh.

Referenced by TEST().

◆ index

Bitfield< 22, 0 > MipsISA::index

Definition at line 46 of file pra_constants.hh.

Referenced by FlashDevice::accessDevice(), Prefetcher::accessUnitFilter(), Histogram::add(), sc_dt::add_mants(), IndirectMemoryPrefetcher::allocateOrUpdateIPDEntry(), archPrctlFunc(), sc_core::sc_vector< svp_gicv3_comms::gicv3_comms_target_socket<> >::at(), NetDest::bitIndex(), LoopPredictor::BranchInfo::BranchInfo(), PowerISA::BranchRegCond::branchTarget(), MPP_LoopPredictor::calcConf(), TAGE_SC_L_LoopPredictor::calcConf(), LoopPredictor::calcConf(), IndirectMemoryPrefetcher::calculatePrefetch(), Minor::Scoreboard::canInstIssue(), StoreSet::checkInst(), IntrControl::clear(), AlphaISA::Interrupts::clear(), SparcISA::Interrupts::clear(), tlm_utils::instance_specific_extensions_per_accessor::clear_extension(), tlm::tlm_generic_payload::clear_extension(), TimingSimpleCPU::SplitFragmentSenderState::clearFromParent(), Minor::Scoreboard::clearInstDests(), Prefetcher::clearNonunitEntry(), cloneFunc(), MultiCompressor::compress(), VirtQueue::consumeDescriptor(), Stats::VectorBase< Vector, StatStor >::data(), Stats::Vector2dBase< Vector2d, StatStor >::data(), Stats::VectorDistBase< VectorAverageDeviation, AvgSampleStor >::data(), sc_dt::div_scfx_rep(), DVFSHandler::domainID(), SMMUTranslationProcess::doReadSTE(), SyscallDesc::doSyscall(), Set::elementAt(), TimingExprSrcReg::eval(), TimingExprRef::eval(), Minor::Scoreboard::execSeqNumToWaitFor(), fcntl64Func(), fcntlFunc(), MultiperspectivePerceptron::findBest(), WholeTranslationState::finish(), Sparc32Process::flushWindows(), Sparc64Process::flushWindows(), ftruncate64Func(), SparcISA::Mem::generateDisassembly(), SparcISA::MemImm::generateDisassembly(), SparcISA::WrPriv::generateDisassembly(), SparcISA::WrPrivImm::generateDisassembly(), ArmISA::SveBinIdxUnpredOp::generateDisassembly(), tlm::tlm_generic_payload::get_extension(), Histogram::getData(), AbstractController::getDelayVCHist(), getEventQueue(), MultiperspectivePerceptronTAGE::getIndex(), MultiperspectivePerceptron::getIndex(), getMiscRegName(), X86KvmCPU::getMSR(), CxxConfigManager::getObject(), SparcISA::getresuidFunc(), NetDest::getSize(), PowerISA::TLB::getsize(), O3ThreadContext< Impl >::getWritableVecPredReg(), O3ThreadContext< Impl >::getWritableVecReg(), TAGE_SC_L_TAGE::gindex(), TAGEBase::gindex(), TAGE_SC_L_TAGE_64KB::gindex_ext(), StatisticalCorrector::gPredict(), MPP_StatisticalCorrector::gUpdate(), StatisticalCorrector::gUpdate(), sc_core::sc_vector_base::implicitCast(), PhysRegFile::initFreeList(), Prefetcher::initializeStream(), Check::initiateAction(), Check::initiateCheck(), Check::initiateFlush(), Check::initiatePrefetch(), SBOOEPrefetcher::Sandbox::insert(), MultiperspectivePerceptron::insert(), StoreSet::insertStore(), ArmISA::INTREG_ABT(), ArmISA::INTREG_FIQ(), ArmISA::INTREG_HYP(), ArmISA::INTREG_IRQ(), ArmISA::INTREG_MON(), ArmISA::INTREG_SVC(), ArmISA::INTREG_UND(), ArmISA::INTREG_USR(), ClDriver::ioctl(), ioctlFunc(), StoreSet::issued(), Prefetcher::issueNextPrefetch(), makeKvmCpuid(), Minor::Scoreboard::markupInstDests(), System::markWorkItem(), MPP_LoopPredictor::MPP_LoopPredictor(), mremapFunc(), PAL::name(), sc_dt::next_pow2_index(), ComputeUnit::nextLocRdBus(), DVFSHandler::numDomains(), Prefetcher::observeMiss(), Arguments::operator+=(), Arguments::operator-=(), MultiperspectivePerceptron::LocalHistories::operator[](), CircularQueue< T >::iterator::operator[](), sc_core::sc_vector< svp_gicv3_comms::gicv3_comms_target_socket<> >::operator[](), Stats::VectorProxy< Stat >::operator[](), osf_getsysinfoFunc(), osf_setsysinfoFunc(), pipeImpl(), pollFunc(), IntrControl::post(), AlphaISA::Interrupts::post(), SparcISA::Interrupts::post(), Sinic::Device::prepareRead(), ArmISA::MemoryReg::printOffset(), SparcISA::IntOp::printPseudoOps(), SparcISA::IntOpImm::printPseudoOps(), ComputeUnit::DataPort::processMemReqEvent(), ComputeUnit::DataPort::processMemRespEvent(), Sinic::Device::read(), Pl111::read(), O3ThreadContext< Impl >::readCCReg(), O3ThreadContext< Impl >::readFloatReg(), O3ThreadContext< Impl >::readIntReg(), Iob::readIob(), Iob::readJBus(), O3ThreadContext< Impl >::readReg(), O3ThreadContext< Impl >::readVecElem(), O3ThreadContext< Impl >::readVecPredReg(), O3ThreadContext< Impl >::readVecReg(), ComputeUnit::DataPort::recvTimingResp(), ArmISA::PMU::regProbeListeners(), tlm::tlm_generic_payload::release_extension(), Set::remove(), Stats::DistStor::sample(), Stats::HistStor::sample(), ComputeUnit::sendRequest(), ComputeUnit::sendSyncRequest(), tlm::tlm_generic_payload::set_auto_extension(), tlm_utils::instance_specific_extensions_per_accessor::set_extension(), tlm::tlm_generic_payload::set_extension(), O3ThreadContext< Impl >::setCCReg(), Prefetcher::setController(), MipsISA::Interrupts::setCPU(), O3ThreadContext< Impl >::setFloatReg(), O3ThreadContext< Impl >::setIntReg(), X86KvmCPU::setMSR(), setThreadArea32Func(), setThreadAreaFunc(), setTLSFunc32(), setTLSFunc64(), O3ThreadContext< Impl >::setVecElem(), O3ThreadContext< Impl >::setVecLane(), O3ThreadContext< Impl >::setVecPredReg(), O3ThreadContext< Impl >::setVecReg(), LoopPredictor::specLoopUpdate(), Stats::ScalarProxy< Stat >::str(), sc_dt::sub_mants(), Stats::DataWrapVec< VectorStandardDeviation, VectorDistInfoProxy >::subdesc(), Stats::DataWrapVec< VectorStandardDeviation, VectorDistInfoProxy >::subname(), sys_getsysinfoFunc(), sys_setsysinfoFunc(), sysctlFunc(), TAGE_SC_L_LoopPredictor::TAGE_SC_L_LoopPredictor(), TAGE_SC_L_TAGE::TAGE_SC_L_TAGE(), TAGE_SC_L_TAGE_64KB::TAGE_SC_L_TAGE_64KB(), TAGE_SC_L_TAGE_8KB::TAGE_SC_L_TAGE_8KB(), TEST(), sc_dt::sc_logic::to_value(), SparcISA::unameFunc(), unameFunc(), unameFunc32(), unameFunc64(), MultiperspectivePerceptron::LocalHistories::update(), MPP_StatisticalCorrector::MPP_SCThreadHistory::updateHistoryStack(), Sinic::Device::write(), Pl111::write(), Iob::writeIob(), Iob::writeJBus(), FlashDevice::writeMemory(), Stats::DataWrapVec2d< Derived, Vector2dInfoProxy >::ysubname(), BaseIndexingPolicy::~BaseIndexingPolicy(), and MultiperspectivePerceptronTAGE::MPPTAGEBranchInfo::~MPPTAGEBranchInfo().

◆ io

Bitfield<26> MipsISA::io

Definition at line 77 of file dt_constants.hh.

◆ ip0

Bitfield<8> MipsISA::ip0

Definition at line 195 of file pra_constants.hh.

◆ ip1

Bitfield<9> MipsISA::ip1

Definition at line 194 of file pra_constants.hh.

◆ ip2

Bitfield<10> MipsISA::ip2

Definition at line 193 of file pra_constants.hh.

◆ ip3

Bitfield<11> MipsISA::ip3

Definition at line 192 of file pra_constants.hh.

◆ ip4

Bitfield<12> MipsISA::ip4

Definition at line 191 of file pra_constants.hh.

◆ ip5

Bitfield<13> MipsISA::ip5

Definition at line 190 of file pra_constants.hh.

◆ ip6

Bitfield<14> MipsISA::ip6

Definition at line 189 of file pra_constants.hh.

Referenced by Net::hsplit(), IGbE::RxDescCache::pktComplete(), IGbE::TxDescCache::pktComplete(), and Net::UdpPtr::pstart().

◆ ipl

Bitfield<15, 10> MipsISA::ipl

Definition at line 122 of file pra_constants.hh.

Referenced by AlphaISA::Interrupts::checkInterrupts(), AlphaISA::Interrupts::getInterrupt(), AlphaISA::Kernel::Statistics::hwrei(), and AlphaISA::Kernel::Statistics::swpipl().

◆ ippci

Bitfield<28, 26> MipsISA::ippci

Definition at line 146 of file pra_constants.hh.

◆ ipti

MipsISA::ipti

Definition at line 145 of file pra_constants.hh.

◆ is

Bitfield<24, 22> MipsISA::is

Definition at line 234 of file pra_constants.hh.

Referenced by sc_dt::sc_bitref< X >::clean_tail(), X86ISA::m5PageFault(), sc_dt::sc_uint_subref::operator=(), sc_dt::sc_int_subref::operator=(), sc_dt::sc_unsigned_subref::operator=(), sc_dt::sc_signed_subref::operator=(), sc_dt::operator>>(), TrafficGen::parseConfig(), sc_dt::sc_logic::print(), sc_dt::sc_proxy< sc_subref_r< X > >::print(), sc_dt::sc_uint_base::print(), sc_dt::sc_int_base::print(), sc_dt::sc_unsigned::print(), sc_dt::sc_signed::print(), sc_dt::sc_int_bitref::sc_int_bitref(), sc_dt::sc_signed_bitref::sc_signed_bitref(), sc_dt::sc_uint_bitref::sc_uint_bitref(), and sc_dt::sc_unsigned_bitref::sc_unsigned_bitref().

◆ ITOUCH_ANNOTE

const uint32_t MipsISA::ITOUCH_ANNOTE = 0xffffffff

Definition at line 141 of file isa_traits.hh.

◆ iv

Bitfield<23> MipsISA::iv

Definition at line 183 of file pra_constants.hh.

◆ ixmt

Bitfield<10> MipsISA::ixmt

Definition at line 94 of file mt_constants.hh.

◆ k

Bitfield< 1 > MipsISA::k

Definition at line 80 of file dt_constants.hh.

Referenced by ClDriver::ClDriver(), MipsISA::ISA::clear(), Profiler::collateStats(), HsailISA::LdInst< MemDataType, DestDataType, AddrOperandType >::completeAcc(), ComputeUnit::ComputeUnit(), Debug::CompoundFlag::disable(), Debug::CompoundFlag::enable(), SimpleLTInitiator2_dmi::end_of_simulation(), SimpleLTInitiator1_dmi::end_of_simulation(), SimpleLTInitiator_ext::end_of_simulation(), HsailISA::StInst< MemDataType, SrcDataType, AddrOperandType >::execSt(), HsailISA::StInst< MemDataType, SrcDataType, AddrOperandType >::execute(), Topology::extend_shortest_path(), FUPool::FUPool(), sc_dt::sc_subref_r< X >::get_cword(), sc_dt::scfx_rep::get_slice(), sc_dt::sc_fxnum_fast::get_slice(), sc_dt::sc_subref_r< X >::get_word(), MultiperspectivePerceptron::ACYCLIC::getHash(), MultiperspectivePerceptron::MODHIST::getHash(), MultiperspectivePerceptron::RECENCY::getHash(), MultiperspectivePerceptron::PATH::getHash(), MultiperspectivePerceptron::GHISTPATH::getHash(), Prefetcher::initializeStream(), HsailISA::LdInst< MemDataType, DestDataType, AddrOperandType >::initiateAcc(), ClDriver::ioctl(), sc_dt::sc_subref_r< X >::set_cword(), sc_dt::scfx_rep::set_slice(), sc_dt::sc_fxnum_fast::set_slice(), sc_dt::sc_subref_r< X >::set_word(), ComputeUnit::startWavefront(), CompressedTags::tagsInit(), SectorTags::tagsInit(), MultiperspectivePerceptron::ThreadData::ThreadData(), sc_dt::vec_div_large(), and sc_dt::vec_rem_large().

◆ k0

Bitfield<2, 0> MipsISA::k0

Definition at line 228 of file pra_constants.hh.

Referenced by ArmISA::upperAndLowerRange().

◆ k23

Bitfield<30, 28> MipsISA::k23

Definition at line 219 of file pra_constants.hh.

◆ KernelReg0

const int MipsISA::KernelReg0 = 26

Definition at line 116 of file registers.hh.

◆ KernelReg1

const int MipsISA::KernelReg1 = 27

Definition at line 117 of file registers.hh.

◆ KSeg0Base

const Addr MipsISA::KSeg0Base = ULL(0x80000000)

Definition at line 73 of file isa_traits.hh.

Referenced by Phys2K0Seg().

◆ KSeg0End

const Addr MipsISA::KSeg0End = ULL(0x9FFFFFFF)

Definition at line 72 of file isa_traits.hh.

◆ KSeg0Mask

const Addr MipsISA::KSeg0Mask = ULL(0x1FFFFFFF)

Definition at line 74 of file isa_traits.hh.

◆ KSeg1Base

const Addr MipsISA::KSeg1Base = ULL(0xA0000000)

Definition at line 78 of file isa_traits.hh.

◆ KSeg1End

const Addr MipsISA::KSeg1End = ULL(0xBFFFFFFF)

Definition at line 77 of file isa_traits.hh.

◆ KSeg1Mask

const Addr MipsISA::KSeg1Mask = ULL(0x1FFFFFFF)

Definition at line 79 of file isa_traits.hh.

◆ KSeg3Base

const Addr MipsISA::KSeg3Base = ULL(0xE0000000)

Definition at line 87 of file isa_traits.hh.

◆ KSeg3End

const Addr MipsISA::KSeg3End = ULL(0xFFFFFFFF)

Definition at line 86 of file isa_traits.hh.

◆ KSSegBase

const Addr MipsISA::KSSegBase = ULL(0xC0000000)

Definition at line 83 of file isa_traits.hh.

◆ KSSegEnd

const Addr MipsISA::KSSegEnd = ULL(0xDFFFFFFF)

Definition at line 82 of file isa_traits.hh.

◆ ksu

Bitfield<4, 3> MipsISA::ksu

Definition at line 136 of file pra_constants.hh.

◆ ku

Bitfield<27, 25> MipsISA::ku

Definition at line 220 of file pra_constants.hh.

◆ l

Bitfield<5> MipsISA::l

Definition at line 322 of file pra_constants.hh.

Referenced by ProbePointArg< RequestPtr >::addListener(), PerfectSwitch::addOutPort(), sc_dt::sc_unsigned::check_range(), sc_dt::sc_signed::check_range(), CacheBlk::checkWrite(), CacheBlk::clearLoadLocks(), sc_dt::sc_concref_r< X, Y >::get_cword(), sc_dt::scfx_rep::get_slice(), sc_dt::sc_fxnum_fast::get_slice(), sc_dt::sc_concref_r< X, Y >::get_word(), MultiperspectivePerceptron::RECENCYPOS::hash(), sc_core::sc_inout< sc_dt::sc_logic >::initialize(), tlm_utils::callback_binder_bw< tlm::tlm_base_protocol_types >::invalidate_direct_mem_ptr(), ArmISA::ISA::MiscRegLUTEntryInitializer::mapsTo(), ProbePointArg< RequestPtr >::notify(), sc_dt::operator<<(), operator>(), MathExpr::parse(), SparcISA::SparcStaticInst::passesFpCondition(), RubyPort::PioSlavePort::recvAtomic(), RubyPort::PioSlavePort::recvTimingReq(), WalkCache::regStats(), ProbePointArg< RequestPtr >::removeListener(), PhysicalMemory::serialize(), sc_dt::sc_concref_r< X, Y >::set_cword(), sc_dt::scfx_rep::set_slice(), sc_dt::sc_fxnum_fast::set_slice(), sc_dt::sc_concref_r< X, Y >::set_word(), UnifiedRenameMap::switchMode(), CacheBlk::trackLoadLocked(), sc_core::sc_signal_resolved::write(), sc_core::sc_signal_rv< W >::write(), CoherentXBar::~CoherentXBar(), NoncoherentXBar::~NoncoherentXBar(), and ProbeListenerObject::~ProbeListenerObject().

◆ lpa

Bitfield<7> MipsISA::lpa

Definition at line 266 of file pra_constants.hh.

◆ lsnm

Bitfield<28> MipsISA::lsnm

Definition at line 44 of file dt_constants.hh.

◆ mask

Bitfield< 11, 3 > MipsISA::mask

Definition at line 72 of file pra_constants.hh.

Referenced by MipsISA::ISA::configCP().

◆ maskx

Bitfield<12, 11> MipsISA::maskx

Definition at line 73 of file pra_constants.hh.

◆ MaxShadowRegSets

const int MipsISA::MaxShadowRegSets = 16

Definition at line 56 of file registers.hh.

◆ mcheckep

Bitfield<23> MipsISA::mcheckep

Definition at line 49 of file dt_constants.hh.

◆ md

Bitfield<5> MipsISA::md

Definition at line 241 of file pra_constants.hh.

◆ MIPS32_QNAN

const uint32_t MipsISA::MIPS32_QNAN = 0x7fbfffff

Definition at line 65 of file registers.hh.

◆ MIPS64_QNAN

const uint64_t MipsISA::MIPS64_QNAN = ULL(0x7ff7ffffffffffff)

Definition at line 66 of file registers.hh.

◆ mmuSize

Bitfield<30, 25> MipsISA::mmuSize

Definition at line 233 of file pra_constants.hh.

◆ mode

Bitfield<11, 7> MipsISA::mode

Definition at line 97 of file dt_constants.hh.

Referenced by MipsISA::TLB::demapPage().

◆ mt

Bitfield< 2 > MipsISA::mt

Definition at line 225 of file pra_constants.hh.

◆ mvp

Bitfield<1> MipsISA::mvp

Definition at line 73 of file mt_constants.hh.

◆ mx

Bitfield<24> MipsISA::mx

Definition at line 114 of file pra_constants.hh.

◆ nmi

Bitfield<19> MipsISA::nmi

Definition at line 119 of file pra_constants.hh.

◆ nodcr

Bitfield<29> MipsISA::nodcr

Definition at line 43 of file dt_constants.hh.

◆ nosst

Bitfield<9> MipsISA::nosst

Definition at line 61 of file dt_constants.hh.

◆ NPtePage

const Addr MipsISA::NPtePage = ULL(1) << NPtePageShift

Definition at line 61 of file isa_traits.hh.

◆ NPtePageShift

const Addr MipsISA::NPtePageShift = PageShift - PteShift

Definition at line 60 of file isa_traits.hh.

◆ NumCCRegs

const int MipsISA::NumCCRegs = 0

Definition at line 63 of file registers.hh.

Referenced by copyRegs().

◆ NumFloatArchRegs

const int MipsISA::NumFloatArchRegs = 32

Definition at line 53 of file registers.hh.

◆ NumFloatRegs

const int MipsISA::NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs

Definition at line 58 of file registers.hh.

Referenced by copyRegs().

◆ NumFloatSpecialRegs

const int MipsISA::NumFloatSpecialRegs = 5

Definition at line 54 of file registers.hh.

◆ NumIntArchRegs

const int MipsISA::NumIntArchRegs = 32

Definition at line 51 of file registers.hh.

◆ NumIntRegs

const int MipsISA::NumIntRegs = NumIntArchRegs + NumIntSpecialRegs

Definition at line 57 of file registers.hh.

Referenced by copyRegs().

◆ NumIntSpecialRegs

const int MipsISA::NumIntSpecialRegs = 9

Definition at line 52 of file registers.hh.

◆ NumMiscRegs

const int MipsISA::NumMiscRegs = MISCREG_NUMREGS

Definition at line 282 of file registers.hh.

Referenced by MipsISA::ISA::clear(), copyRegs(), and MipsISA::ISA::ISA().

◆ NumVecElemPerVecReg

constexpr unsigned MipsISA::NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg

Definition at line 291 of file registers.hh.

◆ NumVecPredRegs

const int MipsISA::NumVecPredRegs = 1

Definition at line 61 of file registers.hh.

◆ NumVecRegs

const int MipsISA::NumVecRegs = 1

Definition at line 59 of file registers.hh.

◆ offline

Bitfield<7> MipsISA::offline

Definition at line 63 of file dt_constants.hh.

◆ on

Bitfield<0> MipsISA::on

Definition at line 89 of file dt_constants.hh.

Referenced by sc_gem5::Scheduler::deschedule(), and sc_gem5::TraceFile::traceDeltas().

◆ p

Bitfield<0> MipsISA::p

Definition at line 325 of file pra_constants.hh.

Referenced by _llseekFunc(), acceptFunc(), accessFunc(), sc_core::sc_join::add_process(), sc_gem5::SensitivityEvents::addEvent(), ProbeManager::addListener(), ProbeManager::addPoint(), DRAMCtrl::addToReadQueue(), archPrctlFunc(), ArmSemihosting::ArmSemihosting(), ArmISA::ISA::assert64(), atomic_read(), atomic_write(), AtomicSimpleCPU::AtomicSimpleCPU(), SignaturePathPrefetcherV2::auxiliaryPrefetcher(), BaseCache::BaseCache(), BaseCPU::BaseCPU(), BaseTrafficGen::BaseTrafficGen(), EtherInt::bind(), sc_core::sc_in< sc_dt::sc_lv< W > >::bind(), sc_core::sc_in< bool >::bind(), sc_core::sc_in< sc_dt::sc_logic >::bind(), bindFunc(), BOPPrefetcher::BOPPrefetcher(), brkFunc(), tlm::circular_buffer< T >::buf_clear(), tlm::circular_buffer< T >::buf_read(), tlm::circular_buffer< T >::buf_write(), MultiSocketSimpleSwitchAT::bwPEQcb(), chdirFunc(), PacketQueue::checkConflict(), sc_gem5::WriteChecker< sc_core::SC_ONE_WRITER >::checkWriter(), sc_gem5::WriteChecker< sc_core::SC_MANY_WRITERS >::checkWriter(), chownFunc(), sc_gem5::Scheduler::clear(), ArmISA::ISA::clear(), cloneFunc(), closeFunc(), BaseRemoteGDB::cmd_async_cont(), BaseRemoteGDB::cmd_async_step(), BaseRemoteGDB::cmd_clr_hw_bkpt(), BaseRemoteGDB::cmd_cont(), BaseRemoteGDB::cmd_mem_r(), BaseRemoteGDB::cmd_mem_w(), BaseRemoteGDB::cmd_reg_w(), BaseRemoteGDB::cmd_set_hw_bkpt(), BaseRemoteGDB::cmd_set_thread(), BaseRemoteGDB::cmd_step(), connectFunc(), VirtIO9PSocket::connectSocket(), sc_dt::convert_to_bin(), FrameBuffer::copyIn(), FrameBuffer::copyOut(), GenericTimer::createTimers(), sc_gem5::Scheduler::current(), Linux::ThreadInfo::curThreadInfo(), CustomNoMaliGpu::CustomNoMaliGpu(), Packet::dataStaticConst(), sc_gem5::DefaultReportMessages::DefaultReportMessages(), Sinic::Device::Device(), sc_gem5::Process::disable(), DRAMCtrl::doDRAMAccess(), doGzipLoad(), sc_core::sc_module::dont_initialize(), DRAMCtrl::DRAMCtrl(), dup2Func(), dupFunc(), sc_gem5::Process::enable(), sc_core::sc_in< sc_dt::sc_int< W > >::end_of_elaboration(), sc_core::sc_in< sc_dt::sc_uint< W > >::end_of_elaboration(), sc_core::sc_in< sc_dt::sc_biguint< W > >::end_of_elaboration(), sc_core::sc_in< sc_dt::sc_bigint< W > >::end_of_elaboration(), sc_core::sc_inout< sc_dt::sc_int< W > >::end_of_elaboration(), sc_core::sc_inout< sc_dt::sc_uint< W > >::end_of_elaboration(), sc_core::sc_inout< sc_dt::sc_biguint< W > >::end_of_elaboration(), sc_core::sc_inout< sc_dt::sc_bigint< W > >::end_of_elaboration(), EnergyCtrl::EnergyCtrl(), EtherBus::EtherBus(), eventfdFunc(), execveFunc(), exitImpl(), fallocateFunc(), fchmodFunc(), fchownFunc(), fcntl64Func(), fcntlFunc(), FrameBuffer::fill(), VGic::findHighestPendingLR(), AlphaISA::ISA::flattenMiscIndex(), CoherentXBar::forwardAtomic(), CoherentXBar::forwardFunctional(), CoherentXBar::forwardTiming(), sc_dt::scfx_rep::from_string(), PixelConverter::fromPixel(), fstat64Func(), fstatfsFunc(), fstatFunc(), ftruncate64Func(), ftruncateFunc(), GarnetSyntheticTraffic::GarnetSyntheticTraffic(), GenericTimerMem::GenericTimerMem(), ArmPPIGen::get(), sc_core::sc_simcontext::get_curr_proc_info(), getcwdFunc(), FastModel::CortexA76Cluster::getEvs(), LoopPredictor::getLoopUseCounter(), sc_gem5::Scheduler::getNextReady(), IGbE::TxDescCache::getPacketData(), getpeernameFunc(), SparcISA::getresuidFunc(), SimpleIndirectPredictor::getSetIndex(), getsocknameFunc(), getsockoptFunc(), GicV2::GicV2(), GPUCoalescer::GPUCoalescer(), SignaturePathPrefetcher::handlePageCrossingLookahead(), HDLcd::HDLcd(), CPA::hwWe(), IdeDisk::IdeDisk(), IGbE::IGbE(), sc_core::sc_vector_base::implicitCast(), sc_gem5::Kernel::init(), CpuLocalTimer::init(), CoherentXBar::init(), sc_core::sc_vector< svp_gicv3_comms::gicv3_comms_target_socket<> >::init(), ListOperand::init(), FunctionRefOperand::init(), MultiperspectivePerceptron::init(), BaseRegOperand::init_from_vect(), ImmOperand< SrcCType >::init_from_vect(), sc_gem5::Scheduler::initPhase(), ArmSystem::initState(), GenericPageTableFault::invoke(), AlphaISA::NDtbMissFault::invoke(), SparcISA::FastInstructionAccessMMUMiss::invoke(), SparcISA::FastDataAccessMMUMiss::invoke(), SparcISA::SpillNNormal::invoke(), AlphaISA::ItbPageFault::invoke(), SparcISA::FillNNormal::invoke(), SparcISA::TrapInstruction::invoke(), ioctlFunc(), sc_gem5::Process::kill(), linkFunc(), listenFunc(), lseekFunc(), SnoopFilter::maskToPortList(), MemTest::MemTest(), DRAMCtrl::minBankPrep(), mkdirFunc(), mknodFunc(), mmapFunc(), EtherInt::name(), tlm_utils::callback_binder_bw< tlm::tlm_base_protocol_types >::nb_transport_bw(), tlm_utils::callback_binder_fw< tlm::tlm_base_protocol_types >::nb_transport_fw(), sc_gem5::newCThreadProcess(), sc_gem5::newMethodProcess(), sc_gem5::newThreadProcess(), sc_core::next_trigger(), TrafficGen::nextState(), NoMaliGpu::NoMaliGpu(), RawDiskImage::notifyFork(), NSGigE::NSGigE(), ClDriver::open(), openatFunc(), sc_dt::sc_logic::operator new(), Net::EthPtr::operator!(), Net::IpPtr::operator!(), Net::Ip6Ptr::operator!(), Net::TcpPtr::operator!(), Net::UdpPtr::operator!(), TypedAtomicOpFunctor< T >::operator()(), sc_core::sc_in< sc_dt::sc_lv< W > >::operator()(), sc_core::sc_module::operator()(), sc_core::sc_in< bool >::operator()(), sc_core::sc_in< sc_dt::sc_logic >::operator()(), sc_core::sc_sensitive::operator<<(), sc_core::sc_out_resolved::operator=(), sc_core::sc_inout_resolved::operator=(), sc_core::sc_out_rv< W >::operator=(), sc_core::sc_inout_rv< W >::operator=(), VPtr< T >::operator=(), sc_core::sc_inout< sc_dt::sc_lv< W > >::operator=(), sc_core::sc_process_handle::operator=(), RefCountingPtr< MinorDynInst >::operator=(), sc_core::sc_inout< bool >::operator=(), sc_core::sc_inout< sc_dt::sc_logic >::operator=(), sc_gem5::VcdTraceScope::output(), Net::EthPtr::packet(), Net::IpPtr::packet(), Net::Ip6Ptr::packet(), Net::TcpPtr::packet(), Net::UdpPtr::packet(), BadDevice::params(), AmbaFake::params(), IsaFake::params(), RealView::params(), Sinic::Base::params(), MaltaCChip::params(), Uart8250::params(), Root::params(), PL031::params(), MaltaIO::params(), Gicv3::params(), Sp804::params(), IdeController::params(), A9GlobalTimer::params(), ArmSystem::params(), RealViewCtrl::params(), CpuLocalTimer::params(), VGic::params(), Pl111::params(), GicV2::params(), MathExpr::parse(), WriteMask::performAtomic(), sc_gem5::pickParentObj(), pipeImpl(), Pl011::Pl011(), Pl111::Pl111(), pollFunc(), Printk(), AnnotateDumpCallback::process(), Trace::TarmacParserRecord::TarmacParserRecordEvent::process(), BrigObject::processDirectives(), MemBackdoor::ptr(), pwrite64Func(), ClockedObject::pwrState(), PortProxy::readBlobPhys(), DRAMSim2::readComplete(), PseudoInst::readfile(), readFunc(), readlinkFunc(), readvFunc(), NoncoherentCache::recvAtomicSnoop(), recvfromFunc(), NoncoherentXBar::recvFunctional(), SimpleMemory::recvFunctional(), CoherentXBar::recvFunctional(), CoherentXBar::recvFunctionalSnoop(), recvmsgFunc(), BaseXBar::recvRangeChange(), NoncoherentXBar::NoncoherentXBarMasterPort::recvReqRetry(), sc_core::sc_report::register_id(), BaseMemProbe::regProbeListeners(), sc_gem5::Kernel::regStats(), StackDistProbe::regStats(), ClockedObject::ClockedObjectStats::regStats(), sc_core::sc_mempool::release(), ProbeManager::removeListener(), renameFunc(), sc_gem5::Process::reset(), sc_dt::scfx_mant::resize_to(), sc_gem5::Process::resume(), rmdirFunc(), Root::Root(), RubyPort::ruby_eviction_callback(), RubyDirectedTester::RubyDirectedTester(), RubyTester::RubyTester(), sc_core::sc_event_finder_t< sc_core::sc_signal_inout_if< bool > >::sc_event_finder_t(), sc_core::sc_gen_unique_name(), sc_core::sc_spawn(), sc_core::sc_start(), selectFunc(), BaseRemoteGDB::send(), sendmsgFunc(), EtherTapStub::sendReal(), ComputeUnit::sendRequest(), sendtoFunc(), Sequencer::Sequencer(), SymbolTable::serialize(), tlm_utils::passthrough_target_socket_b< MODULE, BUSWIDTH, TYPES, POL >::process::set_b_transport_ptr(), tlm_utils::simple_target_socket_b< MODULE, BUSWIDTH, TYPES, POL >::fw_process::set_b_transport_ptr(), tlm_utils::passthrough_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >::process::set_b_transport_ptr(), tlm_utils::simple_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >::fw_process::set_b_transport_ptr(), tlm::tlm_dmi::set_dmi_ptr(), tlm_utils::passthrough_target_socket_b< MODULE, BUSWIDTH, TYPES, POL >::process::set_get_direct_mem_ptr(), tlm_utils::simple_target_socket_b< MODULE, BUSWIDTH, TYPES, POL >::fw_process::set_get_direct_mem_ptr(), tlm_utils::passthrough_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >::process::set_get_direct_mem_ptr(), tlm_utils::simple_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >::fw_process::set_get_direct_mem_ptr(), tlm_utils::simple_initiator_socket_b< MODULE, BUSWIDTH, TYPES, POL >::process::set_invalidate_direct_mem_ptr(), tlm_utils::simple_initiator_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >::process::set_invalidate_direct_mem_ptr(), tlm_utils::passthrough_target_socket_b< MODULE, BUSWIDTH, TYPES, POL >::process::set_nb_transport_ptr(), tlm_utils::simple_target_socket_b< MODULE, BUSWIDTH, TYPES, POL >::fw_process::set_nb_transport_ptr(), tlm_utils::passthrough_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >::process::set_nb_transport_ptr(), tlm_utils::simple_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >::fw_process::set_nb_transport_ptr(), tlm_utils::passthrough_target_socket_b< MODULE, BUSWIDTH, TYPES, POL >::process::set_transport_dbg_ptr(), tlm_utils::simple_target_socket_b< MODULE, BUSWIDTH, TYPES, POL >::fw_process::set_transport_dbg_ptr(), tlm_utils::passthrough_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >::process::set_transport_dbg_ptr(), tlm_utils::simple_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >::fw_process::set_transport_dbg_ptr(), tlm_utils::simple_initiator_socket_b< MODULE, BUSWIDTH, TYPES, POL >::process::set_transport_ptr(), tlm_utils::simple_initiator_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >::process::set_transport_ptr(), SETranslatingPortProxy::setPageTable(), EtherInt::setPeer(), SETranslatingPortProxy::setProcess(), ThreadState::setProcessPtr(), SnoopFilter::setSlavePorts(), setsockoptFunc(), CheckerCPU::setSystem(), Shader::Shader(), shutdownFunc(), socketFunc(), socketpairFunc(), DRAMCtrl::sortTime(), sc_gem5::spawnWork(), VirtIO9PDiod::startDiod(), sc_gem5::Kernel::startup(), BaseKvmCPU::startup(), MathExprPowerModel::startup(), MipsISA::ISA::startup(), PowerISA::ISA::startup(), BaseKvmCPU::startupThread(), DmaReadFifo::stopFill(), sc_gem5::Kernel::stopWork(), sc_gem5::Process::suspend(), symlinkFunc(), sc_gem5::Process::syncResetOff(), sc_gem5::Process::syncResetOn(), ArmISA::TableWalker::TableWalker(), ThermalModel::ThermalModel(), sc_gem5::ExceptionWrapper< T >::throw_it(), sc_gem5::Process::throw_it(), sc_core::timed_out(), timeFunc(), TLBCoalescer::TLBCoalescer(), MipsISA::TLB::translateData(), PowerISA::TLB::translateData(), MipsISA::TLB::translateInst(), PowerISA::TLB::translateInst(), ArmISA::TLB::translateSe(), truncateFunc(), Process::tryLoaders(), SETranslatingPortProxy::tryReadBlob(), FSTranslatingPortProxy::tryReadBlob(), SETranslatingPortProxy::tryWriteBlob(), FSTranslatingPortProxy::tryWriteBlob(), UFSHostDevice::UFSHostDevice(), unlinkFunc(), sc_dt::sc_global< T >::update(), TLBCoalescer::updatePhysAddresses(), Stats::validateStatName(), sc_core::sc_port_b< tlm_nonblocking_put_if< T > >::vbind(), sc_core::wait(), wait4Func(), System::workItemBegin(), System::workItemEnd(), sc_core::sc_signal_resolved::write(), sc_core::sc_signal_rv< W >::write(), PortProxy::writeBlobPhys(), DRAMSim2::writeComplete(), writeFunc(), writevFunc(), MPP_StatisticalCorrector::BranchInfo::~BranchInfo(), CoherentXBar::~CoherentXBar(), DmaReadFifo::~DmaReadFifo(), FSTranslatingPortProxy::~FSTranslatingPortProxy(), MultiperspectivePerceptronTAGE::MPPTAGEBranchInfo::~MPPTAGEBranchInfo(), PortProxy::~PortProxy(), QueuedPrefetcher::~QueuedPrefetcher(), StreamGen::~StreamGen(), and ThreadContext::~ThreadContext().

◆ PABits

const unsigned MipsISA::PABits = 32

Definition at line 97 of file isa_traits.hh.

◆ paco

Bitfield<0> MipsISA::paco

Definition at line 132 of file dt_constants.hh.

◆ PAddrImplMask

const Addr MipsISA::PAddrImplMask = (ULL(1) << PABits) - 1

Definition at line 104 of file isa_traits.hh.

◆ Page_Mask

const Addr MipsISA::Page_Mask = ~(PageBytes - 1)

Definition at line 50 of file isa_traits.hh.

◆ PageBytes

const Addr MipsISA::PageBytes = ULL(1) << PageShift

Definition at line 49 of file isa_traits.hh.

Referenced by MipsProcess::argsInit(), RoundPage(), and TruncPage().

◆ PageOffset

const Addr MipsISA::PageOffset = PageBytes - 1

Definition at line 51 of file isa_traits.hh.

Referenced by VAddrOffset().

◆ PageShift

const Addr MipsISA::PageShift = 13

Definition at line 48 of file isa_traits.hh.

Referenced by VAddrVPN().

◆ pc

Bitfield<4> MipsISA::pc

Definition at line 242 of file pra_constants.hh.

Referenced by GenericISA::M5DebugFault::advancePC(), ArmISA::ArmStaticInst::advancePC(), ArmProcess::argsInit(), MPP_TAGE::bindex(), SparcISA::BlockMemImmMicro::BlockMemImmMicro(), SparcISA::BlockMemMicro::BlockMemMicro(), SparcISA::BranchDisp::BranchDisp(), ArmISA::BranchEret64::BranchEret64(), ArmISA::BranchEretA64::BranchEretA64(), ArmISA::BranchImm::BranchImm(), SparcISA::BranchImm13::BranchImm13(), ArmISA::BranchImm64::BranchImm64(), ArmISA::BranchImmCond64::BranchImmCond64(), ArmISA::BranchImmImmReg64::BranchImmImmReg64(), ArmISA::BranchImmReg64::BranchImmReg64(), LoopPredictor::BranchInfo::BranchInfo(), GenericISA::SimplePCState< MachInst >::branching(), GenericISA::UPCState< MachInst >::branching(), GenericISA::DelaySlotPCState< MachInst >::branching(), PowerISA::BranchNonPCRel::BranchNonPCRel(), PowerISA::BranchNonPCRelCond::BranchNonPCRelCond(), PowerISA::BranchPCRel::BranchPCRel(), PowerISA::BranchPCRelCond::BranchPCRelCond(), ArmISA::BranchReg::BranchReg(), ArmISA::BranchReg64::BranchReg64(), PowerISA::BranchRegCond::BranchRegCond(), ArmISA::BranchRegReg::BranchRegReg(), ArmISA::BranchRegReg64::BranchRegReg64(), ArmISA::BranchRet64::BranchRet64(), ArmISA::BranchRetA64::BranchRetA64(), Iris::ThreadContext::breakpointHit(), DeltaCorrelatingPredictionTables::calculatePrefetch(), IrregularStreamBufferPrefetcher::calculatePrefetch(), StridePrefetcher::calculatePrefetch(), STeMSPrefetcher::calculatePrefetch(), IndirectMemoryPrefetcher::calculatePrefetch(), Trace::SparcNativeTrace::check(), Check::Check(), BaseSimpleCPU::checkPcEventQueue(), StaticInst::completeAcc(), PowerISA::CondLogicOp::CondLogicOp(), PowerISA::CondMoveOp::CondMoveOp(), ArmISA::DataImmOp::DataImmOp(), ArmISA::DataRegOp::DataRegOp(), ArmISA::DataRegRegOp::DataRegRegOp(), ArmISA::DataX1Reg2ImmOp::DataX1Reg2ImmOp(), ArmISA::DataX1RegImmOp::DataX1RegImmOp(), ArmISA::DataX1RegOp::DataX1RegOp(), ArmISA::DataX2RegImmOp::DataX2RegImmOp(), ArmISA::DataX2RegOp::DataX2RegOp(), ArmISA::DataX3RegOp::DataX3RegOp(), ArmISA::DataXCondCompImmOp::DataXCondCompImmOp(), ArmISA::DataXCondCompRegOp::DataXCondCompRegOp(), ArmISA::DataXCondSelOp::DataXCondSelOp(), ArmISA::DataXERegOp::DataXERegOp(), ArmISA::DataXImmOnlyOp::DataXImmOnlyOp(), ArmISA::DataXImmOp::DataXImmOp(), ArmISA::DataXSRegOp::DataXSRegOp(), MipsISA::StackTrace::decodePrologue(), AlphaISA::StackTrace::decodePrologue(), PowerISA::PCDependentDisassembly::disassemble(), SparcISA::doNormalFault(), SparcISA::doREDFault(), Trace::IntelTraceRecord::dump(), FunctionProfile::dump(), ArmKvmCPU::dumpKvmStateCore(), ArmISA::EndBitUnion(), PCEventQueue::equal_range(), DecoderFaultInst::execute(), ArmISA::PredMacroOp::execute(), ArmISA::RfeOp::fetchMicroop(), ArmISA::SrsOp::fetchMicroop(), ArmISA::FpCondCompRegOp::FpCondCompRegOp(), ArmISA::FpCondSelOp::FpCondSelOp(), ArmISA::FpRegImmOp::FpRegImmOp(), ArmISA::FpRegRegImmOp::FpRegRegImmOp(), ArmISA::FpRegRegOp::FpRegRegOp(), ArmISA::FpRegRegRegCondOp::FpRegRegRegCondOp(), ArmISA::FpRegRegRegImmOp::FpRegRegRegImmOp(), ArmISA::FpRegRegRegOp::FpRegRegRegOp(), ArmISA::FpRegRegRegRegOp::FpRegRegRegRegOp(), SparcISA::BranchDisp::generateDisassembly(), GPUCoalescer::getFirstResponseToCompletionDelayHist(), BasePrefetcher::PrefetchInfo::getPC(), SparcISA::RemoteGDB::SPARCGdbRegCache::getRegs(), SparcISA::RemoteGDB::SPARC64GdbRegCache::getRegs(), TAGE_SC_L_TAGE::gindex(), MPP_StatisticalCorrector_8KB::gPredictions(), MPP_StatisticalCorrector_64KB::gPredictions(), haltThread(), SparcProcess::handleTrap(), ImmOp64::ImmOp64(), TimingSimpleCPU::initiateMemAMO(), TimingSimpleCPU::initiateMemRead(), RiscvProcess32::initState(), PowerISA::PowerStaticInst::insertCRField(), Iris::ThreadContext::installBp(), ArmISA::Decoder::instReady(), PowerISA::IntImmOp::IntImmOp(), PowerISA::IntShiftOp::IntShiftOp(), AlphaISA::AlphaFault::invoke(), SparcISA::SparcFaultBase::invoke(), SparcISA::PowerOnReset::invoke(), ArmISA::ArmFault::invoke(), AlphaISA::ItbFault::invoke(), AlphaISA::ItbPageFault::invoke(), SparcISA::TrapInstruction::invoke(), ArmISA::Reset::invoke(), ArmISA::SupervisorCall::invoke(), ArmISA::ArmFault::invoke64(), Sequencer::issueRequest(), GPUCoalescer::issueRequest(), LoopPredictor::lindex(), PowerISA::IntOp::makeCRField(), PowerISA::FloatOp::makeCRField(), PowerISA::MemDispOp::MemDispOp(), SparcISA::MemImm::MemImm(), PowerISA::MemOp::MemOp(), ArmISA::MemoryDImm64::MemoryDImm64(), ArmISA::MemoryDImmEx64::MemoryDImmEx64(), ArmISA::MemoryEx64::MemoryEx64(), ArmISA::MemoryImm64::MemoryImm64(), ArmISA::MemoryLiteral64::MemoryLiteral64(), ArmISA::MemoryPostIndex64::MemoryPostIndex64(), ArmISA::MemoryPreIndex64::MemoryPreIndex64(), ArmISA::MemoryRaw64::MemoryRaw64(), ArmISA::MemoryReg64::MemoryReg64(), ArmISA::MicroIntImmOp::MicroIntImmOp(), ArmISA::MicroIntImmXOp::MicroIntImmXOp(), ArmISA::MicroIntMov::MicroIntMov(), ArmISA::MicroIntOp::MicroIntOp(), ArmISA::MicroIntRegXOp::MicroIntRegXOp(), ArmISA::MicroMemOp::MicroMemOp(), ArmISA::MicroMemPairOp::MicroMemPairOp(), ArmISA::MicroSetPCCPSR::MicroSetPCCPSR(), MiscRegImmOp64::MiscRegImmOp64(), MiscRegImplDefined64::MiscRegImplDefined64(), MiscRegRegImmOp64::MiscRegRegImmOp64(), TraceCPU::FixedRetryGen::name(), GenericISA::operator<<(), PowerISA::PCDependentDisassembly::PCDependentDisassembly(), Iris::ThreadContext::pcState(), BaseSimpleCPU::postExecute(), BPredUnit::predict(), ArmISA::PredImmOp::PredImmOp(), ArmISA::PredIntOp::PredIntOp(), PIFPrefetcher::PrefetchListenerPC::PrefetchListenerPC(), Trace::TarmacParserRecord::TarmacParserRecordEvent::process(), HardBreakpoint::process(), ArmISA::ISA::readMiscReg(), RegMiscRegImmOp64::RegMiscRegImmOp64(), RegRegImmImmOp64::RegRegImmImmOp64(), RegRegRegImmOp64::RegRegRegImmOp64(), PowerISA::IntRotateOp::rotateValue(), FunctionProfile::sample(), GenericISA::SimplePCState< MachInst >::set(), MipsISA::MipsFaultBase::setExceptionState(), SparcISA::SetHi::SetHi(), ArmISA::ISA::setMiscReg(), Request::setPC(), SparcISA::RemoteGDB::SPARCGdbRegCache::setRegs(), SparcISA::RemoteGDB::SPARC64GdbRegCache::setRegs(), Request::setVirt(), SouthBridge::SouthBridge(), DefaultIEW< Impl >::squashDueToBranch(), ArmISA::SveAdrOp::SveAdrOp(), ArmISA::SveBinConstrPredOp::SveBinConstrPredOp(), ArmISA::SveBinDestrPredOp::SveBinDestrPredOp(), ArmISA::SveBinIdxUnpredOp::SveBinIdxUnpredOp(), ArmISA::SveBinImmIdxUnpredOp::SveBinImmIdxUnpredOp(), ArmISA::SveBinImmPredOp::SveBinImmPredOp(), ArmISA::SveBinImmUnpredConstrOp::SveBinImmUnpredConstrOp(), ArmISA::SveBinImmUnpredDestrOp::SveBinImmUnpredDestrOp(), ArmISA::SveBinUnpredOp::SveBinUnpredOp(), ArmISA::SveBinWideImmUnpredOp::SveBinWideImmUnpredOp(), ArmISA::SveCmpImmOp::SveCmpImmOp(), ArmISA::SveCmpOp::SveCmpOp(), ArmISA::SveComplexIdxOp::SveComplexIdxOp(), ArmISA::SveComplexOp::SveComplexOp(), ArmISA::SveCompTermOp::SveCompTermOp(), ArmISA::SveContigMemSI::SveContigMemSI(), ArmISA::SveContigMemSS::SveContigMemSS(), ArmISA::SveDotProdIdxOp::SveDotProdIdxOp(), ArmISA::SveDotProdOp::SveDotProdOp(), ArmISA::SveElemCountOp::SveElemCountOp(), ArmISA::SveIndexIIOp::SveIndexIIOp(), ArmISA::SveIndexIROp::SveIndexIROp(), ArmISA::SveIndexRIOp::SveIndexRIOp(), ArmISA::SveIndexRROp::SveIndexRROp(), ArmISA::SveIntCmpImmOp::SveIntCmpImmOp(), ArmISA::SveIntCmpOp::SveIntCmpOp(), ArmISA::SveMemPredFillSpill::SveMemPredFillSpill(), ArmISA::SveMemVecFillSpill::SveMemVecFillSpill(), ArmISA::SveOrdReducOp::SveOrdReducOp(), ArmISA::SvePartBrkOp::SvePartBrkOp(), ArmISA::SvePartBrkPropOp::SvePartBrkPropOp(), ArmISA::SvePredBinPermOp::SvePredBinPermOp(), ArmISA::SvePredCountOp::SvePredCountOp(), ArmISA::SvePredCountPredOp::SvePredCountPredOp(), ArmISA::SvePredLogicalOp::SvePredLogicalOp(), ArmISA::SvePredTestOp::SvePredTestOp(), ArmISA::SvePredUnaryWImplicitDstOp::SvePredUnaryWImplicitDstOp(), ArmISA::SvePredUnaryWImplicitSrcOp::SvePredUnaryWImplicitSrcOp(), ArmISA::SvePredUnaryWImplicitSrcPredOp::SvePredUnaryWImplicitSrcPredOp(), ArmISA::SvePtrueOp::SvePtrueOp(), ArmISA::SveReducOp::SveReducOp(), ArmISA::SveSelectOp::SveSelectOp(), ArmISA::SveTblOp::SveTblOp(), ArmISA::SveTerImmUnpredOp::SveTerImmUnpredOp(), ArmISA::SveTerPredOp::SveTerPredOp(), ArmISA::SveUnaryPredOp::SveUnaryPredOp(), ArmISA::SveUnaryPredPredOp::SveUnaryPredPredOp(), ArmISA::SveUnarySca2VecUnpredOp::SveUnarySca2VecUnpredOp(), ArmISA::SveUnaryUnpredOp::SveUnaryUnpredOp(), ArmISA::SveUnaryWideImmPredOp::SveUnaryWideImmPredOp(), ArmISA::SveUnaryWideImmUnpredOp::SveUnaryWideImmUnpredOp(), ArmISA::SveUnpackOp::SveUnpackOp(), ArmISA::SveWhileOp::SveWhileOp(), ArmISA::SveWImplicitSrcDstOp::SveWImplicitSrcDstOp(), FullO3CPU< O3CPUImpl >::switchRenameMode(), ArmISA::SysDC64::SysDC64(), TAGE_SC_L_TAGE::TAGE_SC_L_TAGE(), TAGE_SC_L_TAGE_64KB::TAGE_SC_L_TAGE_64KB(), TAGE_SC_L_TAGE_8KB::TAGE_SC_L_TAGE_8KB(), TAGEBase::tagePredict(), AlphaISA::StackTrace::trace(), BaseCPU::traceFunctionsInternal(), Trace::ExeTracerRecord::traceInst(), SparcISA::Trap::Trap(), UnknownOp64::UnknownOp64(), BaseCPU::unserializeThread(), BPredUnit::update(), MultiperspectivePerceptronTAGE::updateHistories(), ArmKvmCPU::updateTCStateCore(), ArmV8KvmCPU::updateThreadContext(), TimingSimpleCPU::writeMem(), SparcISA::WrPrivImm::WrPrivImm(), TAGEBase::BranchInfo::~BranchInfo(), MultiperspectivePerceptronTAGE::MPPTAGEBranchInfo::~MPPTAGEBranchInfo(), and SparcISA::SparcMacroInst::~SparcMacroInst().

◆ pci

Bitfield<26> MipsISA::pci

Definition at line 181 of file pra_constants.hh.

◆ pcp

Bitfield<27> MipsISA::pcp

Definition at line 52 of file mt_constants.hh.

◆ pfn

Bitfield<29, 6> MipsISA::pfn

Definition at line 57 of file pra_constants.hh.

Referenced by ArmISA::TLB::insert().

◆ procId

Bitfield<15, 8> MipsISA::procId

Definition at line 205 of file pra_constants.hh.

Referenced by MipsISA::ISA::configCP().

◆ pss

Bitfield<9, 6> MipsISA::pss

Definition at line 160 of file pra_constants.hh.

◆ pState

Bitfield<7, 6> MipsISA::pState

Definition at line 321 of file pra_constants.hh.

◆ pTagLo

MipsISA::pTagLo

Definition at line 320 of file pra_constants.hh.

◆ ptc

Bitfield<7, 0> MipsISA::ptc

Definition at line 56 of file mt_constants.hh.

◆ pteBase

MipsISA::pteBase

Definition at line 65 of file pra_constants.hh.

◆ PteMask

const Addr MipsISA::PteMask = NPtePage - 1

Definition at line 62 of file isa_traits.hh.

◆ PteShift

const Addr MipsISA::PteShift = 3

Definition at line 59 of file isa_traits.hh.

◆ ptlbe

Bitfield<25, 16> MipsISA::ptlbe

Definition at line 53 of file mt_constants.hh.

◆ pvpe

Bitfield<13, 10> MipsISA::pvpe

Definition at line 55 of file mt_constants.hh.

◆ px

Bitfield<23> MipsISA::px

Definition at line 115 of file pra_constants.hh.

Referenced by sc_dt::sc_proxy< sc_subref_r< X > >::print().

◆ r

Bitfield< 1 > MipsISA::r

Definition at line 97 of file pra_constants.hh.

Referenced by __to_number(), sc_gem5::ScSignalBaseBinary::_signalReset(), AddrRange::AddrRange(), DRAMCtrl::allRanksDrained(), Set::AND(), bitrev(), BPredUnit::BPredUnit(), LSQ< Impl >::SplitDataRequest::buildPackets(), sc_dt::sc_unsigned::check_range(), sc_dt::sc_signed::check_range(), ArmISA::TLB::checkPermissions64(), ArmISA::decodeMrsMsrBankedReg(), DirectoryMemory::DirectoryMemory(), doGzipLoad(), DRAMCtrl::drain(), DRAMCtrl::drainResume(), SimpleATTarget1::endRequest(), SimpleATInitiator1::endResponse(), sc_gem5::Port::finalize(), Stats::Formula::Formula(), ArmISA::fp64_sqrt(), sc_dt::sc_concref_r< X, Y >::get_cword(), sc_dt::sc_concref_r< X, Y >::get_word(), RubyPort::PioSlavePort::getAddrRanges(), sc_gem5::Gem5ToTlmBridge< BITWIDTH >::getBackdoor(), PhysicalMemory::getConfAddrRanges(), sc_gem5::getCurrentProcess(), ArmISA::getExecutingAsid(), Sequencer::getHitTypeMachLatencyHist(), Sequencer::getMissTypeMachLatencyHist(), GPUCoalescer::getMissTypeMachLatencyHist(), AlphaISA::RemoteGDB::AlphaGdbRegCache::getRegs(), PowerISA::RemoteGDB::PowerGdbRegCache::getRegs(), SparcISA::RemoteGDB::SPARCGdbRegCache::getRegs(), MipsISA::RemoteGDB::MipsGdbRegCache::getRegs(), ArmISA::RemoteGDB::AArch32GdbRegCache::getRegs(), SparcISA::RemoteGDB::SPARC64GdbRegCache::getRegs(), ArmISA::RemoteGDB::AArch64GdbRegCache::getRegs(), LSQ< Impl >::SplitDataRequest::handleIprRead(), LSQ< Impl >::SplitDataRequest::handleIprWrite(), LSQ< Impl >::SplitDataRequest::initiateTranslation(), BaseCache::inRange(), GPUCoalescer::insertRequest(), Set::intersectionIsEmpty(), sc_gem5::Gem5ToTlmBridge< BITWIDTH >::invalidate_direct_mem_ptr(), QTIsaac< ALPHA >::isaac(), LSQ< Impl >::SplitDataRequest::isCacheBlockHit(), DirectoryMemory::isPresent(), Set::isSuperset(), lookupTraceForAddress(), sc_gem5::ScMainFiber::main(), DirectoryMemory::mapAddressToLocalIdx(), operator!=(), AddrRange::operator!=(), operator+(), operator-(), sc_dt::operator<<(), RefCountingPtr< MinorDynInst >::operator=(), Stats::Formula::operator=(), rgb_t::operator==(), operator==(), operator>(), Set::OR(), MathExpr::parse(), PersistentTable::persistentRequestLock(), tlm::tlm_endian_context_pool::pop(), HardBreakpoint::process(), DRAMCtrl::processNextReqEvent(), QTIsaac< ALPHA >::randinit(), MemBackdoor::range(), ArmISA::recipEstimate(), ArmISA::recipSqrtEstimate(), RubyPort::PioMasterPort::recvRangeChange(), BaseXBar::recvRangeChange(), RefCountingPtr< MinorDynInst >::RefCountingPtr(), sc_gem5::reportifyException(), SimpleBusAT< NR_OF_INITIATORS, NR_OF_TARGETS >::ResponseThread(), SC_MODULE(), sc_dt::scfx_pow2(), Cache::sendMSHRQueuePacket(), sc_dt::sc_concref_r< X, Y >::set_cword(), sc_dt::sc_concref_r< X, Y >::set_word(), AlphaISA::RemoteGDB::AlphaGdbRegCache::setRegs(), PowerISA::RemoteGDB::PowerGdbRegCache::setRegs(), SparcISA::RemoteGDB::SPARCGdbRegCache::setRegs(), MipsISA::RemoteGDB::MipsGdbRegCache::setRegs(), ArmISA::RemoteGDB::AArch32GdbRegCache::setRegs(), SparcISA::RemoteGDB::SPARC64GdbRegCache::setRegs(), ArmISA::RemoteGDB::AArch64GdbRegCache::setRegs(), LSQUnit< Impl >::LSQEntry::setRequest(), DRAMCtrl::startup(), LSQ< Impl >::LSQRequest::taskId(), TEST(), LinearSystem::toStr(), sc_dt::vec_div_small(), sc_dt::vec_rem_on_small(), sc_dt::vec_rem_small(), sc_dt::vec_reverse(), LSQ< Impl >::LSQRequest::~LSQRequest(), and QTIsaac< ALPHA >::randctx::~randctx().

◆ r0

Bitfield<3> MipsISA::r0

Definition at line 138 of file pra_constants.hh.

◆ random

MipsISA::random

Definition at line 52 of file pra_constants.hh.

Referenced by StreamGen::create(), and StatTest::run().

◆ re

Bitfield<25> MipsISA::re

Definition at line 113 of file pra_constants.hh.

◆ ReturnAddressReg

const int MipsISA::ReturnAddressReg = 31

Definition at line 121 of file registers.hh.

Referenced by MipsISA::StackTrace::decodePrologue(), and skipFunction().

◆ ReturnValueReg

const int MipsISA::ReturnValueReg = 2

Definition at line 114 of file registers.hh.

◆ rev

Bitfield<7, 0> MipsISA::rev

Definition at line 206 of file pra_constants.hh.

◆ ripl

Bitfield<15, 10> MipsISA::ripl

Definition at line 186 of file pra_constants.hh.

◆ rnst

Bitfield<24, 23> MipsISA::rnst

Definition at line 87 of file mt_constants.hh.

◆ s

Bitfield< 2 > MipsISA::s

Definition at line 81 of file dt_constants.hh.

◆ sa

Bitfield<3, 0> MipsISA::sa

Definition at line 258 of file pra_constants.hh.

Referenced by dspExtr(), dspMulq(), dspPrece(), dspPrecrSra(), and dspShra().

◆ scs

Bitfield<18> MipsISA::scs

Definition at line 70 of file mt_constants.hh.

◆ SIMD_LOG2N

const uint32_t MipsISA::SIMD_LOG2N[SIMD_NUM_FMTS] = { 6, 5, 4, 3 }

Definition at line 101 of file dsp.hh.

Referenced by dspShll(), dspShra(), and dspShrl().

◆ SIMD_MAX_VALS

const uint32_t MipsISA::SIMD_MAX_VALS = 4

Definition at line 95 of file dsp.hh.

Referenced by dspAbs(), dspAdd(), dspAddh(), dspCmp(), dspCmpg(), dspCmpgd(), dspDpa(), dspDpaq(), dspDps(), dspDpsq(), dspMaq(), dspMul(), dspMuleq(), dspMuleu(), dspMulq(), dspMulsa(), dspMulsaq(), dspPack(), dspPick(), dspPrece(), dspPrecrq(), dspPrecrqu(), dspPrecrSra(), dspShll(), dspShra(), dspShrl(), dspSub(), and dspSubh().

◆ SIMD_NBITS

const uint32_t MipsISA::SIMD_NBITS[SIMD_NUM_FMTS] = { 64, 32, 16, 8 }

Definition at line 99 of file dsp.hh.

Referenced by dspMulq(), dspPrece(), dspPrecrqu(), signExtend(), simdPack(), and simdUnpack().

◆ SIMD_NVALS

const uint32_t MipsISA::SIMD_NVALS[SIMD_NUM_FMTS] = { 1, 1, 2, 4 }

Definition at line 97 of file dsp.hh.

Referenced by dspAbs(), dspAdd(), dspAddh(), dspCmp(), dspCmpg(), dspCmpgd(), dspDpa(), dspDpaq(), dspDps(), dspDpsq(), dspMaq(), dspMul(), dspMuleq(), dspMuleu(), dspMulq(), dspMulsaq(), dspPick(), dspPrece(), dspPrecrSra(), dspShll(), dspShra(), dspShrl(), dspSub(), dspSubh(), simdPack(), and simdUnpack().

◆ sl

Bitfield<7, 4> MipsISA::sl

Definition at line 257 of file pra_constants.hh.

◆ sm

Bitfield<1> MipsISA::sm

Definition at line 272 of file pra_constants.hh.

Referenced by CPA::hwWe(), and AnnotateDumpCallback::process().

◆ sp

Bitfield<4> MipsISA::sp

Definition at line 269 of file pra_constants.hh.

◆ sr

Bitfield<20> MipsISA::sr

Definition at line 118 of file pra_constants.hh.

Referenced by DistIface::SyncEvent::process().

◆ ss

Bitfield<11, 8> MipsISA::ss

Definition at line 256 of file pra_constants.hh.

◆ sst

Bitfield<8> MipsISA::sst

Definition at line 62 of file dt_constants.hh.

◆ ssv0

Bitfield<3, 0> MipsISA::ssv0

Definition at line 173 of file pra_constants.hh.

◆ ssv1

Bitfield<7, 4> MipsISA::ssv1

Definition at line 172 of file pra_constants.hh.

◆ ssv2

Bitfield<11, 8> MipsISA::ssv2

Definition at line 171 of file pra_constants.hh.

◆ ssv3

Bitfield<15, 12> MipsISA::ssv3

Definition at line 170 of file pra_constants.hh.

◆ ssv4

Bitfield<19, 16> MipsISA::ssv4

Definition at line 169 of file pra_constants.hh.

◆ ssv5

Bitfield<23, 20> MipsISA::ssv5

Definition at line 168 of file pra_constants.hh.

◆ ssv6

Bitfield<27, 24> MipsISA::ssv6

Definition at line 167 of file pra_constants.hh.

◆ ssv7

MipsISA::ssv7

Definition at line 166 of file pra_constants.hh.

◆ StackPointerReg

const int MipsISA::StackPointerReg = 29

Definition at line 119 of file registers.hh.

◆ stlb

Bitfield<2> MipsISA::stlb

Definition at line 43 of file mt_constants.hh.

◆ su

Bitfield<15, 12> MipsISA::su

Definition at line 255 of file pra_constants.hh.

◆ sx

Bitfield<6> MipsISA::sx

Definition at line 134 of file pra_constants.hh.

◆ syp

Bitfield<2, 0> MipsISA::syp

Definition at line 101 of file dt_constants.hh.

◆ SyscallPseudoReturnReg

const int MipsISA::SyscallPseudoReturnReg = 3

Definition at line 123 of file registers.hh.

◆ SyscallSuccessReg

const int MipsISA::SyscallSuccessReg = 7

Definition at line 112 of file registers.hh.

◆ ta

Bitfield<19, 16> MipsISA::ta

Definition at line 254 of file pra_constants.hh.

◆ targTC

Bitfield<7, 0> MipsISA::targTC

Definition at line 63 of file mt_constants.hh.

◆ tb

Bitfield<27> MipsISA::tb

Definition at line 76 of file dt_constants.hh.

Referenced by SC_MODULE().

◆ tbe

Bitfield<17> MipsISA::tbe

Definition at line 80 of file mt_constants.hh.

Referenced by SparcISA::vtophys().

◆ tbi

Bitfield<4> MipsISA::tbi

Definition at line 99 of file dt_constants.hh.

◆ tbu

Bitfield<3> MipsISA::tbu

Definition at line 100 of file dt_constants.hh.

◆ tca

Bitfield<15> MipsISA::tca

Definition at line 54 of file mt_constants.hh.

◆ tcnum

Bitfield<19, 12> MipsISA::tcnum

Definition at line 96 of file dt_constants.hh.

◆ tcs

Bitfield<19> MipsISA::tcs

Definition at line 69 of file mt_constants.hh.

◆ tcu

MipsISA::tcu

Definition at line 85 of file mt_constants.hh.

◆ tcv

Bitfield<20> MipsISA::tcv

Definition at line 95 of file dt_constants.hh.

◆ tds

Bitfield<21> MipsISA::tds

Definition at line 88 of file mt_constants.hh.

◆ te

Bitfield<15> MipsISA::te

Definition at line 62 of file mt_constants.hh.

◆ tfcr

Bitfield<3> MipsISA::tfcr

Definition at line 86 of file dt_constants.hh.

◆ ti

Bitfield<30> MipsISA::ti

Definition at line 178 of file pra_constants.hh.

Referenced by DumpStatsPCEvent::getTaskDetails(), DumpStatsPCEvent64::getTaskDetails(), LinuxAlphaSystem::PrintThreadInfo::process(), LinuxMipsSystem::PrintThreadInfo::process(), AnnotateDumpCallback::process(), and ArmISA::TLB::setTestInterface().

◆ tim

Bitfield<1> MipsISA::tim

Definition at line 88 of file dt_constants.hh.

◆ tksu

Bitfield<12, 11> MipsISA::tksu

Definition at line 93 of file mt_constants.hh.

◆ tl

Bitfield< 0 > MipsISA::tl

Definition at line 253 of file pra_constants.hh.

Referenced by SparcISA::copyMiscRegs(), SparcISA::SparcFaultBase::invoke(), SparcISA::ISA::setFSReg(), SparcISA::TLB::translateData(), and SparcISA::TLB::translateInst().

◆ tlbs

Bitfield<29> MipsISA::tlbs

Definition at line 50 of file mt_constants.hh.

◆ tlsm

Bitfield<2> MipsISA::tlsm

Definition at line 87 of file dt_constants.hh.

◆ tmx

Bitfield<27> MipsISA::tmx

Definition at line 86 of file mt_constants.hh.

◆ TotalNumRegs

const int MipsISA::TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs

Definition at line 284 of file registers.hh.

◆ ts

Bitfield< 27, 24 > MipsISA::ts

Definition at line 117 of file pra_constants.hh.

◆ tu

Bitfield<30, 28> MipsISA::tu

Definition at line 251 of file pra_constants.hh.

Referenced by sc_core::sc_set_default_time_unit(), sc_core::sc_set_time_resolution(), sc_core::sc_time::sc_time(), and sc_gem5::TraceFile::set_time_unit().

◆ tup

Bitfield<1> MipsISA::tup

Definition at line 131 of file dt_constants.hh.

◆ u

Bitfield< 3 > MipsISA::u

Definition at line 82 of file dt_constants.hh.

◆ um

Bitfield<4> MipsISA::um

Definition at line 137 of file pra_constants.hh.

◆ USegBase

const Addr MipsISA::USegBase = ULL(0x0)

Definition at line 68 of file isa_traits.hh.

◆ USegEnd

const Addr MipsISA::USegEnd = ULL(0x7FFFFFFF)

Definition at line 69 of file isa_traits.hh.

◆ ut

Bitfield<30> MipsISA::ut

Definition at line 75 of file dt_constants.hh.

◆ ux

Bitfield<5> MipsISA::ux

Definition at line 135 of file pra_constants.hh.

◆ v

Bitfield<1> MipsISA::v

Definition at line 60 of file pra_constants.hh.

◆ VABits

const unsigned MipsISA::VABits = 32

Definition at line 96 of file isa_traits.hh.

◆ vaddr

MipsISA::vaddr

Definition at line 277 of file pra_constants.hh.

Referenced by ArmISA::TLB::checkPermissions(), ArmISA::TLB::checkPermissions64(), Process::clone(), PseudoInst::decodeAddrOffset(), HsailISA::AtomicInst< MemDataType, AddrOperandType, NumSrcOperands, HasDst >::execAtomic(), HsailISA::StInst< MemDataType, SrcDataType, AddrOperandType >::execSt(), AlphaISA::TLB::flushAddr(), GenericPageTableFault::getFaultVAddr(), GenericAlignmentFault::getFaultVAddr(), AlphaISA::TLB::getsize(), MipsISA::TLB::getsize(), PowerISA::TLB::getsize(), ArmISA::TLB::getsize(), ArmISA::TLB::getTE(), X86ISA::GpuTLB::handleFuncTranslationReturn(), X86ISA::GpuTLB::handleTranslationReturn(), HsailISA::LdInst< MemDataType, DestDataType, AddrOperandType >::initiateAcc(), FetchUnit::initiateFetch(), ExecContext::initiateMemAMO(), AlphaISA::TLB::insert(), GenericPageTableFault::invoke(), GenericAlignmentFault::invoke(), AlphaISA::DtbFault::invoke(), AlphaISA::NDtbMissFault::invoke(), SparcISA::FastInstructionAccessMMUMiss::invoke(), SparcISA::FastDataAccessMMUMiss::invoke(), AlphaISA::ItbPageFault::invoke(), X86ISA::Walker::WalkerState::name(), Iris::ThreadContext::noThrow(), EmulationPageTable::pageOffset(), Process::progName(), ArmISA::PteAddr(), X86ISA::GpuTLB::CpuSidePort::recvFunctional(), ComputeUnit::DTLBPort::recvReqRetry(), ComputeUnit::ITLBPort::recvReqRetry(), ComputeUnit::DTLBPort::recvTimingResp(), ComputeUnit::sendRequest(), MipsISA::TlbFault< TlbInvalidFault >::setTlbExceptionState(), X86ISA::Walker::WalkerState::setupWalk(), Request::setVirt(), BaseTLB::Translation::squashed(), X86ISA::Walker::WalkerState::stepWalk(), AlphaISA::TlbEntry::TlbEntry(), SparcISA::TlbEntry::TlbEntry(), X86ISA::GpuTLB::tlbLookup(), X86ISA::TLB::translate(), X86ISA::GpuTLB::translate(), SparcISA::TLB::translateData(), ArmISA::TLB::translateFs(), Iris::TLB::translateFunctional(), SparcISA::TLB::translateInst(), X86ISA::TLB::translateInt(), X86ISA::GpuTLB::translateInt(), ArmISA::TLB::translateSe(), X86ISA::GpuTLB::translationReturn(), MultiLevelPageTable< EntryTypes >::unmap(), EmulationPageTable::unserialize(), AlphaISA::TlbEntry::updateVaddr(), X86ISA::vtophys(), and AlphaISA::vtophys().

◆ VAddrImplMask

const Addr MipsISA::VAddrImplMask = (ULL(1) << VABits) - 1

Definition at line 98 of file isa_traits.hh.

Referenced by VAddrImpl().

◆ VAddrUnImplMask

const Addr MipsISA::VAddrUnImplMask = ~VAddrImplMask

Definition at line 99 of file isa_traits.hh.

◆ validModes

Bitfield<6, 5> MipsISA::validModes

Definition at line 98 of file dt_constants.hh.

◆ VecPredRegHasPackedRepr

constexpr bool MipsISA::VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr

Definition at line 299 of file registers.hh.

◆ VecPredRegSizeBits

constexpr size_t MipsISA::VecPredRegSizeBits = ::DummyVecPredRegSizeBits

Definition at line 298 of file registers.hh.

◆ VecRegSizeBytes

constexpr size_t MipsISA::VecRegSizeBytes = ::DummyVecRegSizeBytes

Definition at line 292 of file registers.hh.

◆ veic

Bitfield<6> MipsISA::veic

Definition at line 267 of file pra_constants.hh.

◆ vi

Bitfield<3> MipsISA::vi

Definition at line 227 of file pra_constants.hh.

◆ vint

Bitfield<5> MipsISA::vint

Definition at line 268 of file pra_constants.hh.

◆ vpa

Bitfield<0> MipsISA::vpa

Definition at line 74 of file mt_constants.hh.

◆ vpc

Bitfield<1> MipsISA::vpc

Definition at line 44 of file mt_constants.hh.

◆ vpn2

Bitfield<39, 13> MipsISA::vpn2

Definition at line 99 of file pra_constants.hh.

◆ vpn2x

Bitfield<12, 11> MipsISA::vpn2x

Definition at line 100 of file pra_constants.hh.

◆ vs

Bitfield<9, 5> MipsISA::vs

Definition at line 148 of file pra_constants.hh.

Referenced by sc_dt::compare_unsigned(), sc_dt::operator%(), sc_dt::operator&(), sc_dt::operator+(), sc_dt::operator-(), sc_dt::operator<(), sc_dt::operator==(), sc_dt::operator>=(), sc_dt::operator^(), and sc_dt::operator|().

◆ w

Bitfield< 30 > MipsISA::w

Definition at line 280 of file pra_constants.hh.

Referenced by ComputeUnit::AllAtBarrier(), HsailISA::Call::calcAddr(), RegAddrOperand< RegOperandType >::calcLane(), RegAddrOperand< RegOperandType >::calcVector(), ArmISA::TLB::checkPermissions64(), HsailISA::LdInst< MemDataType, DestDataType, AddrOperandType >::completeAcc(), HsailISA::AtomicInst< MemDataType, AddrOperandType, NumSrcOperands, HasDst >::completeAcc(), LocalMemPipeline::exec(), GlobalMemPipeline::exec(), HsailISA::Call::execPseudoInst(), HsailISA::BrnInstBase< SRegOperand >::execute(), HsailISA::LdaInst< DestDataType, AddrOperandType >::execute(), HsailISA::CbrInstBase< SRegOperand >::execute(), HsailISA::BrInstBase< SRegOperand >::execute(), HsailISA::LdInst< MemDataType, DestDataType, AddrOperandType >::execute(), HsailISA::Ret::execute(), HsailISA::Barrier::execute(), HsailISA::MemFence::execute(), HsailISA::StInst< MemDataType, SrcDataType, AddrOperandType >::execute(), HsailISA::AtomicInst< MemDataType, AddrOperandType, NumSrcOperands, HasDst >::execute(), ImmOperand< SrcCType >::get(), RegOrImmOperand< RegOperand, T >::get(), sc_dt::sc_bv_base::get_cword(), Packet::getConstPtr(), PowerModel::getDynamicPower(), MultiperspectivePerceptron::GHISTPATH::getHash(), MultiperspectivePerceptron::SGHISTPATH::getHash(), PowerModel::getStaticPower(), SRegOperand::getTarget(), HsailISA::Call::MagicAtomicNRAddGlobalU32Reg(), HsailISA::Call::MagicAtomicNRAddGroupU32Reg(), HsailISA::Call::MagicMaskLower(), HsailISA::Call::MagicMaskUpper(), HsailISA::Call::MagicMostSigBroadcast(), HsailISA::Call::MagicMostSigThread(), HsailISA::Call::MagicPanic(), HsailISA::Call::MagicPrefixSum(), HsailISA::Call::MagicPrintLane(), HsailISA::Call::MagicPrintLane64(), HsailISA::Call::MagicPrintWF32(), HsailISA::Call::MagicPrintWF32ID(), HsailISA::Call::MagicPrintWF64(), HsailISA::Call::MagicPrintWFFloat(), HsailISA::Call::MagicPrintWFID64(), HsailISA::Call::MagicReduction(), HsailISA::Call::MagicXactCasLd(), ConditionRegisterState::numRegs(), VectorRegisterFile::numRegs(), sc_dt::operator<<(), sc_dt::sc_bitref< X >::operator^=(), sc_gem5::VcdTraceScope::output(), sc_gem5::VcdTraceValFinite< T >::output(), sc_gem5::VcdTraceValFxnum< T >::output(), sc_gem5::VcdTraceValInt< T >::output(), ComputeUnit::DataPort::recvTimingResp(), ComputeUnit::DTLBPort::recvTimingResp(), FutexMap::requeue(), SC_MODULE(), sc_dt::sc_lv_base::set_cword(), sc_dt::sc_bv_base::set_word(), sc_dt::sc_lv_base::set_word(), sc_dt::sc_subref_r< X >::size(), sc_dt::sc_concref_r< X, Y >::size(), ComputeUnit::StartWorkgroup(), sc_dt::sc_proxy< sc_subref_r< X > >::to_anything_signed(), sc_dt::sc_proxy< sc_subref_r< X > >::to_anything_unsigned(), sc_dt::sc_proxy< sc_subref_r< X > >::to_uint64(), sc_dt::vec_mul(), ComputeUnit::wfSize(), sc_gem5::ScEvent::when(), VGic::writeVCpu(), MPP_StatisticalCorrector::BranchInfo::~BranchInfo(), and GpuDispatcher::~GpuDispatcher().

◆ wired

MipsISA::wired

Definition at line 88 of file pra_constants.hh.

◆ wp

Bitfield<22> MipsISA::wp

Definition at line 184 of file pra_constants.hh.

◆ wr

Bitfield<3> MipsISA::wr

Definition at line 243 of file pra_constants.hh.

Referenced by SC_MODULE().

◆ xtc

Bitfield<28, 21> MipsISA::xtc

Definition at line 68 of file mt_constants.hh.

◆ ZeroReg

const int MipsISA::ZeroReg = 0

Definition at line 110 of file registers.hh.

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