base.hh

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/*
 * Copyright (c) 2014, 2016-2017 ARM Limited
 * All rights reserved
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 * Authors: Andreas Sandberg
 */

#ifndef __DEV_VIRTIO_BASE_HH__
#define __DEV_VIRTIO_BASE_HH__

#include "arch/isa_traits.hh"
#include "base/bitunion.hh"
#include "base/callback.hh"
#include "dev/virtio/virtio_ring.h"
#include "mem/port_proxy.hh"
#include "sim/sim_object.hh"

struct VirtIODeviceBaseParams;
struct VirtIODummyDeviceParams;

class VirtQueue;

template <> inline vring_used_elem
swap_byte(vring_used_elem v) {
    v.id = swap_byte(v.id);
    v.len = swap_byte(v.len);
    return v;
}

template <> inline vring_desc
swap_byte(vring_desc v) {
    v.addr = swap_byte(v.addr);
    v.len = swap_byte(v.len);
    v.flags = swap_byte(v.flags);
    v.next = swap_byte(v.next);
    return v;
}

class VirtDescriptor
{
  public:
    typedef uint16_t Index;

    VirtDescriptor(PortProxy &memProxy, ByteOrder bo,
            VirtQueue &queue, Index index);
    // WORKAROUND: The noexcept declaration works around a bug where
    // gcc 4.7 tries to call the wrong constructor when emplacing
    // something into a vector.
    VirtDescriptor(VirtDescriptor &&other) noexcept;
    ~VirtDescriptor() noexcept;

    VirtDescriptor &operator=(VirtDescriptor &&rhs) noexcept;

    Index index() const { return _index; }

    void update();

    void updateChain();
    void dump() const;
    void dumpChain() const;
    void read(size_t offset, uint8_t *dst, size_t size) const;
    void write(size_t offset, const uint8_t *src, size_t size);
    size_t size() const { return desc.len; }

    bool hasNext() const { return desc.flags & VRING_DESC_F_NEXT; }
    VirtDescriptor *next() const;

    bool isIncoming() const { return !isOutgoing(); }
    bool isOutgoing() const { return desc.flags & VRING_DESC_F_WRITE; }


    void chainRead(size_t offset, uint8_t *dst, size_t size) const;
    void chainWrite(size_t offset, const uint8_t *src, size_t size);
    size_t chainSize() const;
  private:
    // Remove default constructor
    VirtDescriptor();
    // Prevent copying
    VirtDescriptor(const VirtDescriptor &other);

    PortProxy *memProxy;
    VirtQueue *queue;

    ByteOrder byteOrder;

    Index _index;

    vring_desc desc;
};

class VirtQueue : public Serializable {
public:
    virtual ~VirtQueue() {};

    void serialize(CheckpointOut &cp) const override;
    void unserialize(CheckpointIn &cp) override;

    void setAddress(Addr address);
    Addr getAddress() const { return _address; }

     uint16_t getSize() const { return _size; }

    VirtDescriptor *getDescriptor(VirtDescriptor::Index index) {
        return &descriptors[index];
    }
    VirtDescriptor *consumeDescriptor();
    void produceDescriptor(VirtDescriptor *desc, uint32_t len);
    virtual void onNotify();
    virtual void onNotifyDescriptor(VirtDescriptor *desc) {};
    void dump() const;
    static const Addr ALIGN_BITS = 12;
    static const Addr ALIGN_SIZE = 1 << ALIGN_BITS;
  protected:
    VirtQueue(PortProxy &proxy, ByteOrder bo, uint16_t size);

    ByteOrder byteOrder;

  private:
    VirtQueue();

    const uint16_t _size;
    Addr _address;
    PortProxy &memProxy;

  private:
    template<typename T>
    class VirtRing
    {
      public:
        typedef uint16_t Flags;
        typedef uint16_t Index;

        struct Header {
            Flags flags;
            Index index;
        } M5_ATTR_PACKED;

        VirtRing<T>(PortProxy &proxy, ByteOrder bo, uint16_t size) :
            header{0, 0}, ring(size), _proxy(proxy), _base(0), byteOrder(bo)
        {}

        void setAddress(Addr addr) { _base = addr; }

        void
        readHeader()
        {
            assert(_base != 0);
            _proxy.readBlob(_base, &header, sizeof(header));
            header.flags = gtoh(header.flags, byteOrder);
            header.index = gtoh(header.index, byteOrder);
        }

        void
        writeHeader()
        {
            Header out;
            assert(_base != 0);
            out.flags = htog(header.flags, byteOrder);
            out.index = htog(header.index, byteOrder);
            _proxy.writeBlob(_base, &out, sizeof(out));
        }

        void
        read()
        {
            readHeader();

            /* Read and byte-swap the elements in the ring */
            T temp[ring.size()];
            _proxy.readBlob(_base + sizeof(header),
                            temp, sizeof(T) * ring.size());
            for (int i = 0; i < ring.size(); ++i)
                ring[i] = gtoh(temp[i], byteOrder);
        }

        void
        write()
        {
            assert(_base != 0);
            /* Create a byte-swapped copy of the ring and write it to
             * guest memory. */
            T temp[ring.size()];
            for (int i = 0; i < ring.size(); ++i)
                temp[i] = htog(ring[i], byteOrder);
            _proxy.writeBlob(_base + sizeof(header),
                             temp, sizeof(T) * ring.size());
            writeHeader();
        }

        Header header;
        std::vector<T> ring;

      private:
        // Remove default constructor
        VirtRing<T>();

        PortProxy &_proxy;
        Addr _base;
        ByteOrder byteOrder;
    };

    VirtRing<VirtDescriptor::Index> avail;
    VirtRing<struct vring_used_elem> used;

    uint16_t _last_avail;

    std::vector<VirtDescriptor> descriptors;
};

class VirtIODeviceBase : public SimObject
{
  public:
    typedef uint16_t QueueID;
    typedef uint32_t FeatureBits;
    typedef uint16_t VirtAddress;
    typedef uint16_t DeviceId;

    BitUnion8(DeviceStatus)
        Bitfield<7> failed;
        Bitfield<2> driver_ok;
        Bitfield<1> driver;
        Bitfield<0> acknowledge;
    EndBitUnion(DeviceStatus)

    typedef VirtIODeviceBaseParams Params;
    VirtIODeviceBase(Params *params, DeviceId id, size_t config_size,
                     FeatureBits features);
    virtual ~VirtIODeviceBase();

  public:
    void serialize(CheckpointOut &cp) const override;
    void unserialize(CheckpointIn &cp) override;
  protected:
    void kick() {
        assert(transKick);
        transKick->process();
    };

    void registerQueue(VirtQueue &queue);


    FeatureBits guestFeatures;
  public:
    virtual void readConfig(PacketPtr pkt, Addr cfgOffset);
    virtual void writeConfig(PacketPtr pkt, Addr cfgOffset);

    virtual void reset();
  protected:
    void readConfigBlob(PacketPtr pkt, Addr cfgOffset, const uint8_t *cfg);

    void writeConfigBlob(PacketPtr pkt, Addr cfgOffset, uint8_t *cfg);

    ByteOrder byteOrder;

  public:
    void registerKickCallback(Callback *c) {
        assert(!transKick);
        transKick = c;
    }


    void onNotify(QueueID index);


    void setQueueSelect(QueueID idx) { _queueSelect = idx; }
    QueueID getQueueSelect() const { return _queueSelect; }

    void setQueueAddress(uint32_t address);
    uint32_t getQueueAddress() const;

    uint16_t getQueueSize() const { return getCurrentQueue().getSize(); }

    void setDeviceStatus(DeviceStatus status);

    DeviceStatus getDeviceStatus() const { return _deviceStatus; }

    void setGuestFeatures(FeatureBits features);

    FeatureBits getGuestFeatures() const { return guestFeatures; }

    const DeviceId deviceId;

    const size_t configSize;

    const FeatureBits deviceFeatures;
  private:
    const VirtQueue &getCurrentQueue() const;
    VirtQueue &getCurrentQueue();

    DeviceStatus _deviceStatus;

    QueueID _queueSelect;

    std::vector<VirtQueue *> _queues;

    Callback *transKick;
};

class VirtIODummyDevice : public VirtIODeviceBase
{
  public:
    VirtIODummyDevice(VirtIODummyDeviceParams *params);

  protected:
    static const DeviceId ID_INVALID = 0x00;
};

#endif // __DEV_VIRTIO_BASE_HH__