Prefetcher.hh

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/*
 * Copyright (c) 1999-2012 Mark D. Hill and David A. Wood
 * All rights reserved.
 *
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 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
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 * documentation and/or other materials provided with the distribution;
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 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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#ifndef __MEM_RUBY_STRUCTURES_PREFETCHER_HH__
#define __MEM_RUBY_STRUCTURES_PREFETCHER_HH__

// Implements Power 4 like prefetching

#include <bitset>

#include "base/statistics.hh"
#include "mem/ruby/common/Address.hh"
#include "mem/ruby/network/MessageBuffer.hh"
#include "mem/ruby/slicc_interface/AbstractController.hh"
#include "mem/ruby/slicc_interface/RubyRequest.hh"
#include "mem/ruby/system/RubySystem.hh"
#include "params/Prefetcher.hh"
#include "sim/sim_object.hh"
#include "sim/system.hh"

#define MAX_PF_INFLIGHT 8

class PrefetchEntry
{
    public:
        PrefetchEntry()
        {
            // default: 1 cache-line stride
            m_stride   = (1 << RubySystem::getBlockSizeBits());
            m_use_time = Cycles(0);
            m_is_valid = false;
        }

        Addr m_address;

        int m_stride;

        Cycles m_use_time;

        bool m_is_valid;

        RubyRequestType m_type;

        std::bitset<MAX_PF_INFLIGHT> requestIssued;
        std::bitset<MAX_PF_INFLIGHT> requestCompleted;
};

class Prefetcher : public SimObject
{
    public:
        typedef PrefetcherParams Params;
        Prefetcher(const Params *p);
        ~Prefetcher();

        void issueNextPrefetch(Addr address, PrefetchEntry *stream);
        void observePfHit(Addr address);
        void observePfMiss(Addr address);

        void observeMiss(Addr address, const RubyRequestType& type);

        void print(std::ostream& out) const;
        void setController(AbstractController *_ctrl)
        { m_controller = _ctrl; }

        void regStats();

    private:
        uint32_t getLRUindex(void);

        void clearNonunitEntry(uint32_t index);

        void initializeStream(Addr address, int stride,
            uint32_t index, const RubyRequestType& type);

        PrefetchEntry* getPrefetchEntry(Addr address,
            uint32_t &index);

        bool accessUnitFilter(std::vector<Addr>& filter_table,
            uint32_t *hit_table, uint32_t &index, Addr address,
            int stride, bool &alloc);

        bool accessNonunitFilter(Addr address, int *stride,
            bool &alloc);

        Addr pageAddress(Addr addr) const;

        uint32_t m_num_streams;
        std::vector<PrefetchEntry> m_array;

        uint32_t m_train_misses;
        uint32_t m_num_startup_pfs;
        uint32_t m_num_unit_filters;
        uint32_t m_num_nonunit_filters;

        std::vector<Addr> m_unit_filter;
        uint32_t m_unit_filter_index;
        uint32_t *m_unit_filter_hit;

        std::vector<Addr> m_negative_filter;
        uint32_t m_negative_filter_index;
        uint32_t *m_negative_filter_hit;

        std::vector<Addr> m_nonunit_filter;
        int *m_nonunit_stride;
        uint32_t *m_nonunit_hit;
        uint32_t m_nonunit_index;

        bool m_prefetch_cross_pages;

        AbstractController *m_controller;

        const Addr m_page_shift;

        Stats::Scalar numMissObserved;
        Stats::Scalar numAllocatedStreams;
        Stats::Scalar numPrefetchRequested;
        Stats::Scalar numPrefetchAccepted;
        Stats::Scalar numDroppedPrefetches;
        Stats::Scalar numHits;
        Stats::Scalar numPartialHits;
        Stats::Scalar numPagesCrossed;
        Stats::Scalar numMissedPrefetchedBlocks;
};

#endif // __MEM_RUBY_STRUCTURES_PREFETCHER_HH__