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decoder.hh
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40  * Authors: Gabe Black
41  */
42 
43 #ifndef __ARCH_ARM_DECODER_HH__
44 #define __ARCH_ARM_DECODER_HH__
45 
46 #include <cassert>
47 
48 #include "arch/arm/miscregs.hh"
49 #include "arch/arm/types.hh"
51 #include "base/types.hh"
52 #include "cpu/static_inst.hh"
53 #include "enums/DecoderFlavour.hh"
54 
55 namespace ArmISA
56 {
57 
58 class ISA;
59 class Decoder
60 {
61  protected:
62  //The extended machine instruction being generated
65  bool bigThumb;
66  bool instDone;
67  bool outOfBytes;
68  int offset;
69  bool foundIt;
70  ITSTATE itBits;
71 
72  int fpscrLen;
74 
79  int sveLen;
80 
81  Enums::DecoderFlavour decoderFlavour;
82 
85 
90  void process();
91 
96  void consumeBytes(int numBytes);
97 
98  public: // Decoder API
99  Decoder(ISA* isa = nullptr);
100 
102  void reset();
103 
111  bool needMoreBytes() const { return outOfBytes; }
112 
121  bool instReady() const { return instDone; }
122 
149  void moreBytes(const PCState &pc, Addr fetchPC, MachInst inst);
150 
163 
174  {
175  return defaultCache.decode(this, mach_inst, addr);
176  }
177 
191 
197  void takeOverFrom(Decoder *old) {}
198 
199 
200  public: // ARM-specific decoder state manipulation
201  void setContext(FPSCR fpscr)
202  {
203  fpscrLen = fpscr.len;
204  fpscrStride = fpscr.stride;
205  }
206 
207  void setSveLen(uint8_t len)
208  {
209  sveLen = len;
210  }
211 };
212 
213 } // namespace ArmISA
214 
215 #endif // __ARCH_ARM_DECODER_HH__
uint32_t MachInst
Definition: types.hh:54
ip6_addr_t addr
Definition: inet.hh:335
void consumeBytes(int numBytes)
Consume bytes by moving the offset into the data word and sanity check the results.
Definition: decoder.cc:146
void takeOverFrom(Decoder *old)
Take over the state from an old decoder when switching CPUs.
Definition: decoder.hh:197
Definition: ccregs.hh:42
int sveLen
SVE vector length, encoded in the same format as the ZCR_EL<x>.LEN bitfields.
Definition: decoder.hh:79
void process()
Pre-decode an instruction from the current state of the decoder.
Definition: decoder.cc:79
ITSTATE itBits
Definition: decoder.hh:70
MachInst data
Definition: decoder.hh:64
StaticInstPtr decodeInst(ExtMachInst mach_inst)
Decode a machine instruction without calling the cache.
Bitfield< 4 > pc
static GenericISA::BasicDecodeCache defaultCache
A cache of decoded instruction objects.
Definition: decoder.hh:84
bool outOfBytes
Definition: decoder.hh:67
bool instReady() const
Is an instruction ready to be decoded?
Definition: decoder.hh:121
Bitfield< 18, 16 > len
StaticInstPtr decode(ArmISA::PCState &pc)
Decode an instruction or fetch it from the code cache.
Definition: decoder.cc:174
StaticInstPtr decode(TheISA::Decoder *const decoder, TheISA::ExtMachInst mach_inst, Addr addr)
Decode a machine instruction.
Definition: decode_cache.cc:42
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,16,32,64}_t.
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
uint64_t ExtMachInst
Definition: types.hh:41
StaticInstPtr decode(ExtMachInst mach_inst, Addr addr)
Decode a pre-decoded machine instruction.
Definition: decoder.hh:173
bool needMoreBytes() const
Can the decoder accept more data?
Definition: decoder.hh:111
void moreBytes(const PCState &pc, Addr fetchPC, MachInst inst)
Feed data to the decoder.
Definition: decoder.cc:155
Enums::DecoderFlavour decoderFlavour
Definition: decoder.hh:81
GenericISA::SimplePCState< MachInst > PCState
Definition: types.hh:43
Decoder(ISA *isa=nullptr)
Definition: decoder.cc:57
void reset()
Reset the decoders internal state.
Definition: decoder.cc:68
ExtMachInst emi
Definition: decoder.hh:63
void setContext(FPSCR fpscr)
Definition: decoder.hh:201
void setSveLen(uint8_t len)
Definition: decoder.hh:207

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