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pagetable_walker.hh
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39 
40 #ifndef __ARCH_X86_PAGE_TABLE_WALKER_HH__
41 #define __ARCH_X86_PAGE_TABLE_WALKER_HH__
42 
43 #include <vector>
44 
45 #include "arch/x86/pagetable.hh"
46 #include "arch/x86/tlb.hh"
47 #include "base/types.hh"
48 #include "mem/packet.hh"
49 #include "params/X86PagetableWalker.hh"
50 #include "sim/clocked_object.hh"
51 #include "sim/faults.hh"
52 #include "sim/system.hh"
53 
54 class ThreadContext;
55 
56 namespace X86ISA
57 {
58  class Walker : public ClockedObject
59  {
60  protected:
61  // Port for accessing memory
62  class WalkerPort : public MasterPort
63  {
64  public:
65  WalkerPort(const std::string &_name, Walker * _walker) :
66  MasterPort(_name, _walker), walker(_walker)
67  {}
68 
69  protected:
71 
72  bool recvTimingResp(PacketPtr pkt);
73  void recvReqRetry();
74  };
75 
76  friend class WalkerPort;
78 
79  // State to track each walk of the page table
81  {
82  friend class Walker;
83  private:
84  enum State {
87  // Long mode
88  LongPML4, LongPDP, LongPD, LongPTE,
89  // PAE legacy mode
90  PAEPDP, PAEPD, PAEPTE,
91  // Non PAE legacy mode with and without PSE
92  PSEPD, PD, PTE
93  };
94 
95  protected:
101  int dataSize;
102  bool enableNX;
103  unsigned inflight;
111  bool timing;
112  bool retrying;
113  bool started;
114  bool squashed;
115  public:
116  WalkerState(Walker * _walker, BaseTLB::Translation *_translation,
117  const RequestPtr &_req, bool _isFunctional = false) :
118  walker(_walker), req(_req), state(Ready),
119  nextState(Ready), inflight(0),
120  translation(_translation),
121  functional(_isFunctional), timing(false),
122  retrying(false), started(false), squashed(false)
123  {
124  }
125  void initState(ThreadContext * _tc, BaseTLB::Mode _mode,
126  bool _isTiming = false);
127  Fault startWalk();
128  Fault startFunctional(Addr &addr, unsigned &logBytes);
129  bool recvPacket(PacketPtr pkt);
130  unsigned numInflight() const;
131  bool isRetrying();
132  bool wasStarted();
133  bool isTiming();
134  void retry();
135  void squash();
136  std::string name() const {return walker->name();}
137 
138  private:
139  void setupWalk(Addr vaddr);
140  Fault stepWalk(PacketPtr &write);
141  void sendPackets();
142  void endWalk();
143  Fault pageFault(bool present);
144  };
145 
146  friend class WalkerState;
147  // State for timing and atomic accesses (need multiple per walker in
148  // the case of multiple outstanding requests in timing mode)
150  // State for functional accesses (only need one of these per walker)
152 
154  {
157  senderWalk(_senderWalk) {}
158  };
159 
160  public:
161  // Kick off the state machine.
162  Fault start(ThreadContext * _tc, BaseTLB::Translation *translation,
163  const RequestPtr &req, BaseTLB::Mode mode);
165  unsigned &logBytes, BaseTLB::Mode mode);
166  Port &getPort(const std::string &if_name,
167  PortID idx=InvalidPortID) override;
168 
169  protected:
170  // The TLB we're supposed to load.
171  TLB * tlb;
174 
175  // The number of outstanding walks that can be squashed per cycle.
176  unsigned numSquashable;
177 
178  // Wrapper for checking for squashes before starting a translation.
179  void startWalkWrapper();
180 
185 
186  // Functions for dealing with packets.
187  bool recvTimingResp(PacketPtr pkt);
188  void recvReqRetry();
189  bool sendTiming(WalkerState * sendingState, PacketPtr pkt);
190 
191  public:
192 
193  void setTLB(TLB * _tlb)
194  {
195  tlb = _tlb;
196  }
197 
198  typedef X86PagetableWalkerParams Params;
199 
200  const Params *
201  params() const
202  {
203  return static_cast<const Params *>(_params);
204  }
205 
206  Walker(const Params *params) :
207  ClockedObject(params), port(name() + ".port", this),
208  funcState(this, NULL, NULL, true), tlb(NULL), sys(params->system),
209  masterId(sys->getMasterId(this)),
210  numSquashable(params->num_squash_per_cycle),
211  startWalkWrapperEvent([this]{ startWalkWrapper(); }, name())
212  {
213  }
214  };
215 }
216 #endif // __ARCH_X86_PAGE_TABLE_WALKER_HH__
A MasterPort is a specialisation of a BaseMasterPort, which implements the default protocol for the t...
Definition: port.hh:75
Ports are used to interface objects to each other.
Definition: port.hh:60
bool sendTiming(WalkerState *sendingState, PacketPtr pkt)
void recvReqRetry()
Called by the peer if sendTimingReq was called on this peer (causing recvTimingReq to be called on th...
const PortID InvalidPortID
Definition: types.hh:238
X86PagetableWalkerParams Params
Walker(const Params *params)
std::shared_ptr< Request > RequestPtr
Definition: request.hh:83
WalkerState(Walker *_walker, BaseTLB::Translation *_translation, const RequestPtr &_req, bool _isFunctional=false)
Fault start(ThreadContext *_tc, BaseTLB::Translation *translation, const RequestPtr &req, BaseTLB::Mode mode)
WalkerSenderState(WalkerState *_senderWalk)
WalkerPort(const std::string &_name, Walker *_walker)
Bitfield< 7 > present
Definition: misc.hh:994
Definition: system.hh:77
Bitfield< 4, 0 > mode
TLB::Translation * translation
ThreadContext is the external interface to all thread state for anything outside of the CPU...
WalkerState funcState
EventFunctionWrapper startWalkWrapperEvent
Event used to call startWalkWrapper.
STL vector class.
Definition: stl.hh:40
void setTLB(TLB *_tlb)
Fault startFunctional(ThreadContext *_tc, Addr &addr, unsigned &logBytes, BaseTLB::Mode mode)
The ClockedObject class extends the SimObject with a clock and accessor functions to relate ticks to ...
ClockedObject declaration and implementation.
STL list class.
Definition: stl.hh:54
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,16,32,64}_t.
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
uint16_t MasterID
Definition: request.hh:86
virtual const std::string name() const
Definition: sim_object.hh:120
A Packet is used to encapsulate a transfer between two objects in the memory system (e...
Definition: packet.hh:255
const Params * params() const
Bitfield< 15 > system
Definition: misc.hh:999
A virtual base opaque structure used to hold state associated with the packet (e.g., an MSHR), specific to a SimObject that sees the packet.
Definition: packet.hh:403
Mode
Definition: tlb.hh:59
std::vector< PacketPtr > writes
Declaration of the Packet class.
This is exposed globally, independent of the ISA.
Definition: acpi.hh:57
const std::string name() const
Return port name (for DPRINTF).
Definition: port.hh:106
std::list< WalkerState * > currStates
bool recvTimingResp(PacketPtr pkt)
Receive a timing response from the peer.
const SimObjectParams * _params
Cached copy of the object parameters.
Definition: sim_object.hh:110
virtual void initState()
initState() is called on each SimObject when not restoring from a checkpoint.
Definition: sim_object.cc:94
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:237
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
std::shared_ptr< FaultBase > Fault
Definition: types.hh:240
Bitfield< 3 > addr
Definition: types.hh:81

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