exec_context.hh

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 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
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 * modified or unmodified, in source code or in binary form.
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 * Copyright (c) 2002-2005 The Regents of The University of Michigan
 * Copyright (c) 2015 Advanced Micro Devices, Inc.
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 * this software without specific prior written permission.
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 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * Authors: Kevin Lim
 *          Andreas Sandberg
 */

#ifndef __CPU_EXEC_CONTEXT_HH__
#define __CPU_EXEC_CONTEXT_HH__

#include "arch/registers.hh"
#include "base/types.hh"
#include "config/the_isa.hh"
#include "cpu/base.hh"
#include "cpu/reg_class.hh"
#include "cpu/static_inst_fwd.hh"
#include "cpu/translation.hh"
#include "mem/request.hh"

class ExecContext {
  public:
    typedef TheISA::PCState PCState;

    using VecRegContainer = TheISA::VecRegContainer;
    using VecElem = TheISA::VecElem;
    using VecPredRegContainer = TheISA::VecPredRegContainer;

  public:
    virtual RegVal readIntRegOperand(const StaticInst *si, int idx) = 0;

    virtual void setIntRegOperand(const StaticInst *si,
                                  int idx, RegVal val) = 0;

    virtual RegVal readFloatRegOperandBits(const StaticInst *si, int idx) = 0;

    virtual void setFloatRegOperandBits(const StaticInst *si,
                                        int idx, RegVal val) = 0;

    virtual const VecRegContainer&
    readVecRegOperand(const StaticInst *si, int idx) const = 0;

    virtual VecRegContainer&
    getWritableVecRegOperand(const StaticInst *si, int idx) = 0;

    virtual void
    setVecRegOperand(const StaticInst *si, int idx,
                     const VecRegContainer& val) = 0;
    virtual ConstVecLane8
    readVec8BitLaneOperand(const StaticInst *si, int idx) const = 0;

    virtual ConstVecLane16
    readVec16BitLaneOperand(const StaticInst *si, int idx) const = 0;

    virtual ConstVecLane32
    readVec32BitLaneOperand(const StaticInst *si, int idx) const = 0;

    virtual ConstVecLane64
    readVec64BitLaneOperand(const StaticInst *si, int idx) const = 0;

    virtual void setVecLaneOperand(const StaticInst *si, int idx,
            const LaneData<LaneSize::Byte>& val) = 0;
    virtual void setVecLaneOperand(const StaticInst *si, int idx,
            const LaneData<LaneSize::TwoByte>& val) = 0;
    virtual void setVecLaneOperand(const StaticInst *si, int idx,
            const LaneData<LaneSize::FourByte>& val) = 0;
    virtual void setVecLaneOperand(const StaticInst *si, int idx,
            const LaneData<LaneSize::EightByte>& val) = 0;
    virtual VecElem readVecElemOperand(const StaticInst *si,
                                        int idx) const = 0;

    virtual void setVecElemOperand(const StaticInst *si, int idx,
                                   const VecElem val) = 0;
    virtual const VecPredRegContainer&
    readVecPredRegOperand(const StaticInst *si, int idx) const = 0;

    virtual VecPredRegContainer&
    getWritableVecPredRegOperand(const StaticInst *si, int idx) = 0;

    virtual void
    setVecPredRegOperand(const StaticInst *si, int idx,
                         const VecPredRegContainer& val) = 0;
    virtual RegVal readCCRegOperand(const StaticInst *si, int idx) = 0;
    virtual void setCCRegOperand(
            const StaticInst *si, int idx, RegVal val) = 0;
    virtual RegVal readMiscRegOperand(const StaticInst *si, int idx) = 0;
    virtual void setMiscRegOperand(const StaticInst *si,
                                   int idx, RegVal val) = 0;

    virtual RegVal readMiscReg(int misc_reg) = 0;

    virtual void setMiscReg(int misc_reg, RegVal val) = 0;

    virtual PCState pcState() const = 0;
    virtual void pcState(const PCState &val) = 0;
    virtual Fault readMem(Addr addr, uint8_t *data, unsigned int size,
            Request::Flags flags,
            const std::vector<bool>& byte_enable = std::vector<bool>())
    {
        panic("ExecContext::readMem() should be overridden\n");
    }

    virtual Fault initiateMemRead(Addr addr, unsigned int size,
            Request::Flags flags,
            const std::vector<bool>& byte_enable = std::vector<bool>())
    {
        panic("ExecContext::initiateMemRead() should be overridden\n");
    }

    virtual Fault writeMem(uint8_t *data, unsigned int size, Addr addr,
                           Request::Flags flags, uint64_t *res,
                           const std::vector<bool>& byte_enable =
                               std::vector<bool>()) = 0;

    virtual Fault amoMem(Addr addr, uint8_t *data, unsigned int size,
                         Request::Flags flags,
                         AtomicOpFunctorPtr amo_op)
    {
        panic("ExecContext::amoMem() should be overridden\n");
    }

    virtual Fault initiateMemAMO(Addr addr, unsigned int size,
                                 Request::Flags flags,
                                 AtomicOpFunctorPtr amo_op)
    {
        panic("ExecContext::initiateMemAMO() should be overridden\n");
    }

    virtual void setStCondFailures(unsigned int sc_failures) = 0;

    virtual unsigned int readStCondFailures() const = 0;

    virtual void syscall(Fault *fault) = 0;

    virtual ThreadContext *tcBase() = 0;

    virtual bool readPredicate() const = 0;
    virtual void setPredicate(bool val) = 0;
    virtual bool readMemAccPredicate() const = 0;
    virtual void setMemAccPredicate(bool val) = 0;

    virtual void demapPage(Addr vaddr, uint64_t asn) = 0;
    virtual void armMonitor(Addr address) = 0;
    virtual bool mwait(PacketPtr pkt) = 0;
    virtual void mwaitAtomic(ThreadContext *tc) = 0;
    virtual AddressMonitor *getAddrMonitor() = 0;

};

#endif // __CPU_EXEC_CONTEXT_HH__