137 #include <sys/signal.h> 153 #include "blobs/gdb_xml_aarch64_core.hh" 154 #include "blobs/gdb_xml_aarch64_fpu.hh" 155 #include "blobs/gdb_xml_aarch64_target.hh" 156 #include "blobs/gdb_xml_arm_core.hh" 157 #include "blobs/gdb_xml_arm_target.hh" 158 #include "blobs/gdb_xml_arm_vfpv3.hh" 162 #include "debug/GDBAcc.hh" 163 #include "debug/GDBMisc.hh" 174 :
BaseRemoteGDB(_system, tc, _port), regCache32(this), regCache64(this)
187 DPRINTF(GDBAcc,
"acc: %#x mapping is invalid\n", va);
192 DPRINTF(GDBAcc,
"acc: %#x mapping is valid\n", va);
204 DPRINTF(GDBAcc,
"getRegs in remotegdb \n");
206 for (
int i = 0;
i < 31; ++
i)
227 DPRINTF(GDBAcc,
"setRegs in remotegdb \n");
229 for (
int i = 0;
i < 31; ++
i)
231 auto pc_state = context->
pcState();
256 DPRINTF(GDBAcc,
"getRegs in remotegdb \n");
273 r.gpr[15] = context->
pcState().pc();
277 for (
int i = 0;
i < 32;
i++)
286 DPRINTF(GDBAcc,
"setRegs in remotegdb \n");
303 auto pc_state = context->
pcState();
304 pc_state.set(
r.gpr[15]);
316 #define GDB_XML(x, s) \ 317 { x, std::string(reinterpret_cast<const char *>(Blobs::s), \ 319 static const std::map<std::string, std::string> annexMap32{
320 GDB_XML(
"target.xml", gdb_xml_arm_target),
321 GDB_XML(
"arm-core.xml", gdb_xml_arm_core),
322 GDB_XML(
"arm-vfpv3.xml", gdb_xml_arm_vfpv3),
324 static const std::map<std::string, std::string> annexMap64{
325 GDB_XML(
"target.xml", gdb_xml_aarch64_target),
326 GDB_XML(
"aarch64-core.xml", gdb_xml_aarch64_core),
327 GDB_XML(
"aarch64-fpu.xml", gdb_xml_aarch64_fpu),
331 auto it = annexMap.find(annex);
332 if (it == annexMap.end())
virtual void setMiscReg(RegIndex misc_reg, RegVal val)=0
static void output(const char *filename)
AArch32GdbRegCache regCache32
virtual TheISA::PCState pcState() const =0
virtual RegVal readIntReg(RegIndex reg_idx) const =0
AArch64GdbRegCache regCache64
void getRegs(ThreadContext *)
Fill the raw buffer from the registers in the ThreadContext.
virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val)=0
BaseGdbRegCache * gdbRegs()
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
virtual Process * getProcessPtr()=0
bool virtvalid(ThreadContext *tc, Addr vaddr)
Overload hash function for BasicBlockRange type.
ThreadContext is the external interface to all thread state for anything outside of the CPU...
virtual const VecRegContainer & readVecReg(const RegId ®) const =0
void setRegs(ThreadContext *) const
Set the ThreadContext's registers from the values in the raw buffer.
void getRegs(ThreadContext *)
Fill the raw buffer from the registers in the ThreadContext.
This class takes an arbitrary memory region (address/length pair) and generates a series of appropria...
Concrete subclasses of this abstract class represent how the register values are transmitted on the w...
void setRegs(ThreadContext *) const
Set the ThreadContext's registers from the values in the raw buffer.
const int NumVecV8ArchRegs
virtual void setIntReg(RegIndex reg_idx, RegVal val)=0
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
bool done() const
Are we done? That is, did the last call to next() advance past the end of the region?
ThreadContext * context()
EmulationPageTable * pTable
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
Declarations of a non-full system Page Table.
virtual VecRegContainer & getWritableVecReg(const RegId ®)=0
bool acc(Addr addr, size_t len)
const Entry * lookup(Addr vaddr)
Lookup function.
bool getXferFeaturesRead(const std::string &annex, std::string &output)
Get an XML target description.
Register ID: describe an architectural register with its class and index.
bool inAArch64(ThreadContext *tc)
Declaration and inline definition of ChunkGenerator object.
constexpr unsigned NumVecElemPerNeonVecReg